Johannah Mae D.

Abestano Video Sync Generator Targe Wave Behaviour

ECE 195

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Wave Form Views The falling and rising edge of vsync are at 493 and 495. As specified above.

The falling and rising edge of hsync are at 660 and 756 as specified above.

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Counter for vcount returns to 0 after reaching 525-1.

Counter for hcount returns to 0 after reaching 800-1.

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VideoSync_tf.v
`timescale 1ns / 1ps module VideoSync_tf; // Inputs reg reset; reg enable; reg clock; // Outputs wire vsync; wire hsync; // Test Bench Specific integer simulation_max; // Instantiate the Unit Under Test (UUT) VideoSync uut ( .vsync(vsync), .hsync(hsync), .reset(reset), .enable(enable), .clock(clock) ); initial begin /* this variable only applies for limiting * the simulation when in use with xilinx. */ simulation_max = 5; /* reset high, and enable low means a device is off */ reset = 1; enable = 0; /* initialize clock and then do a forever to * oscillate clock source model. */ clock = 0; forever #1 clock = !clock; /* Wait 1 time unit for global reset to finish */ #1; /* reset low, and enable high means turn uut on. */ reset = 0; enable = 1; end /* this part is an advance method for test bench * simulation. use this with caution in your own * code. it simply counts the number of negative * edges on the vsync output of the unit under test * and stops/finishes the simulation when the numner * reaches 5 as initially set for simulation_max. */ always@(negedge vsync) begin simulation_max = simulation_max - 1; if (simulation_max == 0) begin $finish; end end endmodule

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VideoSync.v
`timescale 1ns / 1ps module VideoSync( output reg vsync, output reg hsync, input wire reset, input wire enable, input wire clock ); integer vcount; integer hcount; /* these parameters store important details regarding * the vsync wave behaviour. please refer to documentation * about drawings/specifications. */ parameter vsync_width = 525; parameter vsync_fall = 494; parameter vsync_rise = 495; /* these parameters store important details regarding * the hsync wave behaviour. please refer to documentation * about drawings/specifications. */ parameter hsync_width = 800; parameter hsync_fall = 660; parameter hsync_rise = 756; /* this is the main program loop. which runs every positive * edge of the clock wave input. */ always@(posedge clock) begin /* if the hcount is less than the h width, then continue * incrementing ELSE reset the counter to 0 AND make sure * to increment vcount. and while incrementing vcount, make * sure to test vcount if its less than v width, else reset * vcount to 0. */ if (hcount < hsync_width - 1) begin hcount <= hcount + 1; end else begin hcount <= 0; if (vcount < vsync_width - 1) begin vcount <= vcount + 1; end else begin vcount <= 0; end end /* check when to rise and fall the hsync output wave. */ if (hcount >= hsync_fall && hcount <= hsync_rise) begin hsync <= 0; end else begin hsync <= 1; end /* check when to rise and fall the vsync output wave. */ if (vcount >= vsync_fall && vcount <= vsync_rise) begin vsync <= 0; end else begin vsync <= 1; end

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end /* these are async reset operations. */ always@(posedge reset or negedge reset) begin vcount <= 0; hcount <= 0; vsync <= 1; hsync <= 1; end endmodule

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