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INNOVATIVE CONETION CONTROL TO CLEAR THE TRAFFIC FOR AMBULANCE USING RF
CHAPTER 1
INTRODUCTION
EMBEDDED SYSTEM: An embedded system is a special-purpose system in which the computer is completely encapsulated by or dedicated to the device or system it controls. Unlike a general-purpose computer, such as a personal computer, an embedded system performs one or a few predefined tasks, usually with very specific requirements. Since the system is dedicated to specific tasks, design engineers can optimize it, reducing the size and cost of the product. Embedded systems are often mass-produced, benefiting from economies of scale. Personal digital assistants (PDAs) or handheld computers are generally considered embedded devices because of the nature of their hardware design, even though they are more expandable in software terms. This line of definition continues to blur as devices expand. With the introduction of the OQO Model 2 with the Windows XP operating system and ports such as a USB port both features usually belong to "general purpose computers", the line of nomenclature blurs even more. Physically, embedded systems ranges from portable devices such as digital watches and MP3 players, to large stationary installations like traffic lights, factory controllers, or the systems controlling nuclear power plants. In terms of complexity embedded systems can range from very simple with a single microcontroller chip, to very complex with multiple units, peripherals and networks mounted inside a large chassis or enclosure.
FIG 1.1 : Example of embede system.
Examples of Embedded Systems: Avionics, such as inertial guidance systems, flight control hardware/software and other integrated systems in aircraft and missiles Cellular telephones and telephone switches Engine controllers and antilock brake controllers for automobiles Home automation products, such as thermostats, air conditioners, sprinklers, and security monitoring systems Handheld calculators Handheld computers Household appliances, including microwave ovens, washing machines, television sets, DVD players and recorders Medical equipment Personal digital assistant Videogame consoles Computer peripherals such as routers and printers. Industrial controllers for remote machine operation.
CHAPTER 2
BLOCK DIAGRAM
2.1 TRAFFIC POST BLOCK DIAGRAM
Signal post 1
RF Receiver
Red LED Yellow LED Green LED
Signal post 2
Micro controller
Red LED Yellow LED Green LED
Signal post 3 Red LED Yellow LED Green LED
Signal post 4 Red LED Yellow LED Green LED FIG 2.1 : block diagram of traffic post terminal
2.2 AMBULANCE SECTION BLOCK DIAGRAM
LCD
Key pad
Micro controller
RF transmitter
Buzzer & LED
FIG 2.2 : block diagram of ambulance section
CHAPTER 3
CIRCUIT DESCRIPTION
3.1 SCHEMATIC OF TRAFFIC POST :
L L L L L L L L L
E E E E E E E E E
D D D D D D D D D
4 7 4 7 4 7 4 7 4 7 4 7 4 7 4 7 4 7 3 3
0 E 0 E 0 E 0 E 0 E 0 E 0 E 0 E 0 E p f 1 1 1 1 1 1 1 1 5 4 V C h z C 1 2 0 2 3 4 5 6 7 8 9 U P P P P P P P P 1 1 1 1 1 1 1 1 1 . . . . . . . . A A S C 0 1 2 3 4 5 6 7 L L / A PI / A PI P P N3 N3 3 3 P P .0 0 .1 1 . 2 . 3 3 . 3 . P 3 2 / R3 X D / T6 X D / I 7N T 0 / I 8N T 1 4 /9 T 0 5 /1 T 1 1 . 7 1 2 B U Z Z E R L S 1
4 3 3 M h z
R e c e i v e r
3 3
p f 1 2 M
X T X T R V
1 2 P P 4 7 0 C 2 0 5 1 4 7 0 4 7 0 E E E L L L E E E D D D
T / V C A T
8 9
0 u f 1 0 k
FIG 3.1
: SCHEMATIC DIAGRAM OF TRAFFIC POST
3.2 SCHEMATIC OF AMBULANCE SECTION :

L 1 2 B 4 P P P P P P P 1 1 1 1 1 1 1 . . . . . . . 0 1 2 3 4 5 6 7 0 E U Z L Z E E D 2 3 4 5 6 7 8 9 10 R 1 S 1 V C C 1 0 0 E V 1 5 I P C C
I S
K 2
L C D
7 8 9 1 0 1 1 1 2 1 3 1 4 4 5 6 1 6
R 1 0
V K
K e y p a d
U 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 3 2 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 P P P P P P P P P P P P P P P P
1 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 . . . . . . . . . . . . . . . . 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 N R V P/ P/ P/ P/ P/ P/ P/ P/ / / / / / / / / A0 A0 A0 A0 A0 A0 A0 A0 R T I I T T W R 8. 9. 1. 1. 1. 1. 1. 1. 0 1 20 31 42 53 64 75 3 3/ 3/ 3/ 3/ 3/ 3/ 3/ / 1 .2 .3 .40 .51 .6 .7 .8 . 9 A8 A7 A6 A5 A4 A3 A2 A 0 1 2 3 4 5 6 7 9 8 1 T C 0 1 2 M H z D D D D D D D D 0 1 2 3 4 5 6 7
4 3 3 M h z
T r a n s m i t t e r
P X1 D P X 1D NP 1T NP 1T P0 1 P1 1 P R1 P D1 X X E C S
0 9 A P
L E S E
1 1 1 2 3 A9
I N V
3 U
V T
8 9 S
V C C
5 14
7 S 3 3 p 3f 3 p f 9 V b a t t W K
8 E
H Y
2 - S P D T
1 4 1 4 8
k 1
B 2 2 k
FIG 3.2 : SCHEMATIC OF AMBULANCE SECTION
3.3 AT89C2051 CONTROLLER

Looking back into the history of microcomputers, one would at first come across the development of microprocessor i.e. the processing element, and later on the peripheral devices. The three basic elements-the CPU, I/O devices and memory-have developed in distinct directions. While the CPU has been the proprietary item, the memory devices fall into general-purpose category and the I/O devices may be grouped somewhere in-between. The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmels high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer, which provides a highly flexible and cost-effective solution to many embedded control applications. The AT89C51 provides for 4k EPROM/ROM, 128 byte RAM and 32 I/O lines. It also includes a universal asynchronous receive-transmit (UART) device, two 16-bit timer/counters and elaborate interrupt logic. Lack of multiply and divide instructions which had been always felt in 8-bit microprocessors/micro controllers, has also been taken care of in the 89C51Thus the 89C51 may be called nearly equivalent of the following devices on a single chip: 8085 + 8255 + 8251 + 8253 + 2764 + 6116.
In short, the AT89C51 has the following on-chip facilities: ROM (EPROM on 8751) 128 byte RAM UART 32 input-output port lines Two, 16-bit timer/counters Six interrupt sources and On-chip clock oscillator and power on reset circuitry
Fig 3.3 : AT89C51 internal block diagram SALIENT FEATURES
The 89C51 can be configured to bypass, the internal 4k ROM and run solely with external program memory. For this its external access (EA) pin has to be grounded, which makes it equivalent to 8031. The program store enable (PSEN) signal acts as read pulse for program memory. The data memory is external only and a separate RD* signal is available for reading its contents.
Use of external memory requires that three of its 8-bit ports (out of four) are configured to provide data/address multiplexed bus. Hi address bus and control signals related to external memory use. The RXD and TXD ports of UART also appear on pins 10 and 11 of 8051 and 8031, respectively. One 8-bit port, which is bit addressable and, extremely useful for control applications. The UART utilizes one of the internal timers for generation of baud rate. The crystal used for generation of CPU clock has therefore to be chosen carefully. The 11.0596 MHz crystals; available abundantly, can provide a baud rate of 9600.
The internal RAM utilizes the 256-byte address space and special function registers (SFRs) array, which is separate from external data RAM space of 64k. The 00-7F space is occupied by the RAM and the 80 - FF space by the SFRs. The 128 byte internal RAM has been utilized in the following fashion:
00-IF: Used for four banks of eight registers of 8-bit each. The four banks may be selected by software any time during the program. 20-2F: The 16 bytes may be used as 128 bits of individually addressable locations. These are extremely useful for bit-oriented programs. 30- 7F: This area is used for temporary storage, pointers and stack. On reset, the stack starts at 08 and gets incremented during use. The list of special function registers along with their hex addresses is given.
Table 4.1.1 AT89C51 Address register Addr. Port/Register 80 P0 (Port 0) 81 82 83 88 89 8A 8B 8C 8D 90 98 99 A0 A8 B0 B8 D0 E0 F0 SP (stack pointer) DPH (data pointer High) DPL (data pointer Low) TCON (timer control) TMOD (timer mode) TLO (timer 0 low byte) TL1 (timer 1 low byte) TH0 (timer 0 high byte) TH1 (timer 1 high byte) P1 (port 1) SCON (serial control) SBUF (serial buffer) P2 (port 2) Interrupt enable (IE) P3 (port 3) Interrupt priority (IP) Processor status word (PSW) Accumulator (ACC) B register Table 3.1 AT89C51 SFR
Hardware details
The on chip oscillator of 89C51 can be used to generate system clock. Depending upon version of the device, crystals from 3.5 to 12 MHz may be used for this purpose. The system clock is internally divided by 6 and the resultant time period becomes one processor cycle. The instructions take mostly one or two processor cycles to execute, and very occasionally three processor cycles. The ALE (address latch enable) pulse rate is 16th of the system clock, except during access of internal program memory, and thus can be used for timing purposes. AT89C51 Serial port pins PIN P3.O RXD P3.I TXD P3.2 INTO P3.3 INT1 P3.4 TO P3.5 T1 P3.6 WR P3.7 RD ALTERNATE USE Serial data input Serial data output External interrupt 0 External interrupt 1 External timer 0 input External timer 1 input External memory write pulse External memory read pulse Table 3.2 AT89C51 serial port pins SFR SBUF SBUF TCON-1 TCON- 2 TMOD TMOD ------------
The two internal timers are wired to the system clock and pre scaling factor is decided by the software, apart from the count stored in the two bytes of the timer control registers. One of the counters, as mentioned earlier, is used for generation of baud rate clock for the UART. It would be of interest to know that the 8052 have a third timer, which is usually used for generation of baud rate. The reset input is normally low and taking it high resets the micro controller, In the present hardware, a separate CMOS circuit has been used for
generation of reset signal so that it could be used to drive external devices as well. Writing the software The 89C51 have been specifically developed for control applications. As mentioned earlier, out of the 128 bytes of internal RAM, 16 bytes have been organized in such a way that all the 128 bits associated with this group may be accessed bit wise to facilitate their use for bit set/reset/test applications. These are therefore extremely useful for programs involving individual logical operations. One can easily give example of lift for one such application where each one of the floors, door condition, etc may be depicted by a single hit. The 89C51 have instructions for bit manipulation and testing. Apart from these, it has 8-bit multiply and divides instructions, which may be used with advantage. The 89C51 has short branch instructions for 'within page' and conditional jumps, short jumps and calls within 2k memory space which are very convenient, and as such the controller seems to favor programs which are less than 2k byte long. Some versions of 8751 EPROM devices have a security bit which can be programmed to lock the device and then the contents of internal program EPROM cannot be read.
The device has to be erased in full for further alteration, and thus it can only be reused but not copied. EEPROM and FLASH memory versions of the device are also available now. The term used in micro controller is:
Memory unit
Memory is part of the micro controller whose function is to store data. The easiest way to explain it is to describe it as one big closet with lots of drawers. If we suppose that we marked the drawers in such a way that they cannot be confused, any of their contents will then be easily accessible. It is enough to know the designation of the drawer and so we will know its contents for sure.
Memory components are exactly like that. For certain input we get the contents of a certain addressed memory location and thats all. Two new concepts are brought to us: addressing and memory location. Memory consists of all memory locations, and addressing is nothing but selecting one of them. This means that we need to select the desired memory location on one hand, and on the other hand we need to wait for the contents of that location. Besides reading from a memory location, memory must also provide for writing onto it. Supplying an additional line, called control line does this. We will designate this line as R/W (read/write). Control line is used in the following way: if r/w=1, reading is done, and if opposite is true then writing is done on the memory location. Memory is the first element, and we need a few operation of our micro controller.
Central Processing Unit
Let add 3 more memory locations to a specific block that will have a built in capability to multiply, divide, subtract, and move its contents from one memory location onto another. The part we just added in is called central processing unit (CPU). Its memory locations are called registers.
Registers are therefore memory locations whose role is to help with performing various mathematical operations or any other operations with data wherever data can be found. Look at the current situation. We have two independent entities (memory and CPU), that are interconnected, and thus any exchange of data is hindered, as well as its functionality. If, for example, we wish to add the contents of two memory locations and return the result again back to memory, we would need a connection between memory and CPU. Simply stated, we must have some way through data goes from one block to another. Bus That way is called bus. Physically, it represents a group of 8, 16, or more wires. There are two types of buses: address and data bus. The first one consists of as many lines as the amount of memory we wish to address, and the other one is as wide as data, in our case 8 bits or the connection line. First one serves to transmit address from CPU memory, and the second to connect all blocks inside the micro controller.
PIN DESCRIPTION:
Fig 3.4 AT89C51 Pin diagram
VCC Supply voltage. GND Ground. Port 0 Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs. Port 0 may also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode P0 has internal pullups.
Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pullups are required during program verification. Port 1 Port 1 is an 8-bit bi-directional I/O port with internal pull ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull ups. Port 1 also receives the low-order address bytes during Flash programming and verification. Port 2 Port 2 is an 8-bit bi-directional I/O port with internal pull ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pul lups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that uses 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that uses 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.
Port 3
Port 3 is an 8-bit bi-directional I/O port with internal pullups.The Port 3 output buffers can sink/source four TTL inputs.When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups. Port 3 also serves the functions of various special features of the AT89C51 as listed below:
Table 3.3 Port 3 alternative functions Port 3 also receives some control signals for Flash programming and verification. RST Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.
ALE/PROG
Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the micro controller is in external execution mode. PSEN Program Store Enable is the read strobe to external program memory. When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. EA/VPP External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require 12-volt VPP. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2
Output from the inverting oscillator amplifier. Oscillator Characteristics XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2.There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed. Idle Mode
In idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.
Fig 3.5 Oscillator Connection
Power-down Mode In the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. Programming the Flash The AT89C51 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH) and ready to be programmed. The programming interface accepts either a high-voltage (12-volt) or a low-voltage (VCC) program enable signal. The low-voltage programming mode provides a convenient way to program the AT89C51 inside the users system, while the high-voltage programming mode is compatible with conventional thirdparty Flash or EPROM programmers. The AT89C51 is shipped with either the highvoltage or low-voltage programming mode enabled.
3.4 LCD
LCDs with a small number of segments, such as those used in digital watches and pocket calculators, have a single electrical contact for each segment. An external dedicated circuit supplies an electric charge to control each segment. This display structure is unwieldy for more than a few display elements.
Small monochrome displays such as those found in personal organizers, or older laptop screens have a passive-matrix structure employing supertwist nematic (STN) or double-layer STN (DSTN) technology (DSTN corrects a color-shifting problem with STN). Each row or column of the display has a single electrical circuit. The pixels are addressed one at a time by row and column addresses. This type of display is called a passive matrix because the pixel must retain its state between refreshes without the benefit of a steady electrical charge. As the number of pixels (and, correspondingly, columns and rows) increases, this type of display becomes increasingly less feasible. Very slow response times and poor contrast are typical of passive-matrix .
For high-resolution color displays such as modern LCD computer monitors and televisions, an active matrix structure is used. A matrix of thinfilm transistors (TFTs) is added to the polarizing and color filters. Each pixel has its own dedicated transistor, which allows each column line to access one pixel. When a row line is activated, all of the column lines are connected to a row of pixels and the correct voltage is driven onto all of the column lines.
The row line is then deactivated and the next row line is activated. All of the row lines are activated in sequence during a refresh operation. Activematrix displays are much brighter and sharper than passive-matrix displays of the same size, and generally have quicker response times.The most common connector used for the 44780 based LCDs is 14 pins in a row, with pin centers 0.100" apart. Pins 1 2 3 4 5 6 7 14 Description Ground Vcc Contrast Voltage "R/S" _Instruction/Register Select "R/W" _Read/Write LCD Registers "E" Clock Data I/O Pins Table 3.4 : lcd pin description
As you would probably guess from this description, the interface is a parallel bus, allowing simple and fast reading/writing of data to and from the LCD.
This waveform will write an ASCII Byte out to the LCD's screen. The ASCII code to be displayed is eight bits long and is sent to the LCD either four or eight bits at a time. If four bit mode is used, two "nybbles" of data (Sent high
four bits and then low four bits with an "E" Clock pulse with each nybble) are sent to make up a full eight bit transfer. The "E" Clock is used to initiate the data transfer within the LCD.
Sending parallel data as either four or eight bits are the two primary modes of operation. While there are secondary considerations and modes, deciding how to send the data to the LCD is most critical decision to be made for an LCD interface application. Eight bit mode is best used when speed is required in an application and at least ten I/O pins are available. Four bit mode requires a minimum of six bits. To wire a microcontroller to an LCD in four bit mode, just the top four bits (DB4-7) are written to.
The "R/S" bit is used to select whether data or an instruction is being transferred between the microcontroller and the LCD. If the Bit is set, then the
byte at the current LCD "Cursor" Position can be read or written. When the Bit is reset, either an instruction is being sent to the LCD or the execution status of the last instruction is read back (whether or not it has completed). The different instructions available for use with the 44780 are shown in the table below: R/S 4 0 0 0 0 0 0 0 0 0 1 1 R/W D7 D6 D5 D4 D3 D2 D1 D0 Instruction/Description 5 0 0 0 0 0 0 0 0 1 0 1 14 13 12 11 10 9 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 1 D 8 0 1 C * 7 1 * B * * Pins Clear Display Return Cursor and LCD to Home Position Set Cursor Move Direction Enable Display/Cursor Move Cursor/Shift Display Set Interface Length
ID S
SC RL * A A A A * *
DL N F
A A * *
A A Move Cursor into CGRAM A A Move Cursor to Display * * Poll the "Busy Flag" Write a Character to the Display at the Current Cursor Position Read the Charact er on the Display at the Current Cursor Position
A A A
BF *
D D D D D D D D
D D D D
D D D D
Table 3.5 : instructions of LCD
3.5 KEYPAD
The key board here we are interfacing is a matrix keyboard. This key board is designed with a particular rows and columns. These rows and columns are connected to the microcontroller through its ports of the micro controller 8051. We normally use 8*8 matrix key board. So only two ports of 8051 can be easily connected to the rows and columns of the key board. When ever a key is pressed, a row and a column gets shorted through that pressed key and all the other keys are left open. When a key is pressed only a bit in the port goes high. Which indicates microcontroller that the key is pressed. By this high on the bit key in the corresponding column is identified. Once we are sure that one of key in the key board is pressed next our aim is to identify that key. To do this we firstly check for particular row and then we check the corresponding column the key board. To check the row of the pressed key in the keyboard, one of the row is made high by making one of bit in the output port of 8051 high . This is done until the row is found out. Once we get the row next out job is to find out the column of the pressed key. The column is detected by contents in the input ports with the help of a counter. The content of the input port is rotated with carry until the carry bit is set. The contents of the counter is then compared and displayed in the display. This display is designed using a seven segment display and a BCD to seven segment decoder IC 7447. The BCD equivalent number of counter is sent through output part of 8051 displays the number of pressed key.
FIG 3.6: Circuit diagram of INTERFACING KEY BOARD TO 8051. The programming algorithm, program and the circuit diagram is as follows. Here program is explained with comments. Simple Example of Interfacing Key Board: Keyboard is organized in a matrix of rows and columns as shown in the figure. The microcontroller accesses both rows and columns through the port. The 8051 has 4 I/O ports P0 to P3 each with 8 I/O pins, P0.0 to
P0.7,P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7. The one of the port P1 (it understood that P1 means P1.0 to P1.7) as an I/P port for microcontroller 8051, port P0 as an O/P port of microcontroller 8051 and port P2 is used for displaying the number of pressed key. Make all rows of port P0 high so that it gives high signal when key is
pressed. See if any key is pressed by scanning the port P1 by checking all columns for non zero condition. If any key is pressed, to identify which key is pressed make one row high at a time. Initiate a counter to hold the count so that each key is counted. Check port P1 for nonzero condition. If any nonzero number is there in [accumulator], start column scanning by following step 9.
Otherwise make next row high in port P1. Add a count of 08h to the counter to move to the next row by repeating
steps from step 6. If any key pressed is found, the [accumulator] content is rotated right
through the carry until carry bit sets, while doing this increment the count in the counter till carry is found. location Move the content in the counter to display in data field or to memory
FIG 3.7 : general telephonic keypad Our 12-Button telephone-like matrix keypad offers: o o o o o Rugged gray plastic with white key. 3 x 4 Matrix Type 8-position solder pad Contact rating: 24VDC @ 20mA Contact resistance: 200 Ohms max.
o Size: 77 x 56 x 15mm height
FIG 3.8 : MATRIX LOGIC OF KEYPAD Details: This keypad provides a visually appealing way to get numeric data to your control system. The board is a series of pushbutton switches that provide structured input for measuring user input. Output pins are 1-7, where pin 1 corresponds to the pin closest to the * key. Keypad Output Pins 1 2-3 2 1-2 3 2-5 4 3-7 5 1-7 6 5-7 7 3-6 8 1-6 9 5-6 0 1-4 # 4-5 * 3-4 Table 3.6 output pins for keypad
3.6 433 MHz RF TRANSMITTER

The STT-433 is ideal for remote control applications where low cost and longer range is required. The transmitter operates from 1.5-12V supply, making it ideal for battery-powered applications.The transmitter employs SAWstabilized oscillator, ensuring accurate frequency control for best range performance. Output power and harmonic emissions are easy to control, making FCC and ETSI compliance easy. The manufacturing-friendly SIP style package and low-cost make the STT-433 suitable for high volume applications.
FIG 3.9: 433 MHz RF TRANSMITTER
Features
433.92 MHz Frequency Low Cost 1.5-12V operation 11mA current consumption at 3V Small size 4 dBm output power at 3V
Applications
Remote Keyless Entry (RKE) Remote Lighting Controls On-Site Paging Asset Tracking Wireless Alarm and Security Systems Long Range RFID Automated Resource Management
Specification
Table 3.7 specifications of RF transmitter
3.7 433 MHz RF RECEIVER

The STR-433 is ideal for short-range remote control applications where cost is a primary concern. The receiver module requires no external RF components except for the antenna. It generates virtually no emissions, making FCC and ETSI approvals easy. The super-regenerative design exhibits exceptional sensitivity at a very low cost. Themanufacturing-friendly SIP style package and low-cost make the STR-433 suitable for high volume applications
FIG 3.10 : 433 MHz RF RECEIVER
Features
Low Cost 5V operation 3.5mA current drain No External Parts are required Receiver Frequency: 433.92 MHZ Typical sensitivity: -105dBm
IF Frequency: 1MHz
Applications
Car security system Sensor reporting Automation system Remote Keyless Entry (RKE) Remote Lighting Controls On-Site Paging Asset Tracking Wireless Alarm and Security Systems Long Range RFID
3.8 LIGHT EMITTING DIODES
It is a semiconductor diode having radiative recombination. It requires a definite amount of energy to generate an electron-hole pair. The same energy is released when an electron recombines with a hole. This released energy may result in the emission of photon and such a recombination. Hear the amount of energy released when the electro reverts from the conduction band to the valence band appears in the form of radiation. Alternatively the released energy may result in a series of phonons causing lattice vibration. Finally the released energy may be transferred to another electron. The recombination radiation may be lie in the infrared and visible light spectrum. In forward is peaked around the band gap energy and the phenomenon is called injection luminescence. I n a junction biased in the avalanche break down region, there results a spectrum of photons carrying much higher energies . Almost White light then gets emitted from micro-plasma breakdown region in silicon junction. Diodes having radiative recombination are termed as Light Emitting Diode , abbreviated as LEDs. In gallium arsenide diode, recombination is predominantly a radiation recombination and the probability of this radiative recombination far exceeds that in either germanium or silicon. Hence GaAs LED has much higher efficiency in terms of Photons emitted per carrier. The internal efficiency of GaAs LED may ba very close to 100% but because of high index of refraction, only a small fraction of the internal radiation can usually come out of the device surface. In spite of this low efficiency of actually radiated light , these LEDs are efficiency used as light emitters in visual display units and in optically coupled
circuits, The efficiency of light generation increases with the increase of injected current and with decreases in temperature. within one diffusion length of the diode junction. The light so generated is concentrated near the junction since most of the charge carriers are obtained
The following are the merits of LEDs over conventional incandescent and other types of lamps
1. 2. 3. 4. 5. 6. 7.
Low working voltages and currents Less power consumption Very fast action Emission of monochromatic light small size and weight No effect of mechanical vibrations Extremely long life Typical LED uses a forward voltage of about 2V and current of 5 to
10mA. GaAs LED produces infra-red light while red, green and orange lights are produced by gallium arsenide phosphide (GaAs) and gallium phosphide(Gap) .
3.9 Power Supply
FIG 3.11: power supply
Power supply unit provides 5V regulates power supply to the systems. It consists of two parts namely,
1. 2.
Rectifier Monolithic voltage regulator
Rectifier :
Here the step down transformer 230-0v/12-0-12V gives the secondary current up to 500mA, to the Rectifier. The secondary Transformer is provided with a center tap. Hence the voltage V1 and V2 are equal and are having a phase difference of 1800. So it is anode of Diode D1 which is positive with respect to the center tap, the anode of the other diode d2 will be negative with respect to the center tap. During the positive half cycle of the supply D1 conducts and current flows through the center tap D1 and load. During this period D2 will not conduct as its anode is at negative potential. During the negative half cycle of the supply voltage, the voltage on the diode D2 will be positive and hence D2 conducts. The current flows through the transformer winding, Diode D2 and load. It is to be noted that the current i1 and i2 are flowing in the same direction in load. The average of the two current i1 and i2 flows through the load producing a voltage drop, which is the D.C. output voltage of the rectifier. Using monolithic IC voltage regulators, voltage can be regulated.
Monolithic IC voltage regulator :
A voltage regulator is a circuit that supplies a constant voltage regardless of changes in load currents. Although voltage regulators can be designed using op-amps, it is quicker and easier to use IC voltage regulators. Furthermore, IC voltage regulators are versatile and relatively inexpensive and are available with features such as programmable output, current/voltage boosting, internal short-circuit current limiting, thermal shutdown and floating operation for high voltage applications
Here 7800 series voltage regulators are used. The 7800 series consists of 3-terminal positive voltage regulators with seven voltage options. These ICs are designed as fixed voltage regulators and with adequate heat sinking can deliver output currents in excess of 1A. Although these devices do not require external components, such components can be used to obtain adjustable voltages and currents. For proper operation a common ground between input and output voltages is required. In addition, the difference between input and output voltages (Vi Vo) called drop out voltage, must be typically 1.5V even during the low point as the input ripple voltage. The capacitor Ci is required if the regulator is located at an appreciable distance from a power supply filter. Even though Co is not needed, it may be used to improve the transient response of the regulator.
Typical performance parameters for voltage regulators are line regulation, load regulation, temperature stability and ripple rejection. Line regulation is defined as the change in output voltage for a change in the input voltage and is usually expressed in milli volts or as a percentage of Vo. Temperature stability or average temperature coefficient of output voltage (TCVo) is the change in output voltage per unit change in temperature and is expressed in either milli volts/C or parts per million (PPM/C). Ripple rejection is the measure of a regulators ability to reject ripple voltage. It is usually expressed in decibels. The smaller the values of line regulation, load regulation and temperature stability, gives better regulation.
CHAPTER 4
SOFTWARE
4.1 PROGRAMME FOR TRAFFIC DIVERSION FOR AMBULANCE
;----------------------------------------------------------------------------------------------------------;> ;> TITLE ;> TARGET ;> STARTED : TRAFFIC DIVERSION FOR AMBULANCE : AT89C2051 : 18-03-2010
;>
;----------------------------------------------------------------------------------------------------------;> ;> ;> ;----------------------------------------------------------------------------------------------------------;> ;> HARDWARE DETAILS: P2G P2Y P2R BIT BIT BIT P1.7 P1.6 P1.5 INCLUDES $MOD51 :
P1G P1Y P1R P3G P3Y P3R P4G P4Y P4R ;>
BIT BIT BIT BIT BIT BIT BIT BIT BIT
P1.4 P1.3 P1.2 P1.1 P1.0 P3.7 P3.5 P3.4 P3.3
;----------------------------------------------------------------------------------------------------------;> ;> VARIABLES: LOCK1 LOCK2 SEQ_CNT SEQ_CNT1 SEQ_CNT2 SEQ_CNT3 TEMP1 TEMP2 TEMP3 CHEK_SUM TMPR_VAL TMPR_VAH ;> ;----------------------------------------------------------------------------------------------------------BIT BIT 00H 01H 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H
DATA DATA DATA DATA DATA DATA DATA
DATA DATA DATA
;> ;> VECTOR ADDRESESS: ORG ljmp ORG push push jbc ajmp mov mov ljmp mov clr ; ljmp mov clr ; ljmp 0000H RESET 0023H ACC PSW RI, RECEIVE_DATA SKIP_CHKS1 A, SBUF R3, #00H SKIP_CHKS1 A, SBUF LOCK1 SKIP_CHKS1 A, SBUF LOCK2 SKIP_CHKS1
RECEIVE_DATA: cjne A, #55H, LOAD_VAL0
LOAD_VAL0: cjne A, #0A5H, LOAD_VAL01
LOAD_VAL01: cjne A, #0B5H, LOAD_VAL02
LOAD_VAL02: cjne R3, #00H, LOAD_VAL1 cjne A, #0AAH, LOAD_VAL1 mov ljmp R3, #01H SKIP_CHKS1
LOAD_VAL1: cjne R3, #01H, LOAD_VAL2 mov mov ljmp R3, #02H TEMP1, A SKIP_CHKS1
LOAD_VAL2: cjne R3, #02H, SKIP_CHKS mov mov mov xrl clr setb mov clr ljmp R3, #00H CHEK_SUM, A A, #0AAH A, TEMP1 P3.1 P3.1 TMPR_VAH, TEMP1 LOCK1 SKIP_CHKS1
cjne A, CHEK_SUM, SKIP_CHKS1 lcall BUZ_DLY1
SKIP_CHKS: cjne R3, #00H, LOAD_VAL3 cjne A, #0BBH, LOAD_VAL3 mov ljmp R3, #03H SKIP_CHKS1
LOAD_VAL3: cjne R3, #03H, LOAD_VAL4 mov mov ljmp R3, #04H TEMP2, A SKIP_CHKS1
LOAD_VAL4: cjne R3, #04H, SKIP_CHKS1 mov R3, #00H
mov mov xrl clr setb mov clr
CHEK_SUM, A A, #0BBH A, TEMP2 P3.1 P3.1 TMPR_VAL, TEMP2 LOCK2
cjne A, CHEK_SUM, SKIP_CHKS1 lcall BUZ_DLY1
SKIP_CHKS1: pop pop RETI ;> ;----------------------------------------------------------------------------------------------------------;> RESET: mov mov mov anl mov mov mov mov setb clr clr clr P3, #0FFH P1, #0FFH sp, #65H PCON, #7FH TMOD, #21H TH1, #0E8H SCON, #50H IE, #90H TR1 P1G P2R P3R ; init stack pointer ; CLR SMOD BIT ; TIMER 1 IN MODE 2 ; SET BAUD RATE AS 1200 ; SERIAL MODE 1 AND RECEIVE ENABLE ; ENABLE SERIAL INTERRUPT ; RUN TIMER 1 PSW ACC
clr mov mov mov mov clr clr mov mov ;>
P4R SEQ_CNT, #00H SEQ_CNT1, #00H SEQ_CNT2, #00H SEQ_CNT3, #00H LOCK1 LOCK2 TMPR_VAH, #00H TMPR_VAL, #00H
;----------------------------------------------------------------------------------------------------------;> MAIN: inc mov mov inc mov SEQ_CNT3 A, SEQ_CNT3 SEQ_CNT3, #00H SEQ_CNT2 A, SEQ_CNT2
cjne A, #0AH, RST_SEQ_CNT
cjne A, #00H, RST_SEQ_CNT inc mov SEQ_CNT1 A, SEQ_CNT1
cjne A, #00H, RST_SEQ_CNT mov setb clr A, SEQ_CNT P1G P1Y
cjne A, #01H, SET_SEQ1
lcall SERL_DLY1 setb clr clr setb mov setb clr setb clr clr setb mov setb clr setb clr clr setb mov setb clr P1Y P1R P2G P2R A, SEQ_CNT P2G P2Y P2Y P2R P3G P3R A, SEQ_CNT P3G P3Y P3Y P3R P4G P4R A, SEQ_CNT P4G P4Y
SET_SEQ1: cjne A, #02H, SET_SEQ2
lcall SERL_DLY1
lcall SERL_DLY1
lcall SERL_DLY1
setb clr clr setb
P4Y P4R P1G P1R
SET_SEQ4: lcall PRIORITY inc mov mov SEQ_CNT A, SEQ_CNT SEQ_CNT, #01H
cjne A, #05H, RST_SEQ_CNT RST_SEQ_CNT: ljmp ;> ;----------------------------------------------------------------------------------------------------------;> PRIORITY: mov anl ljmp mov anl ljmp A, TMPR_VAH A, #0F0H ON_AMB1_PRIR A, TMPR_VAL A, #0F0H ON_AMB2_PRIR MAIN
cjne A, #080H, CHEK_NXT1 CHEK_NXT1:
cjne A, #080H, CHEK_NXT2 CHEK_NXT2: ON_AMB1_PRIR: mov A, TMPR_VAH
anl mov orl clr clr clr clr mov setb CASE1:
A, #0FH P1, #0FFH P3, #0F8H P1G P2R P3R P4R SEQ_CNT, #04H LOCK1
cjne A, #01H, CASE1
cjne A, #02H, CASE2 mov orl clr clr clr clr mov setb CASE2: cjne A, #03H, CASE3 mov orl clr clr clr clr mov setb CASE3: P1, #0FFH P3, #0F8H P3G P1R P2R P4R SEQ_CNT, #02H LOCK1 P1, #0FFH P3, #0F8H P2G P1R P3R P4R SEQ_CNT, #01H LOCK1
cjne A, #04H, CASE4 mov orl clr clr clr clr mov setb CASE4: jb mov LOCK1, CASE4 TMPR_VAH, #00h P1, #0FFH P3, #0F8H P4G P2R P3R P1R SEQ_CNT, #03H LOCK1
ON_AMB2_PRIR: mov anl mov orl clr clr clr clr mov setb CASE5: cjne A, #02H, CASE6 mov orl clr clr P1, #0FFH P3, #0F8H P2G P1R A, TMPR_VAL A, #0FH P1, #0FFH P3, #0F8H P1G P2R P3R P4R SEQ_CNT, #04H LOCK2
cjne A, #01H, CASE5
clr clr mov setb CASE6:
P3R P4R SEQ_CNT, #01H LOCK2
cjne A, #03H, CASE7 mov orl clr clr clr clr mov setb CASE7: cjne A, #04H, CASE8 mov orl clr clr clr clr mov setb CASE8: jb mov RET ;> ;----------------------------------------------------------------------------------------------------------LOCK2, CASE8 TMPR_VAL, #00h P1, #0FFH P3, #0F8H P4G P2R P3R P1R SEQ_CNT, #03H LOCK2 P1, #0FFH P3, #0F8H P3G P1R P2R P4R SEQ_CNT, #02H LOCK2
;> SERL_DLY1: mov R5, #09H R6, #00H R7, #00H R7, SIN1 EXT1: mov SOUT1: mov SIN1: djnz
djnz R6, SOUT1 djnz R5, EXT1 RET ;> ;----------------------------------------------------------------------------------------------------------;> BUZ_DLY1: mov SIN2: djnz RET ;> END R0, #00H R1, #00H R1, SIN2 SOUT2: mov
djnz R0, SOUT2
4.2 AMBULANCE SECTION PROGRAM

;----------------------------------------------------------------------------------------------------------;> ;> TITLE ;> TARGET ;> STARTED ;> ;----------------------------------------------------------------------------------------------------------;> ;> ;> ;----------------------------------------------------------------------------------------------------------;> ;> HARD WARE DETAILS ;> ;> ;> ;> ;> ;> DISPLAY ENEBLE DEN DRW DRS BUZZ BIT P2.5 BIT P2.6 BIT P2.7 BIT P3.2 DISPLAY READ/WRITE DISPLAY REG SELECT BUZZER CONTROL LED CONTROL : INCLUDES $MOD51 : : AMBULANCE SECTION PROGRAM : AT89C51 : 18-03-2010
LED ;>
BIT P3.3
;----------------------------------------------------------------------------------------------------------;> ;> FLAGS: BUSY_CHEK KEY_RLS ;> ;----------------------------------------------------------------------------------------------------------;> ;> VARIABLES: TMPR_VAL TMPR_VAH PULSE TCNT1 TCNT2 TPLS TEMP1 TEMP2 TEMP3 KEY_VAL KEY_PRS PRV_KEY LP_CNT ;> ;----------------------------------------------------------------------------------------------------------;> CHEK_SUM DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA 31H 32H BIT BIT 00H 01H
33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH
DATA
;>
DEFINITIONS COM DAT EOL
: EQU EQU EQU 0fch 0fdh 0feh ; command ; data ; end of line ;display headers
;> ;----------------------------------------------------------------------------------------------------------;> ;> VECTOR ADDRESESS: ORG ljmp ORG RETI ;> ;----------------------------------------------------------------------------------------------------------;> RESET: mov mov mov mov mov mov mov P3, #0FFH P2, #0FFH P1, #0FFH P0, #0FFH sp, #065H ; init stack pointer ; move all ports HIGH 0000H RESET 0023H
dptr, #INITIALISE dptr, #CLRSCR
lcall MESSAGE lcall MESSAGE anl PCON, #7FH
mov mov mov mov mov setb mov mov MOV ;>
TCON, #05H TMOD, #21H TH1, #0E8H SCON, #50H IE, #0H TR1 DPTR, #NO_SIG TEMP3, #00H TMPR_VAH, #00h
lcall MESSAGE
;----------------------------------------------------------------------------------------------------------;> MAIN: inc mov mov cpl cpl ; ; ; ; mov clr LP_CNT A, LP_CNT LP_CNT, #00H BUZZ LED SBUF, #55H TI, CHAN0 TI
cjne A, #30H, BLINK_LED
CHAN0: jnb
lcall SERL_DLY1 BLINK_LED: lcall MENUS mov TMPR_VAH, KEY_PRS
mov mov
A, TMPR_VAH DPTR, #RT1J
cjne A, #01H, NOT_JAM1 lcall MESSAGE NOT_JAM1: mov mov A, TMPR_VAH DPTR, #RT2J cjne A, #02H, NOT_JAM2 lcall MESSAGE NOT_JAM2: mov mov A, TMPR_VAH DPTR, #RT1J1 cjne A, #03H, NOT_JAM11 lcall MESSAGE NOT_JAM11: mov mov A, TMPR_VAH DPTR, #RT2J1 cjne A, #04H, NOT_JAM21 lcall MESSAGE NOT_JAM21: mov mov A, TMPR_VAH DPTR, #RT3J1 cjne A, #05H, NOT_JAM31 lcall MESSAGE NOT_JAM31: mov mov A, TMPR_VAH DPTR, #RT3J2 cjne A, #06H, NOT_JAM41 lcall MESSAGE NOT_JAM41:
mov mov
A, TMPR_VAH DPTR, #RT3J3
cjne A, #0BH, NOT_JAM51 lcall MESSAGE NOT_JAM51: mov mov A, TMPR_VAH DPTR, #NO_SIG cjne A, #00H, NOT_JAM61 lcall MESSAGE NOT_JAM61: ljmp ;> ;----------------------------------------------------------------------------------------------------------;> MESSAGE: display push acc ; Check weather display is ready ; Clr accumulator a, @a+dptr ; ; If the data is not end of line goto ; Load accumulator with the contents MESSAGE1: lcall READY clr of dptr inc cjne comd pop ret COMD: acc ; if the data is end of line stop sending ; dptr a, #EOL, COMD a movc ; sub for sending charactors to MAIN
cjne data clr clr sjmp DDATA: cjne goto comd setb setb sjmp SENDIT: mov clr nop setb clr sjmp ;>
a, #COM, DDATA DRS BUSY_CHEK MESSAGE1 ; a, #DAT, SENDIT DRS BUSY_CHEK MESSAGE1 ; P0, a DRW DEN DEN MESSAGE1 ;
; if the data is not command goto
; goto message again
; if the data is not data to be send
; goto message again
; place the data at port 1
; send enable strobe ; goto message again
;----------------------------------------------------------------------------------------------------------;> READY: clr mov clr setb DEN P0, #0FFH DRS DRW ; sub to check display busy ; disable display buffer ; set port1 in read mode
WAIT: clr setb jb loop clr jnb setb ret ;> DEN DRS DEN DEN P0.7, WAIT
; ; send enable strobe ; ; if display is not send ready signal be in ; disable display buffer
BUSY_CHEK, NO_DRS_SET
NO_DRS_SET: ; return to message
;----------------------------------------------------------------------------------------------------------;> DLY: mov r4, #0fh r5, #00h r6, #00h GONE: mov OUT: mov IN:
djnz r6, IN djnz r5, OUT djnz r4, GONE ret
DLY1: mov r4, #03h r5, #00h r6, #00h GONE1: mov OUT1: mov
IN1: djnz r6, IN1 djnz r5, OUT1 djnz r4, GONE1 ret ;>
;----------------------------------------------------------------------------------------------------------;> KBREAD: mov clr nop nop nop nop mov nop setb jb mov ajmp jb mov ajmp jb mov ajmp jb mov ajmp P1.0 ACC.3, NOT_KEY1 KEY_PRS, #01H CHEK_BOUNSE ACC.4, NOT_KEY2 KEY_PRS, #04H CHEK_BOUNSE ACC.5, NOT_KEY3 KEY_PRS, #07H CHEK_BOUNSE ACC.6, NOT_KEY4 KEY_PRS, #0AH CHEK_BOUNSE A, P1 PRV_KEY, KEY_PRS P1.0 ; key board sub
NOT_KEY1:
NOT_KEY2:
NOT_KEY3:
NOT_KEY4: clr nop nop nop nop mov nop setb jb mov ajmp jb mov ajmp jb mov ajmp jb mov ajmp P1.1 ACC.3, NOT_KEY5 KEY_PRS, #02H CHEK_BOUNSE ACC.4, NOT_KEY6 KEY_PRS, #05H CHEK_BOUNSE ACC.5, NOT_KEY7 KEY_PRS, #08H CHEK_BOUNSE ACC.6, NOT_KEY8 KEY_PRS, #00H CHEK_BOUNSE A, P1 P1.1
NOT_KEY5:
NOT_KEY6:
NOT_KEY7:
NOT_KEY8: clr nop nop nop P1.2
nop mov nop setb jb mov ajmp jb mov ajmp jb mov ajmp jb mov ajmp mov mov P1.2 ACC.3, NOT_KEY9 KEY_PRS, #03H CHEK_BOUNSE ACC.4, NOT_KEY10 KEY_PRS, #06H CHEK_BOUNSE ACC.5, NOT_KEY11 KEY_PRS, #09H CHEK_BOUNSE ACC.6, NOT_KEY12 KEY_PRS, #0BH CHEK_BOUNSE KEY_PRS, #0FFH A, KEY_PRS A, P1
NOT_KEY9:
NOT_KEY10:
NOT_KEY11:
NOT_KEY12: CHEK_BOUNSE: cjne A, PRV_KEY, SET_BOUNCE SET_BOUNCE: jc clr ret SET_BOUNCE1: setb KEY_RLS SET_BOUNCE1 KEY_RLS
lcall SERL_DLY1
clr
BUZZ
lcall SERL_DLY1 lcall SERL_DLY1 setb ret ;> ;----------------------------------------------------------------------------------------------------------;> MENUS: lcall KBREAD jb ret GOTO_DESELECT: mov A, KEY_PRS ; ; COMPARE BOTH KEY VALS cjne A, #05H, GOTO_LAST GOTO_LAST: jnc mov mov orl mov mov READ_NUM_KEYS KEY_VAL, KEY_PRS A, KEY_PRS KEY_VAL, #80H A, KEY_PRS KEY_VAL, #0B5H ; SAVE PRESENT KEY ; key board sub ; READ KEY ; IF NOT KEYHIT JUMP KEY_RLS, GOTO_DESELECT BUZZ
READ_NUM_KEYS: cjne A, #06H, SET_PRIOR1 SET_PRIOR1: cjne A, #0BH, SET_PRIOR2 SET_PRIOR2: SET_PRIOR: setb P3.7
mov clr
SBUF, #055H TI, CHAN10 TI
CHAN10: jnb
lcall SERL_DLY1 mov clr SBUF, #055H TI, CHAN11 TI
CHAN11: jnb
CHAN12: jnb
CHAN13: jnb
CHAN1: jnb
lcall SERL_DLY1 mov clr SBUF, #0BBH TI, CHAN2 TI
CHAN2: jnb
lcall SERL_DLY1 mov SBUF, KEY_VAL
CHAN3: jnb clr TI
TI, CHAN3
lcall SERL_DLY1 mov xrl mov clr clr ret ;> ;----------------------------------------------------------------------------------------------------------;> SERL_DLY1: mov SIN1: djnz RET ;> ;----------------------------------------------------------------------------------------------------------;> ;> ROM TABLE AREA ;> INITIALISE: db COM, 30h, 30h, 30h, 30h, 3ch, 06h, 0ch, 01h, EOL R6, #05H R7, #00H R7, SIN1 SOUT1: mov A, #0BBH A, KEY_VAL SBUF, A TI, CHAN4 TI P3.7
CHAN4: jnb
lcall SERL_DLY1
djnz R6, SOUT1
RT1J: db COM, 80h, DAT, 'ROUTE 1 CLEAR ', EOL RT2J: db COM, 80h, DAT, 'ROUTE 2 CLEAR ', EOL RT1J1: db COM, 80h, DAT, 'ROUTE 3 CLEAR ', EOL RT2J1: db COM, 80h, DAT, 'ROUTE 4 CLEAR ', EOL RT3J1: db COM, 0C0h, DAT, 'NORMAL MODE ', EOL RT3J2: db COM, 0C0h, DAT, 'PRIORITY MODE ', EOL RT3J3: db COM, 80h, DAT, ' TRAFFIC ', EOL NO_SIG: db COM, 80h, DAT, 'ENTER OPTION.. ', COM, 0C0h, DAT, ' ', EOL CLRSCR: db COM, 01h, EOL ;> ;----------------------------------------------------------------------------------------------------------;> END ', COM, 0C0h, DAT, 'RELEASE
CHAPTER 5
APPLICATIONS
USED IN AMBULANCES USED IN 108 SERVICES USED IN FIRE ENGINE SERVICES
CHAPTER 6
CONCLUSION
WE CAN USE TRAFFIC JAM SENSORS TO DETECT TRAFFIC JAMS FOR DIVERSIONS
CHAPTER 7
BIBILOGRAPHY
NAME OF THE SITES 1. 2. 3. 4. WWW.MITEL.DATABOOK.COM WWW.ATMEL.DATABOOK.COM WWW.FRANKLIN.COM WWW.KEIL.COM
REFERENCES 1. 8051-MICROCONTROLLER AND EMBEDDED SYSTEM. Mohd. Mazidi.

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INNOVATIVE CONETION CONTROL TO CLEAR THE TRAFFIC FOR AMBULANCE USING RF

INNOVATIVE CONETION CONTROL TO CLEAR THE TRAFFIC FOR AMBULANCE USING RF

FIG 1.1 : Example of embede system.

INNOVATIVE CONETION CONTROL TO CLEAR THE TRAFFIC FOR AMBULANCE USING RF

Red LED Yellow LED Green LED

Red LED Yellow LED Green LED

Signal post 3 Red LED Yellow LED Green LED

INNOVATIVE CONETION CONTROL TO CLEAR THE TRAFFIC FOR AMBULANCE USING RF

2.2 AMBULANCE SECTION BLOCK DIAGRAM

Buzzer & LED

FIG 2.2 : block diagram of ambulance section

INNOVATIVE CONETION CONTROL TO CLEAR THE TRAFFIC FOR AMBULANCE USING RF

: SCHEMATIC DIAGRAM OF TRAFFIC POST

INNOVATIVE CONETION CONTROL TO CLEAR THE TRAFFIC FOR AMBULANCE USING RF

3.2 SCHEMATIC OF AMBULANCE SECTION :

FIG 3.2 : SCHEMATIC OF AMBULANCE SECTION

INNOVATIVE CONETION CONTROL TO CLEAR THE TRAFFIC FOR AMBULANCE USING RF

3.3 AT89C2051 CONTROLLER

INNOVATIVE CONETION CONTROL TO CLEAR THE TRAFFIC FOR AMBULANCE USING RF

INNOVATIVE CONETION CONTROL TO CLEAR THE TRAFFIC FOR AMBULANCE USING RF

Fig 3.3 : AT89C51 internal block diagram SALIENT FEATURES

INNOVATIVE CONETION CONTROL TO CLEAR THE TRAFFIC FOR AMBULANCE USING RF

INNOVATIVE CONETION CONTROL TO CLEAR THE TRAFFIC FOR AMBULANCE USING RF

INNOVATIVE CONETION CONTROL TO CLEAR THE TRAFFIC FOR AMBULANCE USING RF

INNOVATIVE CONETION CONTROL TO CLEAR THE TRAFFIC FOR AMBULANCE USING RF

INNOVATIVE CONETION CONTROL TO CLEAR THE TRAFFIC FOR AMBULANCE USING RF

Central Processing Unit

INNOVATIVE CONETION CONTROL TO CLEAR THE TRAFFIC FOR AMBULANCE USING RF

INNOVATIVE CONETION CONTROL TO CLEAR THE TRAFFIC FOR AMBULANCE USING RF

Fig 3.4 AT89C51 Pin diagram

INNOVATIVE CONETION CONTROL TO CLEAR THE TRAFFIC FOR AMBULANCE USING RF

INNOVATIVE CONETION CONTROL TO CLEAR THE TRAFFIC FOR AMBULANCE USING RF

INNOVATIVE CONETION CONTROL TO CLEAR THE TRAFFIC FOR AMBULANCE USING RF

INNOVATIVE CONETION CONTROL TO CLEAR THE TRAFFIC FOR AMBULANCE USING RF

INNOVATIVE CONETION CONTROL TO CLEAR THE TRAFFIC FOR AMBULANCE USING RF

Fig 3.5 Oscillator Connection

INNOVATIVE CONETION CONTROL TO CLEAR THE TRAFFIC FOR AMBULANCE USING RF

INNOVATIVE CONETION CONTROL TO CLEAR THE TRAFFIC FOR AMBULANCE USING RF

INNOVATIVE CONETION CONTROL TO CLEAR THE TRAFFIC FOR AMBULANCE USING RF

INNOVATIVE CONETION CONTROL TO CLEAR THE TRAFFIC FOR AMBULANCE USING RF

INNOVATIVE CONETION CONTROL TO CLEAR THE TRAFFIC FOR AMBULANCE USING RF

Table 3.5 : instructions of LCD

INNOVATIVE CONETION CONTROL TO CLEAR THE TRAFFIC FOR AMBULANCE USING RF

INNOVATIVE CONETION CONTROL TO CLEAR THE TRAFFIC FOR AMBULANCE USING RF

INNOVATIVE CONETION CONTROL TO CLEAR THE TRAFFIC FOR AMBULANCE USING RF

o Size: 77 x 56 x 15mm height

INNOVATIVE CONETION CONTROL TO CLEAR THE TRAFFIC FOR AMBULANCE USING RF

INNOVATIVE CONETION CONTROL TO CLEAR THE TRAFFIC FOR AMBULANCE USING RF

3.6 433 MHz RF TRANSMITTER

FIG 3.9: 433 MHz RF TRANSMITTER

INNOVATIVE CONETION CONTROL TO CLEAR THE TRAFFIC FOR AMBULANCE USING RF

Table 3.7 specifications of RF transmitter

INNOVATIVE CONETION CONTROL TO CLEAR THE TRAFFIC FOR AMBULANCE USING RF

3.7 433 MHz RF RECEIVER

FIG 3.10 : 433 MHz RF RECEIVER

INNOVATIVE CONETION CONTROL TO CLEAR THE TRAFFIC FOR AMBULANCE USING RF

INNOVATIVE CONETION CONTROL TO CLEAR THE TRAFFIC FOR AMBULANCE USING RF

3.8 LIGHT EMITTING DIODES

INNOVATIVE CONETION CONTROL TO CLEAR THE TRAFFIC FOR AMBULANCE USING RF

INNOVATIVE CONETION CONTROL TO CLEAR THE TRAFFIC FOR AMBULANCE USING RF

3.9 Power Supply

FIG 3.11: power supply