International Journal of Electronics, Communication & Instrumentation Engineering Research and Development (IJECIERD) ISSN 2249-684X Vol.

3, Issue 1, Mar 2013, 63-70 TJPRC Pvt. Ltd.

DESIGN OF HIGH SPEED SINE WAVE FLASH ADC FOR UWB APPLICATIONS
D. JACKULINE MONI1 & BINI. T. G2
1 2

Professor, School of Electrical Science, Karunya University, Coimbatore, Tamil Nadu, India

PG Scholar, School of Electrical Science, Karunya University, Coimbatore, Tamil Nadu, India

ABSTRACT
Multigigahertz flash ADC is limited by sampling clock timing jitter. Since it is used in high frequency applications it is essential to remove jitter effects which will reduce the efficiency of ADC. This paper describes the effect of clock transition time on the spurious free dynamic range of a CMOS sample and hold circuit. To improve SFDR the effect of finite clock transition time of the signal and sinusoidal signal sampling clock are considered that is mainly based on signal dependent non linearity model. Where a square wave clock exhibits a shorter transition time but more jitter susceptibility, sinusoidal clocking provides a longer transition time but shorter jitter spectrum. To verify this concept a 6GS/s, 4b flash ADC is designed along with this interpolation technique is added in order to reduce the power consumption achieving effective number of bits of 3.93 bits with a SNR of 22.9dB.

GENERAL TERMS: Flash ADC, ENOB, SNR, SFDR, Jitter KEYWORDS: Flash ADC, SFDR, SNR, ENOB, Transition Time, Jitter, Sinusoidal Clocking INTRODUCTION
Flash Analog -to- Digital Converters(ADCs) are the architecture of choice, where maximum sampling rate and low moderate resolution are required. A typical example is a disk drive system, where customers often ask for the maximum sample rate offered by the currently available technology. High speed ADC are used widely in many communication and signal processing applications such as UWB systems [1], SerDes receivers [2] and optical communication systems[3]. For an ADC with a sampling rate above Gs/s is used for wireless applications. A high speed track and hold circuit is typically used in front end , followed by time interleaving sub ADCs [2][9]. In order to meet the stringent performance requirements of such ADCs it is necessary to use T/H circuits which requires high linearity and wide bandwidth. Furthermore, the performance of ADC is usually limited by the jitter of the sampling clock [8]. Even a small sampling uncertainty can introduce a large error in the sampled voltage, resulting in harmonic distortion at the output. If non idealities are ignored, with a sinusoidal input, the signal to noise ratio (SNR), due to a sampling clock with RMS jitter rms is given in [5]. (1) Where finput is the input signal frequency.

RELATIONSHIP BETWEEN SFDR AND CLOCK TRANSITION TIME

Consider a sample and hold whose gate is controlled by the clock and source (or drain) connected to the input.

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Figure 1: Nonlinearity Model for an Input Dependent Sampling Instant Non linearity model for input-dependent sampling shown in fig1 [1], because of the input-dependent t change at each sampling instance, the output of the sample and hold is (2) Where =tswhere ts is the sampling instant and tr is the real sampling instant. In order to calculate the ts= Asin( s) (3)

(4) Value of point N on a sinusoidal curve (5) By taking Taylor series in the above expression it gives SFDR that can be estimated as SFDR= SFDR is proportional to the square of the clock amplitude clock transition time ttr. A is the input signal swing, and (6) and is inversely proportional to the square of the

input signal frequency

TRACK AND HOLD

Figure 2: Schematic of a Differential NMOS T/H Circuit

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Track and hold circuit is designed in such a way that to get good samples and in the frequency range of 4GHz and with reduced power consumption. Such with the transition time relation w/l as well as resistance, capacitance and voltage is chosen using the formula t=RonCh* (7)

Where Ron is the resistance, Ch is the hold capacitance VGs is the gate source voltage and Vth is the threshold voltage, Spurious free dynamic range is the range which is free from overlapping as well as from spurs.

Figure 3: Shows Relation between SFDR and Input Signal Frequency From the fig 3 as input signal frequency increases as SFDR decreases and when transition time increases the SFDR decreases which can be directly obtained from the equation (6). SFDR roll of by 22.19dB and with clock transition of 120ps. And with a signal frequency of 2GHz. The signal dependent sampling error limits the SFDR by 22.19dB. SFDR analysis was done between the frequencies 0.5GHz to 5GHz, where below 1GHz the sampling was not efficient, and frequency between 1-4GHz there was optimum sampling. And above 5GHz overlapping of samples has occurred. Which means that spurious free dynamic range of the sample and hold is between 1 GHz and 4 GHz.

JITTER EFFECT IN TRACK AND HOLD

Jitter is the delay occurring in the generation circuitry, which affects the efficiency of ADCs, jitter is present in all analog circuits especially in ADCs like flash , SAR and in pipeline which will affect the bits so that the effective number of bits will decrease. SNR limit of the sample and hold in different frequencies are plotted. For 40ps 4GHz sine wave there is a degradation in SFDR as input frequency increases which further decreases the when clock signal frequency is decreased to 2GHz sine wave. Instead of sine wave if square wave is used then the SFDR degradation is further reduced. If jitter is not eliminated and when it is set to 1ps then the degradation of SFDR is in a linear fashion.

FLASH ADC INCORPORATING SINE WAVE SAMPLING

In order to reduce the jitter effect flash ADC is proposed with sine wave sampling clock and with high speed, a 6GS/s flash ADC is proposed. Fig5 shows the schematic of flash ADC.

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Figure 4: Proposed Flash ADC with Sine Wave Clock Input signal is given through a resistive ladder to the comparator along with the reference signal is given to a latch then it is followed by the D flipflop. Now the output will be in the form of thermometer code. Comparator may have a metastability state, so that error may occur in the thermometer code, in order to remove this, an error correction logic has to be implemented after that this 16 bit thermometer code is converted into 4 bit binary code. Figure 5 shows the schematic of the comparator used in the ADC. Current steering is shared between two comparators working in Bang-Bang mode at 4GHz, realizing an effective sampling rate of 6GS/s. Each comparator is folded into two stages in order to operate under a low supply .The first stage work as both sampler as well as preamplifier. It is followed by the latch stage. Another advantage of this comparator is that the clock kickback current is eliminated because the switches are connected to the common mode point in the signal path. The power consumption of the comparator is 2.17pW which is of less power consumption.

Figure 5: Schematic of Comparator

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Gain of the comparator is 1.75KdB, which is of higher gain compared to any of the dynamic comparator. Fig8 here shows the simulated results of comparator quantisation delay of various input amplitudes, for both a 3GHz sine wave clock and 60ps rise tine square wave clock, the difference in quantizer delay is very lessthis is because the current steering comparator whose clock voltage is less than the ability of the differential pair to hard switchthe current from one branch to another. As frequency increases bandwidth decreases. Bandwidth is constant upto 5G after that it decreases rapidly. This is because comparator can compare signals only between the range of 1-5GHz.. After 30GHz the operating frequency range is rapidly decreasing to the minimum. Delay degradation is reduced due to the current steering nature of the complementary quantizers, where clock voltage is not important than the ability of the differential pair. Jitter analysis of comparator is very essential because it can affect the effective number of bits. If square wave is used as the clock which is generated from the chain of inverter buffers these inverters are highly prone to supply noise. So here sine wave is used as the clock which will reduce the jitter entirely Periodic jitter is almost 2ps and frequency jitter is 20 KHz, which is too high that will reduce the efficiency of the ADC.To reduce this effect it is better to use the sine wave as clock instead of square wave clock which has low jitter spectrum. Here both periodic as well as frequency jitter is eliminated by replacing the square wave clock with that of the sine wave.

Figure 6: Represents the Output Waveform of the Current Steering Comparator The sine wave flash ADC of 4 bit with65mW is designed is and the output waveform in the fig6. Current steering comparator means a portion of current is steered from the other blocks or circuits , so that power can be reduced to the maximum because power is inversely proportional to the voltage

Figure 7: Schematic of 4 Bit Flash ADC

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Since sine wave sampling is very efficient to remove jitter effect from the circuits due to their less supply noise in the local oscillator. And again this is cascaded with the D flipflop which will delay the output. Current mode logic buffer will control the comparator d flipflop by providing the control signals. Again this thermometer code is given to the gray encode ROM which will convert the 16 bit thermometer code to 4 bit binary code.

Figure 8: Waveform for 4 Bit Flash ADC The sine wave clock can be generated using an on chip LC-VCO which will load the comparators which have the capability of directly driving the capacitance. CML buffer that separates the LC-VCO from the possible kickback noise. Resistively loaded CML buffer add to power consumption as large static current is needed to achieve near full rail swing, further injection locked VCO can be used as a clock buffer to drive the entire load capacitance. Jitter analysis of the flash ADC has to be done since it is very essential since it will affect the bits there by the efficiency of the ADC. Jitter is completely eliminated through the proposed technique.

EXPERIMENTAL MEASUREMENTS
The ADC is designed in 180nm CMOS technology with a supply voltage of 1V. Resolution of the proposed ADC is 4. Speed of the ADC is about 6GS/s which is the highest sampling rate , this high speed is the major advantage of flash ADC. ADC is capable of working in a frequency of 3GHz which can be used in wireless applications. This ADC can be used in the satellite transceivers because of its high speed. Power obtained by the proposed ADC is 65mW, but this high power consumption is reduced by the help of interpolation technique . After interpolating by a factor of 4 the power consumption is reduced to 19mW. SNR of the proposed ADC is 23.52dB and effective number of bits is 3.93 bits, which shows that the efficiency of the proposed ADC is very high. Relationship between comparator delay and input voltage shows that as the input voltage decreases the delay is decreasing in a linear fashion. Jitter effect is completely eliminated with the usage of sine wave instead of square wave by overcoming the problem of supply noise. Table1 shows the performance characteristic of the proposed flash ADC which offers low power along with high speed. The sampling rate is 6GS/s which assures high speed which can be used for UWB applications.

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Table 1: Measured Performance

CONCLUSIONS
Flash ADCs are architecture of choice in wireless applications especially in UWB applications. Since it is capable of working in 3GHz frequency with a speed of 6GS/s which can be used for the satellite applications . Here jitter is completely eliminated by replacing square wave with sine wave. When square wave is used periodic jitter obtained was 4ps and frequency jitter was 20 KHz but when sine wave is used as clock then both periodic as well as frequency jitter is reduced to 0s and 0Hz. SNR of the proposed flash ADC is 22.19dB and ENOB is 3.93bits. The effect of clock transition time for high speed , multi giga hertz T/H as well as ADC is analysed using a signal dependent ,nonlinear model. The interpolation ADC is energy efficient compared to the conventional ADC.

ACKNOWLEDGEMENTS
The authors would like to thank the reviewers for discussions and valuable suggestion. And special thanks to Mr. Rui Bai , Jingguang Wang for giving valuable information.

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