Digital Design Sec 2. Bus Architecture Digital Design Sec 2.

Bus Architecture
By : Dr. S. Thayaparan
Slide contents are from the following source of origin: 1. 2. 3. 4. 5. 6. http://en.wikipedia.org/wiki/Bus_(computing) http://www.arm.com/products/system-ip/amba/index.php http://en.wikipedia.org/wiki/Advanced_Microcontroller_Bus_Architecture http://www.arm.com/images/Tools_Flow_Large.jpg http://www.arm.com/products/system-ip/amba-design-tools/index.php http://www.cl.cam.ac.uk/teaching/0910/SysOnChip/sp6busnoc/index.html

Background A Computer System Bus

Bus is a subsystem that transfers data between components The technique was developed to reduce costs and improve modularity

Background A Computer System Bus

First generation buses are 8-bit parallel buses Second generation buses are 16 or 32 bit parallel buses Bus systems like PCI, PCI Express are used in Computers Buses can be : 1. Parallel buses - Carry data words in parallel on multiple wires 1. Parallel buses - Carry data words in parallel on multiple wires 2. Serial buses - Carry data in bit-serial form (eg. USB, FireWire, and Serial ATA) Most computers have both internal and external buses. An internal bus (local bus) connects all the internal components of a computer to the motherboard (and thus, the CPU and internal memory) An external bus connects external peripherals to the motherboard Network connections such as Ethernet are not generally regarded as buses Third generation buses have been emerging into the market since about 2001, including HyperTransport and InfiniBand. HyperTransport and InfiniBand. New technologies such as InfiniBand (Serial) and HyperTransport (auto-negotiated bit width, ranging from two- to 32-link interconnects) is further blurring the boundaries between networks and buses InfiniBand is intended to replace both internal buses like PCI as well as external ones like Fibre Channel USB serves as a peripheral bus IC can be used as both an internal bus, or an external (access) bus
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Background PCI vs PCI Express Buses

PCI (Peripheral Component Interconnect) is a local bus, designed by Intel in 1992 PCI is an interconnection system between a microprocessor and attached devices PCI 2.0 is no longer a local bus and is designed to be independent of PCI 2.0 is no longer a local bus and is designed to be independent of microprocessor design PCI is a parallel bus and it transmits 32 bits at a time in a 124-pin connection (the extra pins are for power supply and grounding) and 64 bits in a 188-pin connection PCI uses all active paths to transmit both address and data signals, sending the address on one clock cycle and data on the next In PCI, burst data can be sent starting with an address on the first cycle and a sequence of data transmissions on a certain number of successive cycles PCI Express (PCIe) is developed in 2002 and it is a two-way, serial connection that PCI Express (PCIe) is developed in 2002 and it is a two-way, serial connection that carries data in packets along two pairs of point-to-point data lanes PCIe doubles the data transfer rates of original PCI

A Sample Bus Architecture

Figure shows some typical example of I/O devices that might be attached to expansion devices. The traditional bus connection uses three buses (i) local bus , (ii) system bus and (iii) expansion bus 1. Local bus connects the processor to cache memory 1. Local bus connects the processor to cache memory and may support one or more local devices 2. The cache memory controller connects the cache to local bus and to the system bus. 3. System bus also connects main memory module 4. Input/output transfer to and from the main memory across the system bus do not interface with the processor activity because process accesses cache memory. 5. It is possible to connect I/O controllers directly on to 5. It is possible to connect I/O controllers directly on to the system bus. An efficient solution is to make use of expansion bus for this purpose 6. An expansion bus interface buffers data transfer between system bus and i/o controller on the expansion bus. This arrangement allows the system to support a wide variety of i/o devices and 5 at the same time, insulate the memory to process or traffic from i/o traffic.

Basic Bus with 1 Initiator and 3 Target

Basic Bus with 2 Initiator and 3 Target

Bridged Bus Structures

SoC Design-An Example

Block Diagram of a Multi-Core `platform' chip, used in a number of Networking Products

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Reusable IPs

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Bus Design Parameter

1. 2. 3. 4. 5. 5. Bus Type : Dedicated or multiplexed Arbitration : Centralized or distributed Timing : Synchronous or Asynchronous Bus width : Address, data Data Transfer Type : Read, Write, Read Modify Write, Read after write, block transfer Data Transfer Type : Read, Write, Read Modify Write, Read after write, block transfer

Bus Design Parameter in details

1. Bus Type: i) Dedicated bus: bus is permanently assigned only 1 function E.g. separate address and data lines; separate bus for memory and I/O modules Advantage: It gives high performance and less bus contention Disadvantage: Increased size and cost. ii) Multiplexed bus: bus is used for more than 1 funcion in different time zones E.g. 8085 microprocessor outputs A7- A0 in first clock cycles on pins AD7 AD0. Advantages: few pins lines are required. Low cost and save design space Disadvantages: slow in speed
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2. Bus Arbitration: Several bus masters connected to a common bus may require access to the bus at the same time. A selection mechanism called bus arbitration describes which device should be given access to the bus i) Centralized approach : A hardware device called bus controller or bus arbiter i) Centralized approach : A hardware device called bus controller or bus arbiter allocates bus. It uses one of the following type (1) Daisy chaining (For example, A-B-C-D-E-A : A loop) (2) Polling (3) Multiple priority levels ii) Distributed Approach: Each master has arbiter compared to only single in centralized approach. Equal responsibility is given to all devices to carry out arbitration process, without using a central arbiter process, without using a central arbiter 3. Bus Timing: i) synchronous timing : Every event is synchronized by the clock ii) asynchronous timing : Every event occurring depends on previous events of the bus.
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4. Bus width: It decides the number of lines to be used for address and data. More address lines means more memory can be accessed. e.g 16 line address can access 216 = 64 KB of Data locations where 20 address line can access 220 = 1MB of Data locations. More data lines means more number of bits can be transferred at a time. Therefore speed increases. 5. Data transfer type: 5. Data transfer type: A bus can support various type of data transfer 1) For multiplexed bus: a) Write operation : data is sent immediately after sending the address b) Read operation: First address is sent, then sufficient time is given to addressed device to output the data. Then, the data is read from the bus c) Read modify write: Read data transfer is followed by write data transfer at the same address. It stops other cpu to use the bus. d) Read after write: Writer transfer is followed with read transfer after some d) Read after write: Writer transfer is followed with read transfer after some access time. It is used to check the data write; used for checking purpose. e) Block operation: Number of data are transferred at the same address one after another. e.g. saving file in secondary storage 2) For non-multiplexed bus: Address and data outputted at the same time on different bus. It is a faster system.
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System Bus Standards for SOC, ASIC

AMBA 4.0 by ARM Ltd (Mainly 32, 64, 128 Bit parallel bus) STBus by STMicroelectronics (Bus width is programmable, parallel bus) Wishbone bus By Opencores - Free and open bus architecture (formerly from Silicore) IBM CoreConnect bus technology, used in Power systems, but also in many other SoCs like systems with the Xilinx MicroBlaze or similar cores IPBus By Integrated Device Technology (IDT) Altera Avalon - proprietary bus system for Alteras Nios II-SoCs
Note : Note : 1. OpenCores is the world's largest open source hardware community developing digital open source hardware through electronic design automation, with a similar ethos to the free software movement 2. OpenCores hopes to eliminate redundant design work and slash development costs 3. A number of companies have been reported as adopting OpenCores IP in chips
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System Bus Standards for Computers

S-100 bus Unibus VAXBI VAXBI Mbus STD Bus SMBus Q-Bus ISA Zorro II Zorro III CAMAC FASTBUS FASTBUS LPC HP Precision Bus EISA VME VME VXI NuBus TURBOchannel MCA Sbus VLB PCI PXI HP GSC bus HP GSC bus CoreConnect InfiniBand UPA PCI-X PCI-X AGP PCI Express Intel QuickPath Interconnect HyperTransport

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Advanced Microcontroller Bus Architecture (AMBA)

AMBA was introduced by ARM Ltd in 1996 It is widely accepted in industry as a system bus interconnect AMBA is widely used on a range of ASIC and SoC parts including applications processors used in modern portable mobile devices like applications processors used in modern portable mobile devices like smartphones First AMBA buses were Advanced System Bus (ASB) and Advanced Peripheral Bus (APB) In its 2nd version, AMBA 2, ARM added AMBA High-performance Bus (AHB) that is a single clock-edge protocol In 2003, ARM introduced the 3rd generation, AMBA 3, including AXI to reach even higher performance interconnect and the Advanced Trace Bus (ATB) as part of the CoreSight on-chip debug and trace solution (ATB) as part of the CoreSight on-chip debug and trace solution These protocols are today the de-facto standard for 32-bit embedded processors because they are well documented and can be used without royalties Important aspect of a SoC is not only its components but also how they are interconnected
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Advanced Microcontroller Bus Architecture (AMBA)

AMBA is a widely accepted solution for the blocks to interface with each other Objective of the AMBA specification is to: 1. 2. 3. 4. facilitate right-first-time development of embedded microcontroller products with one or more CPUs, GPUs or signal processors, be technology independent, to allow reuse of IP cores, peripheral and system macrocells across diverse IC processes encourage modular system design to improve processor independence, and the development of reusable peripheral and system IP libraries minimize silicon infrastructure while supporting high performance and low power on-chip communication.

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AMBA protocol specifications

AMBA specification defines an on-chip communications standard for designing high-performance embedded microcontrollers It is supported by the ARM Limited corporation with wide cross-industry It is supported by the ARM Limited corporation with wide cross-industry participation. AMBA 4.0 specification defines five buses/interfaces: 1. Advanced eXtensible Interface (AXI) 2. Advanced High-performance Bus (AHB) 3. Advanced System Bus (ASB) 4. Advanced Peripheral Bus (APB) 5. Advanced Trace Bus (ATB) Note : The timing aspects and the voltage levels on the bus are not dictated by the specifications

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CoreLink System IP & Design Tools for AMBA

CoreLink AMBA design tools from ARM comprise two products AMBA Designer (ADR-301) for configuring, generating and stitching RTL selecting, configuring and generating instances of Systems IP selecting, configuring and generating instances of Systems IP from Network Interconnect, through DMA controllers to Memory Controllers Once generated, ADR-301 allows the designer to connect each of these blocks together, and to generate a top level verilog design file. Further, ADR-301 output also includes an industry standard IP-XACT file for integrating into other 3rd party design flows Verification & Performance Exploration (VPE-301) for functional verification and performance optimisation of AMBA AXI based System verification and performance optimisation of AMBA AXI based System IP and processors To perform functional and performance exploration tasks on your generated block or sub-system. VPE-301 has the unique ability to not only monitor system performance, but also to capture statistical traffic profiles for replay and even modification
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Advanced eXtensible Interface (AXI)

AXI, the third generation of AMBA interface defined in the AMBA 3 specification, is targeted at high performance, high clock frequency system designs and includes features which make it very suitable for high speed sub-micrometer interconnect: features which make it very suitable for high speed sub-micrometer interconnect: 1. 2. 3. 4. 5. separate address/control and data phases support for unaligned data transfers using byte strobes burst based transactions with only start address issued issuing of multiple outstanding addresses easy addition of register stages to provide timing closure.

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Advanced High-performance Bus (AHB)

AHB is a bus protocol introduced in AMBA version 2 published by ARM Ltd company. It has the following notable features: 1. single edge clock protocol 1. single edge clock protocol 2. split transactions 3. several bus masters 4. burst transfers 5. pipelined operations 6. single-cycle bus master handover 7. non-tristate implementation 8. large bus-widths (64/128 bit) A simple transaction on the AHB consists of an address phase and a subsequent data phase (without wait states: only two bus-cycles). Access to the target device data phase (without wait states: only two bus-cycles). Access to the target device is controlled through a MUX (non-tristate), thereby admitting bus-access to one bus-master at a time AHB-Lite is a subset of AHB which is formally defined in the AMBA 3 standard. This subset simplifies the design for a bus with a single master The ARM AMBA Support FAQ page includes notes on how to integrate a full AHB master into an AHB-lite system and vice versa
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Advanced Peripheral Bus (APB)

APB is designed for low bandwidth control accesses Example : register interfaces on system peripherals This bus has an address and data phase similar to AHB, but a much reduced low complexity signal list Example : no bursts.

We continue with AMBA Spec Rev 2.0 We continue with AMBA Spec Rev 2.0

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APB
o o o o o o o o o o o o o 1.1 2.4 5.1 5.2.2 5.2.3 5.4.1 5.4.2 5.4.3 5.5.1 5.5.2 5.5.3 5.6.1 5.6.2 Overview of APB APB Signal List About APB Fig. 5.3 Wr Transfer Fig. 5.4Rd Transfer Fig. 5.5 Interface Diagram & note PENBLE Signal APB Bridge Fig. 5.6 APB Bridge Transfer Fig. 5.7 Slave Interface Description APB Slave Description Fig. 5.8 APB Slave Transfer Fig 5.9 Rd Transfer to AHB & Fig. 5.10 Rd Burst Fig. 5.11 Wr Transfer from AHB & Fig 5.12 Wr Burst

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AHB
o o o o o o 1.1 2.2 3.1 3.1.1 3.2 3.4 Overview of AHB AHB Signal List About AHB Fig. 3.1 AHB System Fig 3.2 Bus-Mux Interconnection Fig. 3.3 Simple Transfer Fig. 3.4 Transfer with Wait States Fig. 3.5 Multiple Transfers Fig. 3.6 Transfer Types Burst Operation Fig. 3.7 Four-beat wrapping burst Fig. 3.8 Four-beat incrementing burst Fig. 3.9 Eight-beat wrapping burst Fig. 3.10 Eight-beat incrementing burst
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o o o

3.5 3.6 3.6.1