ELEG4260

CMOS Integrated Circuits (Fall 2012)

Courtesy: slides from DIC 2/e and EE141 notes from Prof. Jan Rabaey

Wire

Updated: 23/10/2012

Tang Wai Chung, Matthew

Introduction
Traditionally interconnect wires were treated like second class citizens, only considered in special cases. The picture changes rapidly in deep submicron technology. The parasitic effects start to dominate speed, energy consumption and reliability. We need a careful and in-depth analysis of the role and behaviour of the interconnect wire.
2

Chances of Connections
Possible material for connections in a state-of-the-art process
1. multiple layers of aluminum or copper 2. at least one layer of polysilicon 3. even the heavily doped n+ or p+ diffusions
This wires form a complex geometry that introduces capacitive, resistive, and inductive parasitics

1. 2. 3.

cause an increase in propagation delay (lower performance) have an impact on the energy dissipation and power distribution cause extra noise & affect the reliability of the circuit.
3

The Wire
assume all wires lay on the same layer

Schematic

Physical

What does this actually look like electrically?

4

Wire Models

All-inclusive model

Capacitance only
5

Simplifications
It is slow and cumbersome to analyze using the all-inclusive model. You can make simplification(s) (with suitable assumptions).

Inductive effects can be ignored if the resistance of the wire is substantial enough. (R dominates L) When the wires are short, the cross section of the wire is large, or the interconnect material used has a low resistivity, a capacitance-only model can be used. (C dominates small R) When the separation between neighbouring wires is large, or when wires only run together for a short distance, interwire capacitance can be ignored (or modeled as a lumped cap. to ground)
6

Capacitance: The Parallel Plate Model

current flow

W
H

Electrical field lines

tdi

dielectric substrate

Permittivity
Material Free space Aerogels Polyimides (organic) Silicon dioxide Glass-epoxy (PCB) Silicon Nitride (Si3N4) Alumina (package) Silicon r 1 ~1.5 3-4 3.9 5 7.5 9.5 11.7
8

Fringing Capacitance
The wire is no longer flat when the technology scales down. We keep (W x H) as large as possible. WHY?

cfringe

tdi

cpp

An exact model for this geometry is difficult.

Model of Fringing-field Capacitance

H W H/2

10

Fringing vs. Parallel Plate

11

Interwire Capacitance
fringing

parallel

The floating capacitors form source of noise (crosstalk) and give negative impact on the performance.
12

Impact of Interwire Capacitance

13

Wire Area and Fringe Capacitances

area cap - unit: aF/m2

Bottom Plate
Active Poly Al1 Al2

fringe cap - units: aF/m

Field Poly 88 54 Al1 Al2 30 40 13 25 Al3 Al4 8.9 18 6.5 14

Al3

Al4

T o p
P l a t e

41 47 15 27 9.4 19 6.8 15

57 54 17 29 10 20 7 15 36 45 15 27 8.9 18 41 49 15 27 35 45

Al5

5.2
12

5.4
12

5.4
12

6.6
15

9.1
19

14
27

38
52
14

Interwire Capacitances
Layer Cap. Example Consider an aluminum wire of 10 cm long and 1m wide, routed on the first aluminum layer. Area cap.: (0.1 x 106 m) x 1 m x 30 aF/m2 = 3 pF Fringing cap.: 2 x (0.1 x 106 m) x 40 aF/m = 8 pF Poly 40 Al1 95 Al2 85 Al3 85 Al4 85 Al5 115

Total: 11 pF
Suppose now that a second wire is routed alongside the first one, separated with only min. allowed distance, then Cinter = (0.1 x 106 m) x 95 aF/m = 9.5 pF

How about the case when we move up to Al4? Try.

15

Wire Resistance

Sheet Resistance R
L H W

R1 R2

16

Interconnect Resistance Design Data

Material n- or p- well diffusion n+, p+ diffusion n+, p+ diffusion with silicide n+, p+ polysilicon n+, p+ polysilicon with silicide Aluminum Sheet Resistance (/) 1000 1500 50 150 35 150 200 45 0.05 0.1
17

A Polycide-gate MOSFET
Silicide Polysilicon SiO2
Compound material from silicon & refractory metal

n+ p

n+

Combine best properties of good adherence and coverage (Polysilicon) & high conductance (Silicide)
18

Interconnect Choice
Aluminum is the preferred material for the wiring of long interconnections. Polysilicon should only be used for local interconnect. Though sheet resistance of diffusion is comparable to that of polysilicon, the use of diffusion should be avoided due to its large cap. and the associated RC delay.
Pay attention to via/plug resistances as well.
19

Inductance
The inductance of a section of a circuit can always be evaluated with the fundamental formula:

A simpler approach relies on the fact that the product of cap. c and inductance l is a constant, when it is completely surrounded by a uniform dielectric medium

20

Inductance: Example
Consider an Al1 wire routed on top of the field oxide. c = (W x 30 + 2 x 40) aF/m2

Inductance per unit length of the wire, assuming a uniform dielectric of SiO2.
l = (3.9 x 8.854 x 10-12) x (4 x 10-7)/c W = 0.4 m W = 1 m W = 10 m c = 92 aF/m2 c = 110 aF/m2 c = 380 aF/m2 l = 0.47 pH/m l = 0.39 pH/m l = 0.11 pH/m

The resistance of the wire: r = 0.075/W /m The inductive part becomes equal to the resistive component at a frequency 30.6 GHz (given by l = 2fl = r)
21

The Ideal Wire

In schematics, wires occur as simple lines with no attached parameters or parasitics. These wires has no impact on the electrical behaviour of the circuit. A voltage change at one end propagates immediately to its other ends. When studying small circuit components such as gates, the wires tend to be very short and parasitics ignorable.
22

The Lumped Model

When only a single parasitic component is dominant, it is useful to lump the different fractions into a single circuit element. When R and L are small, we may lump the distributed cap. into a single capacitor.
Rdriver Vout Vout

driver

Vin cwire

clumped

23

Lumped Cap.: Example

A driver with a source resistance of 10 k is used to drive a 10-cm-long, 1-m-wide Al1 wire.

When applying a step input, the transient response we have where the time constant Propagation delays: t50% = 0.69 x 10 k x 11 pF = 76 ns

t90% = 2.2 x 10 k x 11 pF = 242 ns

How can we improve the delays?
24

The Lumped RC Model

Adding the resistive component to the Lumped-Cap. model. Lumps the total wire resistance of each wire segment into one single R, and similarly combines the global capacitance into a single C. The lumped RC model usually gives a resistor-capacitor network, called RC tree:
The network has single input node s (root). All the capacitors are between a node and the ground (0 V). The network does not contain any resistive loops (tree).

25

Tree-structured RC Network
A unique resistive path exists between the source node s and any node i. The total R along the path: path resistance Rii e.g. R44 = R1 + R3 + R4 Shared Path Resistance Rik
e.g. Ri4 = R1 + R3

2 R2 R1 C1 C2

1
R3 3

4
R4 C4

C3

Ri
i Ci

Elmore Delay

e.g. Di = C1Ri1 + C2Ri2 + C3Ri3 + C4Ri4 + CiRii Di = C1R1 + C2R1 + C3(R1+R3) + C4(R1+R3) + Ci(R1+R3+Ri) Di = R1(C1+C2+C3+C4+Ci) + R3(C3+C4+Ci) + RiCi

26

Non-Branched RC Chain
R1

s
C1

R2 C2

Ri-1 i-1 Ri Ci-1 Ci

RN CN

VN

shared path resistance Rik

27

Time Constant of RC Wire

If we partition the wire into N identical segments each has length L/N each has resistance and capacitance of rL/N and cL/N
lumped resistance

For large N,

lumped capacitance

The delay of a wire is a quadratic function of its length! The delay of the distributed rc line is one half of the delay of the lumped RC model, which is a pessimistic view on the delay of resistive wire.
28

Elmore Delay
Elmore delay formula has proven to be extremely useful. In addition to analyzing wires, the formula can be used to approximate the propagation delay of complex transistor networks. Recall that we model transistor as switch with resistance and capacitance. It is proven that the Elmore delay always situated between the minimum and maximum bounds Elmore approximation is valid.
Excellent first-order approximation method for delay.
29

Conclusions
Understand the need for analyzing impact of interconnect wires due to technology scaling
How it affects robustness and performance

Reveal the various parasitic resistance, capacitance and inductance of wires

An exact model capturing all the quantities is difficult to be developed.

Develop models for first-order estimation under different situations

Lumped RC Elmore delay model
30

Advanced Topic

THE DISTRIBUTED RC LINE

CONTENT ON THIS PART WILL NOT BE EXAMINED 31

The Distributed RC Line

1. How pessimistic the lumped RC model is? 2. What is the actual response of at different points of the wire? 3. When can we ignore the rc delays? or when the rc delays is significant?

32

Distributed Model
rL rL cL

s
cL

Vi-1

rL cL

Vi

rL cL

Vi+1

rL cL

Vout

Focus on node i, solving for Vi

Taking L to 0, (with fundamental theorem of calculus)

The famous diffusion equation (similar to heat equation)
33

Distributed Model (2)

Simulated step response of resistive-capacitive wire as a function of time and place.

Driving these RC lines and minimizing the delay and signal degradation is one of trickiest problems in modern IC digital design.
34

Step Response of RC networks

Voltage Range 0 50% (tp) 0 63% () Lumped RC Network 0.69 RC RC Distributed RC Network 0.38RC 0.5RC

10% 90% (tr) 0 100% (t)

2.2RC 2.3RC

0.9RC 1.0RC

35

Example
Consider again the 10-cm-long, 1-m-wide Al1 wire. c = 110 aF/m; r = 0.075 /m

With the previous table, we can estimate the propagation delay

tp = 0.38 x (0.075 /m) x (110 aF/m) x (105 m)2 = 31.4 ns Suppose we have the same wire implemented in polysilicon (r=150 /m and Al5 (r = 0.0375 /m), then Poly: tp = 0.38 x (150 /m) x (88 + 2 x 54 aF/m) x (105 m)2 = 112 s Al5: tp = 0.38 x (0.075 /m) x (5.2 + 2 x 12 aF/m) x (105 m)2 = 4.2 ns You need to really careful about the choice of interconnect layers.
36

Design Rules of Thumb

RC delays should be considered only when tpRC is comparable or larger than the tpgate of the driving gate. RC delays become dominant for interconnect wires longer than the critical length

RC delays should be considered only when the rise (fall) time at the line input is smaller than RC, the rise (fall) time of the line. Consider only when
37

RC Versus Lumped Cap.

Rs

(rw, cw, L)

Vout

Vin

Distributed RC line

38

RC Versus Lumped Cap.

Rs (rw, cw, L)

Vout

Vin

A gate of Rs = 1 k driving an Al1 wire of 1 m wide has Lcrit = 2.67 cm

Delay by wire resistance becomes dominant when or

39