ELEC 3400 VI. Operational Amplifiers: 1. MOS Differential Pair With Resistive Loads

ELEC 3400 VI .
Operational Amplifiers

HKUST 2011 Fall 6 1 Ki
1. MOS Differential Pair with Resistive Loads

A very important amplifier stage is the differential pair. It consists of
a current source (sink) biasing a pair of matched input transistors, that
is, (W/L)
1
=(W/L)
2
, and each transistor drives a load. The input
transistors can either be NMOS or PMOS transistors, and two
implementations with resistive loads (R
1
=R
2
=R) are shown below.

Let us consider the implementation with NMOS input transistors for
discussion. The transistor M
b
biased with a gate voltage V
b
serves as
the current sink I
b
. To bias the differential pair properly, a dc voltage
is applied to both V
i+
and V
i
to keep M
1
and M
2
working in the
active region. Because this voltage is common to both input nodes, it
is called the common mode voltage V
cm
.

1
M
dd
V
1
R
2
R
2
M
b
M
b
V
1
M
dd
V
1
R
2
R
+ i
V
o
V
+ o
V
i
V
2
M
b
M
b
V
+ i
V
i
V
+ o
V
o
V
x
V
x
V
1
M
dd
V
1
R
2
R
2
M
b
M
b
V
+ i
V
i
V
+ o
V
o
V
cm
V
x
V
b
I
I I
ELEC 3400 VI . Operational Amplifiers
Since (W/L)
1
=(W/L)
2
, by symmetry, the drain currents of M
1
and
M
2
are equal:
I
d1
=I
d2
=I =I
b
/2.
Both V
o+
and V
o
are then equal, and the output common mode
voltage V
ocm
is
V
o+
=V
o
=V
ocm
=V
dd
I
b
R.
In general, all transistors should operate in the active region. For
simplicity, let all transistors have the same gate overdrive voltage V
ov
.
Hence, for the above equations to hold, the lowest V
cm
is
V
cm
=V
gs1
+V
ov
=V
tn
+2V
ov

For V
cm+
=V
dd
, V
ds1
=V
ov
when V
g1
=V
dd
. Now, V
x
=V
g1
V
gs1
=
V
dd
V
tn
V
ov
. For M
1
to remain in the active region, we require
I
b
R <V
dd
V
ov
V
x
=V
tn
,
or R <2V
tn
/I
b
.

The input common mode range is defined as the extreme input
voltages such that all transistors in the amplifier are still operating in
the active region, and is thus V
cm
to V
cm+
.

Example:
Given
n
C
ox
=50A/V
2
, V
tn
=0.8V, (W/L)
b
=80, (W/L)
1
=(W/L)
2
=40,
n
=0/V. Also, V
dd
=5V, V
b
=1V and V
cm
=2V. Find R such that the
output swing is the largest. With this R, what is V
cm+
and V
cm
?

Solution:
I
b
=5080(1 0.8)
2
=80A
I =I
b
/2 =40A
With (W/L)
1
+(W/L)
2
=(W/L)
b
, we have V
ov1
=V
ov2
=V
ovb
=0.2V.
Given V
cm
=2V, we have
V
x
=V
g1
V
gs1
=2 1 =1V.
To maximize the output swing, V
ocm
=1 +(51)/2 =3V, and
R =(V
dd
V
ocm
)/I =2/40 =50kO.

With V
ocm
=3V, the highest V
x
to keep M
1
and M
2
in the active
region is 3 0.2 =2.8V. The corresponding V
cm+
is then
V
cm+
=V
x
(highest) +V
gs1
=2.8 +1 =3.8V.
Also, V
cm
=V
x
(lowest) +V
gs1
=0.2 +1 =1.2V.
The input common mode range is then 1.2V to 3.8V.

2. Diff. Pair with Resistive Loads: Large Signal Analysis

Suppose V
i
stays constant and V
i+
increases. Then I
1
increases and I
2

decreases (because I
1
+I
2
=I
b
, a constant), driving the drain of M
1

down and the drain of M
2
up. Therefore, V
d1
is the negative output
node V
o
, and V
d2
is the positive output node V
o+
.

1
M
dd
V
1
R
2
R
2
M
+ i
V
i
V
+ o
V
o
V
cm
V
x
V
b
I
1
I
2
I
cm
V
2 / v
id
+ 2 / v
id

For normal operation, a differential input signal v
id
is applied across
V
i+
and V
i
, such that
V
g1
=V
i+
=V
cm
+
2
v
id

V
g2
=V
i
=V
cm

2
v
id

and V
i+
V
i
=v
id

Clearly,
V
o+
=V
dd
I
2
R
and V
o
=V
dd
I
1
R

The differential output signal is
V
o+
V
o
=v
od
=(I
1
I
2
)R.
At this point, we skip the computation details and only state the
results of I
1
and I
2
as follows:
I
1
=
2
I
b
+
2
I
b
2
ov
id
V 2
v
1
|
|
.
|
\
|
ov
id
V
v

and I
2
=
2
I
b

2
I
b
2
ov
id
V 2
v
1
|
|
.
|
\
|
ov
id
V
v

The differential current is
i
d
=I
1
I
2
=
2
ov
id
V 2
v
1
|
|
.
|
\
|
ov
id
V
v
I
b

A typical plot is shown below.

0 5 . 0
2
0 . 1
ov id
V / v
b 2 , 1
I / I
5 . 0 0 . 1
5 . 0
0 . 1
1
I
2
I
2

Observe that the transconductance of M
1
and M
2
is
g
m1
=g
m2
=
tn GS
b
V V
) 2 / I ( 2
=
ov
b
V
) 2 / I ( 2

With v
id
<<2V
ov
, the square root terms are approximately unity, and
I
1
=
2
I
b
+g
m1
2
v
id


and I
2
=
2
I
b
g
m1
2
v
id

The differential current is thus
I
1
I
2
=i
d
=g
m1
v
id

Recall
v
od
=V
o+
V
o
=(I
1
I
2
)R
=g
m1
v
id
R
A
dm
=
id
od
v
v
=g
m1
R.
Hence, a linear amplifier is obtained. To increase the linear range of
the input signal, V
ov
should be as large as possible.

3. Diff. Pair with Resistive Loads: Small Signal Analysis

The small signal model of the differential pair is shown below.

@v
o
: g
m1
(v
i+
v
x
) +
1 ds
x o
r
v v
+
R
v
o
=0 (1)
@v
o+
: g
m1
(v
i
v
x
) +
1 ds
x o
r
v v
+
+
R
v
o+
=0 (2)
@v
x
:
R
v
o
+
R
v
o+
=
dsb
x
r
v
(3)
dsb
r
) v v (
g
x i
1 m
R R
+
+ i
v
o
v
+ o
v
1 ds
r
) v v (
g
x i
1 m
+
x
v
+
i
v
1 ds
r
(1) g
m1
v
i+
=
1 ds
o
r || R
v

+
1 ds 1 m
x
r || ) g / 1 (
v
(4)
(2) g
m1
v
i
=
1 ds
o
r || R
v
+
+
1 ds 1 m
x
r || ) g / 1 (
v
(5)
(4) (5) g
m1
(v
i+
v
i
) =
1 ds
o o
r || R
v v
+

With v
id
=v
i+
v
i
and v
od
=v
o+
v
o
, the differential mode gain is
A
dm
=
id
od
v
v
=
+
+
i i
o o
v v
v v
=g
m1
(R||r
ds1
)
(3) in (4)+(5) g
m1
(v
i+
+v
i
) =
1 ds
r || R
R
dsb
x
r
v
+
1 ds 1 m
x
r || ) g / 1 (
v 2
(6)
Note that V
i+
and V
i
are applied differentially, with V
i+
=V
cm
+v
id
/2
and V
i
=V
cm
v
id
/2. With v
i+
=v
id
/2 and v
i
=v
id
/2, and (6) gives
v
x
=0 (7)
and v
o+
=g
m1
(R||r
ds1
)
2
v
id
(8)
v
o
=g
m1
(R||r
ds1
)
2
v
id
. (9)

Equation (7) means that v
x
can be considered as the virtual ground.
As such, the differential pair with resistive load can be analyzed using
a half circuit.

where v
o
=
2
v
od
=g
m1
(R||r
ds1
)
2
v
id

R
=
+
2
v
v
id
i
o
v
1 ds
r
i 1 m
v g
gnd v
x
=
A
dm
=
id
od
v
v
=g
m1
(R||r
ds1
)
The input and output impedance can easily be found to be:
R
i
=
R
o
=2(R||r
ds1
)

4. Differential Pair with Active Loads: Small Signal Analysis

The resistive loads can be replaced by PMOS transistors biased in the
active region. The gain will thus be enhanced. A useful structure is to
replace the resistive loads by a PMOS current mirror, and produce a
differential pair with a single-ended output. Note that M
b
is relabeled
as M
5
, and V
x
as V
1
.

1
M
dd
V
o
V
2
M
+ i
V
i
V
5
M
b
V
3
M
4
M
1
V
2
V

Principle of operation: For simplicity in symbol, v
i
is used instead of
v
id
. Now, a voltage of V
i+
=V
cm
+v
i
is applied at the gate of M
1
,
and a voltage of V
i
=V
cm
v
i
is applied at the gate of M
2
. I
1
is then
larger than I
b
/2, and I
2
is smaller than I
b
/2. The increase in I
1
is
supplied by M
3
, which is then mirrored to M
4
. Therefore, at V
o
, a
current larger than I
b
/2 is sourced by M
4
, and a current smaller than
I
b
/2 is sunk by M
2
. The excess current that appears at V
o
drives V
o

high.

To analysis the gain of the differential amplifier, the small signal
model is drawn, as shown below. Besides the gain A =v
o
/v
i
(=A
dm
),
we also want to compute v
1
/v
i
, to verify that v
1
can actually be
considered as a virtual ground.



2 ds
r
1 ds
r
4 ds
r
5 ds
r
) v v (
g
1
1 m
+
3 m
g / 1
2 4 m
v g
) v v (
g
1
2 m
3 ds
r
1
v
2
v
o
v

Assumptions: g
m1
=g
m2
, r
ds1
=r
ds2
, g
m3
=g
m4
, r
ds3
=r
ds4
, g
mi
r
dsj
>>1
v
+
=v
=v
i
/2
A
dm
=
+
v v
v
o
=
i
o
v
v
=g
m1
(r
ds2
||r
ds4
)

Due to the diode-connected transistor of M
3
, the left branch is not the
same as the right branch. With this asymmetry, the validity of using
the half-circuit technique becomes questionable, and the small signal
analysis becomes quite tedious and not much insight can be gained in
the operation of the differential pair. However, observe that v
1
=
[1/(2g
m1
r
ds1
)]v
o
is very small compared to v
o
. We may assume indeed
v
1
= 0, that is, by assuming that v
1
is an ac ground. With this
assumption, the analysis is much simplified, and good approximated
result can be obtained.

5. Gain Analysis using Current Steering Principle

By assuming that v
1
is an ac ground, a simpler way to compute the
gain of the differential pair is to use the current steering principle,
which account for steering the changes in currents due to the inputs
v
i+
and v
i
to the change in current at v
o
, and multiply it with the
output resistance at v
o
.

Let V
i+
= V
cm
+
2
v
id

1
M
dd
V
o
v
2
M
2
v
id
5
M
b
V
3
M
4
M
2
v
id
2
g v
1 m id
2
g v
1 m id
2
g v
1 m id
V
i
= V
cm

2
v
id

The increase in current of M
1
, M
3
and M
4
are Ai/2 = v
id
g
m1
/2, while
the decrease in current of M
2
is Ai/2 = v
id
g
m1
/2. Hence, the change
in voltage at the output node is

v
o
= AiR
o
= v
id
g
m1
(r
ds2
||r
ds4
)
and
A
dm
=
id
o
v
v
= g
m1
(r
ds1
||r
ds3
).
This is the same result as obtained using the small signal model and
making appropriate approximations.

6. Generic Two-Stage Operational Amplifiers

In ELEC 2200, we learned that an operational amplifier (op amp) has
a differential input and a single-ended output. One may suggest using
a differential pair with active loads as the op amp, but a simple
analysis would show that the output swing is very limited, as
discussed in pp. 62. Moreover, the gain of a single-stage amplifier is
not high enough. Even a gain of 500 V/V (54dB) is difficult to get. To
achieve a gain of 10,000 V/V (80dB), a two-stage design is needed.
A generic two-stage op amp is obtained by cascading a differential-
to-single-ended amplifier (1
st
stage) with an inverting amplifier (2
nd

stage). Depending on the load (resistive or capacitive), a third buffer
stage may be added to deliver the power needed. To ensure stability, a
compensation network is needed (to be covered in ELEC 4420).

1
A
2
A
1
+
amplifier ended single

to - al differenti
stage 1st
amplifier nverting i
stage 2nd
(optional)
stage buffer
on compensati
+
V
V
o
V

For simplicity, let the buffer stage be left out. For each amplifier
stage, if the input impedance is zero and the output impedance
infinite, the gain is A = A
1
A
2
. In general, both the input and output
impedances are finite, and the gain is given by
A
dm
=
+
v v
v
o
=
2 i 1 o
2 i
R R
R
+
L 2 o
L
R R
R
+
A
1
A
2

The reduction in gain is known as the loading effect.

) v v (
A
1
+

1 i
R
1 o
R
2 i
R
1 o 2
v A
2 o
R
+
v
v
o
v
1 o
v

L
R


For CMOS op amps, the input can be a pair of NMOS or PMOS
transistors. The NMOS case is shown below.

The V
+
and V
are referenced to the output of the whole op amp, not

the output of the differential amplifier. As an inverting amplifier is
cascaded to the differential stage, V
+
is now at the gate of M
2
, and V

the gate of M
1
(compare the connection shown in pp.6-10).

Although the output impedances of both the differential and inverting
amplifiers are finite, the input impedances are infinite, so no loading
effect occurs, and the gain is given by
A
dm
=
+
v v
v
o
= A
1
A
2

The compensation network with C
c
and R
z
is used to make the op
amp stable.

7. Transistor Sizing of 2-Stage Op Amp

Consider the 2-stage op amp with PMOS input transistors. In general,
V
tn
|V
tp
|,
n
|
p
|,
n
C
ox

p
C
ox
, and we define k
=
n
/
p
(>1).

+
V
V
dd
V
1
M
3
M
4
M
5
M
2
M
7
M
6
M
z
R
c
C
+
1 ds
V
+
| V |
3 gs
o
V
1
V
b
V


The bias currents are related to the speed of the op amp, which will be
discussed in ELEC 4420. Let the bias current for the differential pair
be 2MI and that of the inverting amplifier be NI. The sizes of the
transistors are designed to have the same V
ov
. Therefore,

(W/L)
3
= (W/L)
4
= M
(W/L)
1
= (W/L)
2
= k
(W/L)
3
= k
M
(W/L)
5
= 2(W/L)
1
= 2k
M
(W/L)
6
= N
(W/L)
7
= k
(W/L)
6
= k
N

If (W/L)
4
: (W/L)
7
M : N, then V
gs7
V
gs3
, giving V
ds3
V
ds4
, and
the two drain currents I
ds3
and I
ds4
will not be equal, thus causing an
offset voltage at the input, and a systematic error occurs.

Even with (W/L)
4
: (W/L)
7
= M : N, a systematic error still occurs,
because the output voltage V
o
does not necessarily settle at V
dd
/2
when v
id
= 0. The exact value of V
o
can be computed approximately
by considering the bias current of the inverting amplifier NI:
NI =
2
1
n
C
ox
7
L
W
|
.
|
\
|
(V
gsn
V
tn
)
2
(1 +
n
V
dsn
)
=
2
1
p
C
ox
6
L
W
|
.
|
\
|
(|V
gsp
| |V
tp
|)
2
(1 + |
p
V
dsp
|)

dd
V
1
M
2
M
3
M
4
M
5
M
6
M
7
M
V
+
V
o
V
b
V
MI 2 NI
MI NI MI

With (W/L)
6
= k
(W/L)
7
and V
gsn
V
tn
= |V
gsp
| |V
tp
| = V
ov
, we have,
1 +
n
V
dsn
= 1 + |
p
V
dsp
|

n
V
o
= |
p
|(V
dd
V
o
)
V
o
=
| |
| |
p n
p
+

V
dd

The output offset voltage is thus
V
o
(os) =
| |
| |
p n
p
+

V
dd

2
1
V
dd
=
|) | ( 2
| |
p n
n p
+

V
dd

and the input offset voltage is
V
os
=
dm
o
A
) os ( V
.

To finalize the exact value of L (and thus W), we may need to
consider noise issues (to be covered in ELEC 4420). A rule of thumb
for analog designs is to use 1.5 to 3 times the minimum length of the
process, for better matching accuracy, and smaller effect due to
channel length modulation. For example, if a 0.5 process is used, the
minimum length is 0.5m (= 2), and we may choose L = 0.75m to
1.5m.

Example: Compute the gain of the following 2-stage op amp.

+
V
dd
V
o
V
3
M
1
M
2
M
a
M
b
M
b
R
4
M
V
150 150
50
300
25
5
M
6
M
7
M
300 75
100 50
A 100
b
I
z
R
c
C
L
C
A 50 A 50
25/4
c
M
a
R
A 100
200 A 200 A
1
V

For the following computation, let

n
C
ox
= 100A/V
2
,
p
C
ox
= 33.3A/V
2

n
= |
p
| = = 0.05/V V
tn
= |V
tp
| = 0.8V
V
dd
= 5V, R
a
= 4kO, R
b
= 72kO

Recall in the active region, V
ds
> V
gs
V
tn
, and
I
d
=
2
1
n
C
ox
L
W
(V
gs
V
tn
)
2
(1 +
n
V
ds
)
g
m
=
gs
d
V
I
c
c
=
tn gs
d
V V
I 2
~
d ox n
I
L
W
C 2

ds
r
1
=
ds
d
V
I
c
c
= I
d
ds
V 1 +

r
ds
~
d
I
1
.

Bias Calculation

Remember when computing the DC biasing, the channel length
modulation parameters may be set to = 0/V, and it can be shown
easily that
I
b
= 50A
V
ova
= 400mV
V
ovb
= 200mV
and

5
L
W
|
.
|
\
|
=
6
L
W
|
.
|
\
|
= 4
c
W
L
| |
|
\ .
I
d5
= 450A = 200A
I
d1
= I
d2
= 200A/2 = 100A
g
m1
= g
m2
=
d1
ov1
2I
V
=
2 100
0.2

= 1m A/V
(Note that
n
= 3
p
, and all transistors are scaled according to the
same "current density" and should have the same V
ov
as V
ovb
).
r
ds1
= r
ds2
=
1 d
I
1
=
1
0.05 100
= 200kO



DC Gain Analysis

The small signal model of the 2-stage amplifier is

A
v1
=
id
1
v
v
= g
m1
(r
ds2
||r
ds4
)
= 1m(200k||200k) = 100 V/V (=40dB)
A
v2
=
1
o
v
v
= g
m7
(r
ds6
||r
ds7
)
g
m6
= g
m7
=
d6
ov6
2I
V
=
2 200
0.2

= 2m A/V
r
ds6
= r
ds7
=
7 d
I
1
=
1
0.05 200
= 100kO
A
v2
= 2m(100k||100k) = 100 V/V (=40dB)
A
dm
=
id
o
v
v
= A
v1
A
v2
= 10,000 V/V (= 80dB)

The input resistance of the op amp is clearly

R
in
=

and the output resistance is

R
out
= r
ds6
||r
ds7

id 1 m
v g
2 ds
r
4 ds
r
1
v
m6 1
g v
6 ds
r
7 ds
r
o
v

8. Op Amp Circuits

8.1 I ntegrator

An op amp can be connected to do integration.

+
) t ( v
o
) t ( v
i
R
C
) t ( i
+ ) t ( v
c

R
) t ( v
i
= i(t) =
dt
) t ( dv
C
c

=
dt
) t ( dv
C
o

, v
o
(t) =
}
dt ) t ( v
RC
1
i
.

Hence, the output voltage is the integral of the input voltage. If v
i
(t)
is sinusoidal, i.e., v
i
(t) = V
i
coset, we may use phasor to analyze the
circuit.

+
o
V
i
V
R
sC
1
R
V
i
=
sC / 1
V 0
= sCV
o

o
V
o
=
sCR
1
V
i

=
CR j
1
e
V
i

In terms of transfer function, we write
H(s) =
) s ( V
) s ( V
i
o
=
sCR
1

which can be expressed as
H(s) =
o
/ s
1
e
=
s
o
e
(e
o
=
CR
1
)
or H(je) =
o
/ j
1
e e
= ) 90 180 (
o o
o
Z
e
e
=
o
o
90 Z
e
e
.
The corresponding Bode plot is

H Z
o
e
| H | log 20
e log
e log
o
90
dec / dB 20

The magnitude plots of e
o
/s and e
o
/s are the same, but the phase
plots are different.

H Z
e log
o
90
H Z
e log
o
90
s
o
e
s
o
e

N.B.
(1) Recall in sinusoidal analysis, d/dt corresponds to je, then
written as s, i.e., d/dt s. So "s" represents differentiation.
Now, 1/s can be regarded as the inverse operation of d/dt.
Hence, 1/s is integration.

(2) The action of integration can be regarded as accumulating the
charge passed through R and storing it in C.

(3) In practice, the above circuit will not work since the gain at DC
is infinite. Any noise at DC will drive the circuit to saturation.
For the circuit to function properly, we need to put a large
resistor R
2
across C to limit the gain. A common, but
erroneous, saying is that there is no DC path to ground at v
.

(4) By adding R
2
across C, the integrator is turned into a first order
low pass filter.

8.2 First Order Lowpass Filter

For the integrator with a resistor connected across the capacitor, we
can compute the corresponding transfer function.

+
) s ( V
i
) s ( V
o
2
R
C
1
R

H(s) =
) s ( V
) s ( V
i
o
=
1
sC
1
2
R
|| R

=
2
2
1
sCR 1
R
R
1
+
=
2
p
s
1
2
1
1
R
R
+
( p
2
=
2
CR
1
) .
Clearly, this is a first order function, and the Bode plots are as
follows.

) (loge
) (loge
2
p
| H | log 20
H /
o
90
o
0
e
e
t
e
2
p
o
180
o
270
1 2
R / R
2
p 1 . 0
2
p 10
t
e

In fact, we call it a first order lowpass function because signal
below f
2
(=p
2
/2t) has approximately constant gain (R
2
/R
1
), while
signal at high frequencies are being attenuated. Hence, the circuit
only allows low frequency to pass through, and it is known as a 1
st

order lowpass filter. Also, f
2
is known as the 3dB bandwidth of the
circuit.


Now, by changing the value of R
2
, we may adjust the DC gain of the
function. At the same time, the 3dB frequency will change. But if we
multiply the gain and the bandwidth together, we get
gain bandwidth = GBW =
1
2
R
R
2
CR
1
=
1
CR
1
= e
t
.

We call GBW the gain bandwidth product of the filter, and GBW is
equal to e
t
, the unity gain frequency of the filter.

Observe that at high frequencies, especially for e >>e
2
,
H(s) ~
2 1
2
sCR
1
R
R
=
1
sCR
1
=
s
t
e
.
Hence, at high frequencies, the circuit functions as an integrator.

Next, refer to the transfer function of an integrator H'(s):
H'(s) =
s
t
e
.
Since, H'(s) is the ratio of output over input, the corresponding
magnitude |H'(je)| can be regarded as the gain of the circuit at the
frequency e (or f =e/2t), and we have
|H(je)| e = e
t
.
or gain freq. = unity gain freq.

Hence, on the 20dB/dec line (the magnitude plot of an integrator),
the product of the gain and the frequency is always a constant. When
the gain is unity, the corresponding frequency e
t
(or f
t
=e
t
/2t) is the
unity gain frequency. For the 1
st
order lowpass filter, the sloping
portion is 20dB/dec, and so similar terminology is used.

) (loge
s ' p different
2
| H | log 20
e
t
e
s ' R different
2
1
sCR
1
) s ( ' H =

8.3 Differentiator

Rearrange the position of R and C
of an integrator turns the circuit
into a differentiator:

i(t) =
R
) t ( v 0
o
=
dt
) t ( dv
C
c
=
dt
) t ( dv
C
i

, v
o
(t) =
dt
) t ( dv
RC
i
.

If sinusoidal steady state is considered, then we should use phasor:
I =
R
0
o
V
=
) C j /( 1 e
i
V

, V
o
= jeRC V
i
.

In terms of transfer function, we have
H(s) =
) s ( V
) s ( V
i
o
= sRC =
1
p
s
(p
1
=
RC
1
) .
The Bode plots are shown below.

The gain of this differentiator at high frequency has to be limited to
avoid noise problem, and a small capacitor should be added as shown.

+
) t ( v
i
) t ( v
o
R
C
+
c
v
) t ( i
1
p
1
p 1 . 0
1
p 10
dB 20
dB 40
| H | log 20
e
1
p
1
p 1 . 0
1
p 10
o
90
H /
e
+
) t ( v
i
) t ( v
o
R
1
C
2
C
1 2
C C <<

8.4 First Order Highpass Filter

The transfer function and Bode plots of a 1
st
order highpass filter are:

+
) s ( V
i
) s ( V
o
R
1
C
2
C
) (loge
) (loge
R C
1
1
| H | log 20
H /
o
90
o
0
e
e
R C
1
2
2 1
C / C
o
180
R C
10
2
R C
1 . 0
2
H(s) =
) s ( V
) s ( V
i
o
=
R sC 1
R sC
2
1
+

ELEC 3400 VI. Operational Amplifiers: 1. MOS Differential Pair With Resistive Loads

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