OOPS Concepts System Verilog

What is SystemVerilog?
qSystemVerilog is a hardware description and Verification language(HDVL) qSystemVerilog is an extensive set of enhancements to IEEE 1364 Verilog2001 standards qIt has features inherited from Verilog HDL,VHDL,C,C++ qAdds extended features to verilog

Verilog Shortcomings

Verilog

Static components Deals at low lever of abstraction Declaring a transaction Passing transaction from one component to another Ex: USB Frame

Scenario Generation

Result Checking

Summary of Verilog Shortcoming

Module can not take care of Complex frame declaration Being static in nature, difficult to declared dynamic scenario Module can not be declared in array Module can not be passed as argument Module can not be take care of encapsulation, inheritance for future revisions

Shortcoming Cont..

BFM does not support module DPI Functional Coverage Connecting Components Event scheduling Polymorphism

SystemVerilog Features

Literal Values : Logic Arrays : Dynamic in Nature

Ex: Queue, Assoc. Array, Dynamic Array Encapsulation, Inheritance, Polymorphism

Class

Random Constraints Inter Process Synchronization

SystemVerilog Features Contd

Scheduling Scemantics Clocking Blocks Program Block Assertions Interface Functional Coverage DPI

Introduction

Objects are the building blocks of OOP technology The key fetures to understand OOPs is that object basically have two aspects

State Behavior

OOPS concepts

Class Object Properties Method Inheritance Encapsulation Polymorphism

Class

Central point of OOP Defines the properties and behavior of objects made of that class class packet; bit [31:0] data; function write_data; endfunction function read_data; endfunction endclass

Object

Class is the central point of OOPS Object is the basic unit of object orientation with behavior, identity and state An object is expresed by the variables and methods of that class packet p1, p2; p1 = new(); p2 = new();

Variables & Methods

Attributes are defined by variables and behaviors are represented by methods Methods define the abilities of an object.

Inheritance

Inheritance is a mechanism of reusing and extending existing classes without modifying them. Subclass inherits all members of parents The objects are distinguished from each other by some attributes but share some/most of the common attributes

Better data analysis Reduces development time

Example
Class packet; data [255:0]; function set_data; endclass

Class packet_A extends packet; function get_data; endclass

data,set_data are members of class packet Data, set_data are members of class packet_A get_data is the additioonal member that packet_A has

Encapsulation

Seprating objects state from its behavior This helps in hiding an object's data describing its state from any further modification by external component In system verilog, we have three types data hding mechanism

Private members Protected members Public members

Polymorphism

Polymorphism means many shapes Functions can be implemented with the same name but behaviour is different and correct execution takes place at run time

System Verilog

Introduction

System verilog is built on top of verilog Improves the readability, productivity, reusability of verilog based code Help to create more concise HW description Extensive support for directed and constrained random testbench , coverage driven verification, assertion based erification

New constructs

Extensions to data types for better encapsulation and compactness of code and for tighter specification

C data types: int, typedef, struct, union, enum bounded queues, logic (0, 1, X, Z) and bit (0, 1), tagged unions for safety Dynamic data types: string, classes, dynamic queues, dynamic arrays, associative arrays including automatic memory management freeing users from de-allocation issues dynamic casting and bit-stream casting Automatic/static variables

Extended operators for concise description

Wild equality and inequality built-in methods operator overloading streaming operators

byte q[$]; Packet p = new;void(p.randomize()); q = {<< byte{p.header, p.len, p.payload, p.crc}}; // pack stream = {stream, q}; end

set membership

Extended procedural statements

pattern matching on selection statements for use with tagged unions enhanced loop statements plus the foreach statement C like jump statements: return, break, continue final blocks that executes at the end of simulation (inverse of initial) extended event control and sequence events

Enhanced process control

Extensions to always blocks to include synthesis consistent simulation semantics Extensions to forkjoin to model pipelines and for enhanced process control Fine-grain process control

Enhanced tasks and functions

C like void functions pass by reference default arguments pass by name optional arguments import/export functions for DPI (Direct Programming Interface)

Classes: Object-Oriented mechanism that provides abstraction, encapsulation, and safe pointer capabilities Automated testbench support with random constraints Interprocess communication synchronization

semaphores mailboxes event extensions, event variables, and event sequencing

Clarification and extension of the scheduling semantics Cycle-Based Functionality: Clocking blocks and cycle-based attributes that help reduce development, ease maintainability, and promote reusability:

cycle-based signal drives and samples synchronous samples race-free program context

Assertions Extended hierarchy support Interfaces to encapsulate communication Functional coverage

Scheduling semantics

A time slot is divided into a set of ordered regions:

Preponed Pre-active Active Inactive Pre-NBA NBA Post-NBA Observed

- Reactive - Postponed

The purpose of dividing a time slot into these ordered regions is to provide predictable interactions between the design and testbench code. This allows properties and checkers to sample data when the design under test is in a stable state

Data Type

Integer data type

Shortint : 2-state SystemVerilog data type, 16 bit signed integer Int : 2-state SystemVerilog data type, 32 bit signed integer Longint : 2-state SystemVerilog data type, 64 bit signed integer byte :2-state SystemVerilog data type, 8 bit signed integer or ASCII character bit :2-state SystemVerilog data type, user-defined vector size logic: 4-state SystemVerilog data type, user-defined vector size reg :4-state Verilog-2001 data type, user-defined vector size integer: 4-state Verilog-2001 data type, 32 bit signed integer time :4-state Verilog-2001 data type, 64-bit unsigned integer

Signed and unsigned data types

Bit signed [7:0] si_h; Bit unsigned [7:0] unsi_h; Byte by_h; si_h='hff; unsi_h ='hff ; by_h='hff (*_h=='hff) all will return TRUE (*_h==-1) unsi_h will return FALSE,rest two will return TRUE

Void data type:

Non existant data Can be assigned as a return type of function The chandle data type represents storage for pointers passed using the DPI Direct Programming Interface The size of this type is platform dependent, but shall be at least large enough to hold a pointer on the machine in which the tool is running.

chandle data type

class

String data type

Variable size Dynamically allocated array of bytes Provides special method to work on strings

Len, putc,getc, Toupper, tolower,compare atoi(), atohex(), atooct(), atobin()

Event Data Type

SystemVerilog events provide a handle to a synchronization object an event variable can be assigned another event variable or the special value null When assigned another event variable, both event variables refer to the same synchronization object. When assigned null, the association between the synchronization object and the event variable is broken

event done; // declare a new event called done event done_too = done; // declare done_too as alias to done event empty = null; // event variable with no synchronization object

Structures and unions

struct { bit [7:0] opcode; bit [23:0] addr; }IR; typedef struct { bit [7:0] opcode; bit [23:0] addr; } instruction; // named structure type instruction IR; // define variable

Arrays

An array is a collection of variables, all of the same type, and accessed using the same name plus one or more indices

Packed and unpacked arrays

Packed array: represented as continuous set of bits Unpacked array:may or may not be represented as coontinuous set of bits Packed array:bit [7:0] c; Unpacked array: bit c [7:0],bit c [8]

Multidiomensional array

Reg [7:0][9:0] a [8];

Then a [i] [j] [k]

Dynamic arays

A dynamic array is one dimension of an unpacked array whose size can be set or changed at runtime. The space for a dynamic array doesnt exist until the array is explicitly created at runtime. data_type array_name []; Functions

new(),delete(),,size()

Associative arrays

Dynamic arrays are useful for dealing with contiguous collections of variables whose number changes dynamically. When the size of the collection is unknown or the data space is sparse, an associative array is a better option. Associative arrays do not have any storage allocated until it is used the index expression is not restricted to integral expressions, but can be of any type.

Associative array methods

num(),delete(index), exists(string) first(index), last(index),next(index),prev(index)

QUEUE

int q[$] Queue ie generally first in first out, but there are methods to insert and delete entries with index Size(), insert(),delete() push_back(),push_front() pop_back(),pop_front()

Assignment

Make the asynchronous tb using QUEUEs,Dynamic Arrays.

CLASS

SystemVerilog introduces an object-oriented class data abstraction Classes allow objects to be dynamically created, deleted, assigned, and accessed via object handles Object handles provide a safe pointer-like mechanism to the language. Classes offer inheritance and abstract type modeling

class Packet ;//data or class properties bit [3:0] command; bit [40:0] address; bit [4:0] master_id; integer time_requested; integer time_issued; integer status; // initialization function new(); command = IDLE; address = 41b0; master_id = 5bx; endfunction task clean(); command = 0; address = 0; master_id = 5bx; endtask

Objects (class instance)

Packet p; // declare a variable of class Packet p = new; // initialize variable to a new allocated object of the class Packet Calling tasks

p.current_status();

Simple Class
class basicframe; class basicframe; logic [3:0] addr; logic [3:0] addr; logic [7:0] data; logic [7:0] data; // explicit constructor // explicit constructor function new(input logic [3:0] function new(input logic [3:0] pa); pa); addr = pa; addr = pa; data = $urandom; data = $urandom; endfunction endfunction function void print(); function void print(); $display("%h %h",addr,data); $display("%h %h",addr,data); endfunction endfunction endclass endclass
Class Full

declaration

Properties/Methods

access to all members Object variable (handle) defined of a specific class type Class instance created with constructor Explicit or implicit method new

basicframe one = basicframe one = new(.pt(3)); new(.pt(3)); basicframe two; basicframe two; initial begin initial begin two = new(.pt(address)); two = new(.pt(address)); one.addr = 4; one.addr = 4; one.print(); // 4 75 one.print(); // 4 75 ... ...

Inheritance
class parent; class parent; logic [3:0] avec; logic [3:0] avec; logic abit; logic abit; function void print(); function void print(); $display("%d %d", avec, abit); $display("%d %d", avec, abit); endfunction endfunction endclass endclass class child extends parent; class child extends parent; int avec; int avec; byte abyte; byte abyte; function void print(); function void print(); $display("%0d %b %h", avec, abit, abyte); $display("%0d %b %h", avec, abit, abyte); endfunction endfunction endclass endclass
A

class declaration can extend an existing class. Inheritance Subclass inherits all members of parent. Can over-ride parent's members Parent members are accessed as if they were members of the subclass.

child one = new(); child one = new(); initial begin initial begin one.avec = 0; one.avec = 0; one.abit = 1'b1; one.abit = 1'b1; one.abyte = 8'hff; one.abyte = 8'hff; one.print(); // 0 1 ff one.print(); // 0 1 ff ... ...

Inheritance and Constructors

class parent; class parent; logic p1; logic p1; function new(input logic a1); function new(input logic a1); p1 = a1; p1 = a1; endfunction endfunction endclass endclass class child extends parent; class child extends parent; logic c1; logic c1; function new(input logic a1, a2); function new(input logic a1, a2); super.new(a1); super.new(a1); c1 = a2; c1 = a2; endfunction endfunction function void print(); function void print(); $display("%b %b", p1, c1); $display("%b %b", p1, c1); endfunction endfunction endclass endclass
Parent

constructor is implicitly called as first line of subclass constructor. Parent constructor must be explicitly called to pass arguments. Must be the first line of subclass constructor Prefix super allows a subclass to access parent members . Otherwise hidden by subclass members

child one = new(1'b0, 1'b0); child one = new(1'b0, 1'b0); initial begin initial begin one.b1 = 1'b1; one.b1 = 1'b1; one.print(); // 1 0 one.print(); // 1 0 ... ...

Assignment, renaming, copying

Packet p1;

p1 = new;
P1

Packet p2;
P2

p2 = p1;
P1

P1

Shallow copy Packet p1; Packet p2; p1 = new; p2 = new p1;

Deep copy Packet p1 = new; Packet p2 = new; p2.copy(p1);

Overridden members

class Packet; integer i = 1; function integer get(); get = i; endfunction endclass

class LinkedPacket extends Packet; integer i = 2; function integer get(); get = -i; endfunction endclass

To call the overridden method via a parent class object (p in the

example), the method needs to be declared virtual

Virtual Method

virtual class BasePacket; virtual function integer send(bit[31:0] data); endfunction endclass

class EtherPacket extends BasePacket; function integer send(bit[31:0] data); // body of the function endfunction endclass

Virtual class can not be instantiated All the methods of abstract class should be overriden Useful subclasses can be derived Virtual methods can be overdriven

polymorphism allows the use of a variable in the superclass to hold subclass objects, It allows reference the methods of those subclasses directly from the superclass variable

Polymophism:DynamicMethodLookup

BasePacket packets[100]; EtherPacket ep = new;// extends BasePacket TokenPacket tp = new;// extends BasePacket GPSSPacket gp = new;// extends BasePacket packets[0] = ep; packets[1] = tp;

packets[1].send(); It shall invoke the send method associated with the TokenPacket class

Interface

interface simple_bus; logic req, gnt; logic [7:0] addr, data; logic [1:0] mode; logic start, rdy; endinterface: simple_bus

module memMod(simple_b us a, input bit clk); logic avail; always @(posedge clk) a.gnt <= a.req & avail; endmodule

module top; logic clk = 0; simple_bus sb_intf(); memMod mem (sb_intf, clk); cpuMod cpu (.b(sb_intf), .clk(clk)); endmodule

module cpuMod(simple_bu s b, input bit clk); ... endmodule

interface i2; wire a, b, c, d; modport master (input a, b, output c, d); modport slave (output a, b, input c, d); endinterface

Program Block

The program block serves three basic purposes:

It provides an entry point to the execution of testbenches. It creates a scope that encapsulates programwide data. It provides a syntactic context that specifies scheduling in the Reactive region.

module test(...) int shared; program p1; ...; endprogram program p2; ...; endprogram endmodule

A program block can contain one or more initial blocks. It cannot contain always blocks, UDPs, modules,interfaces, or other programs. Type and data declarations within the program are local to the program scope and have static lifetime. Program variables can only be assigned using blocking assignments. Non-program variables can only be assigned using nonblocking assignments. References to program variables from outside any pro-gram block shall be an error.

Eliminating race conditions

Program block helps to avoid DUT/TB race conditions as they are supposed to execute in reactive region

Queue qData storage array [$]

Variable size array with automatic sizing Searching, sorting and insertion methods

Mailbox q Fifo with flow control

passes data between two processes put() stimgen calls put() to pass data to bfm get() bfm calls get() to retrieve data from stimgen

stimgen

bfm

put()

mailbox

get()

Mailbox

mailbox mbx; mailbox mbx; mbx = new(); mbx = new();

// allocate mailbox // allocate mailbox mbx.put(data); // Put data object into mailbox mbx.put(data); // Put data object into mailbox mbx.get(data); // data will be updated with data from FIFO mbx.get(data); // data will be updated with data from FIFO success = mbx.try_get(ref data); // Non-blocking version success = mbx.try_get(ref data); // Non-blocking version mbx.peek(data); // Look but dont remove mbx.peek(data); // Look but dont remove count = mbx.num(); // Number of elements in mailbox count = mbx.num(); // Number of elements in mailbox

Fork/join
Fork/join

Initial Begin
fork

Clk =0; #5 Fork #5 a = 0; #10 b = 0; Join Clk= 1; end

Clk becomes 1 at t=15

join

Fork/join
Fork/join_any

Initial Begin
fork

Clk =0; #5 Fork #5 a = 0; #10 b = 0; Join_any Clk= 1; end

Clk becomes 1 at t=10

Join_any

Fork/join
Fork/join_none

Initial Begin
fork

Clk =0; #5 Fork #5 a = 0; #10 b = 0; Join_none

Clk becomes 1 at t=5

Join_none

Clk= 1; end

Semaphore qUsed for Synchronization

Variable number of keys can be put and removed controlled access to a shared object think of two people wanting to drive the same car the key is a semaphore

Constraint qControl randomization

Values for random variable can be controlled through constraint expressions These are declared within constraint block

Class packet ; Class packet ; rand logic [7:0] src; rand logic [7:0] src; rand logic [7:0] dest; rand logic [7:0] dest; Constraint my_constraints { Constraint my_constraints { src[1:0] == 2b00; // constraint expression src[1:0] == 2b00; // constraint expression // always set src[1:0] to 0 // always set src[1:0] to 0 } } endclass:packet endclass:packet

Covergroup qCaptures results from a random simulation

bins qEncapsulates the coverage transitions specification

Covergroup Covergroup coverpoint coverpoint

check @(posedge top.valid ); check @(posedge top.valid ); global; global;

coverpoint top.test; coverpoint top.test; endgroup:check endgroup:check check chk = new(); check chk = new();

Program Block
q Benefits: Encapsulates the testbench Separates the testbench from the DUT Provides an entry point for execution Creates a scope to encapsulate program-wide data q Functionality: Can be instantiated in any hierarchical location Typically at the top level Ports can be connected in the same manner as any other module

Program Block q The testbench (program) runs separately from design (module)
Triggered by clock Samples just before clock edge, drives just after clock

clock Design Testbench

Sampl e inputs

Drive output s

Interface qbundling of port signals

provide an abstract encapsulation of communication between blocks Directional information (modports) Timing (clocking blocks) Functionality (routines,assertions)

device1

interface

device2

Interface Interface:An example

Interface bus_a (input clock); Interface bus_a (input clock); logic [7:0] address; logic [7:0] address; logic [31:0] data ; logic [31:0] data ; bit valid ; bit valid ; bit rd_wr ; bit rd_wr ; Endinterface: bus_a Endinterface: bus_a

Clocking Block qSpecify synchronization characteristics of the design qOffer a clean way to drive and sample signals qFeatures
Clock specification Input skew,output skew Cycle delay (##)

Clocking Block qCan be declared inside interface,module or program

Clocking Block
Module M1(ck, enin, din, enout, dout); Module M1(ck, enin, din, enout, dout); input ck,enin; input ck,enin; input [31:0] din ; input [31:0] din ; output enout ; output enout ; output [31:0] dout output [31:0] dout ; ; clocking sd @(posedge ck); clocking sd @(posedge ck); input #2ns ein,din ; input #2ns ein,din ; output #3ns enout, dout; output #3ns enout, dout; endclocking:sd endclocking:sd reg [7:0] sab ; reg [7:0] sab ; initial begin initial begin sab = sd.din[7:0]; sab = sd.din[7:0]; end end endmodule:M1 endmodule:M1
Signals will be driven 3ns after posedge ck

Signals will be sampled 2ns before posedge ck

Modports qAn interface can have multiple Master/Slave, viewpointsTransmitter/Receiver qThese can be specified using modports
Interface bus_b (input clock); Interface bus_b (input clock); logic [7:0] addr,data; logic [7:0] addr,data; logic [1:0] mode logic [1:0] mode bit ready bit ready modport master (input modport master (input ; ; ; ;
All signal names in a modport must be declared in the interface

ready,output addr,data,mode) ; ready,output addr,data,mode) ; modport slave (input addr,data,mode,output ready) ; modport slave (input addr,data,mode,output ready) ; endinterface: bus_b endinterface: bus_b

Conclusio n
q Some of SystemVerilog Testbench constructs were discussed
qBut still a long way to go..

Thank you

References
Websources:

1.

www.systemverilog.org

2. www.asic-world.com/systemverilog/index.html 3. http://svug.org/
Books :

1. Writing Testbenches using SystemVerilog - Janick Bergeron 2. Verification Methodology Manual - Janick Bergeron 3. SystemVerilog For Verification - Chris Spear

Test Cases Test Bench

ENV

SCOREBOARD SEQUENCER

DRIVER

MONITOR

Interface MEMORY DUT Assertions

Assignment

Designing TB using Program Block