Spring 2008 J Grover

Switching & Logic

Name______________________________________ please print

Examination 3 Sequential Logic Technologies

You must use the symbols given on the exam paper. Changing symbols will significantly reduce your score. This examination is closed book and closed notes.
Answer the first fifteen questions for two points each by transfer the best answers to Table 1. 1. 6. 11. 2. 7. 12. 3. 8. HW 10-1 4. 9. HW 10-2. 5. 10.

Table 1 Best answers to multiple choice questions. 1. A movement of data from right (LSB) to the left (MSB) in a ____ shift? A. Right B. Left C. Parallel D. Finite state machine 2. A VHDL design technique that connects prepackaged components using internal or buried signals. A. Structural Design B. Dataflow Design C. Behavioral Design D. Block Design 3. A serial shift register with non complemented feedback from the output of the last flip-flop to the input of the first. A. Binary Counter B. Gray Code Counter C. Johnson Counter D. Ring Counter 4. A finite state machine in which the output depends on the present state and the present input. A. Mealy machine B. Mannie machine C. Moore machine D. Vending machine 5. A finite state machine in which the output depends only on the present state. A. Mealy machine B. Mannie machine C. Moore machine D. Vending machine

6. The circuit shown above is used for what purpose? A. Counter B. Pulser C. Shift register D. Switch debounce 7. The a multiplexer is an example of what type of Boolean circuit? A. Sequential B. Combinational C. Moore machine D. Analog

Switching and Logic

Spring 2008

jeg

8. Which flip-flop act like a combination of a set-reset flip-flop and a toggle flip-flop? A. T flip-flop B. D flip-flop C. J-K flip-flop D. R-S flip-flop 9. Which flip-flop's output is a delayed image of the input? A. T flip-flop B. R-S flip-flop C. J-K flip-flop D. D flip-flop 10. Which sequential device has an output that is only dependent on the level of the inputs? A. Latch B. Multiplexer C. Flip-Flop D. Clock Tree
A B AeqB

11. The 1-bit comparator network shown above is to be implemented in VHDL. This would lead to what incorrect type of combinational encoding? A. XOR operator B. OR operator C. Implied Latch D. Buried Node 12. The edge detector on a D flip flop is placed on which input? A. D B. CLK C. Asynchronous Clear D. Detector 13. Two additional points will be added to your score if 80% or more of the 64 registered students complete the Program Outcome Assessment on the course web page. . 14. Two additional points will be added to your score if 100% or more of the 64 registered students complete the Program Outcome Assessment on the course web page. 15. I found the textbook for this course to have the following rating when compared to other textbooks I have used at the university to be ______ (All possible answers correct for this problem):

A. Excellent B. Good C. Fair with the following deficiencies ___________________________ ___________________________________________________ D. Poor with the following deficiencies ___________________________ ___________________________________________________ E. Did not buy the textbook
Report your self-graded homework score out of 100 points each in the boxes marked HW 10-1 and HW 10-2 on the previous page for the problems listed below.

HW 10-1 -- Chapter 10
1, 2 (Mealy or Moore?) 4 (Classic SM Design Through Equations) 6 (SM with No Control Inputs) 12 (SM with Control Input)

HW 10-2 -- Chapter 10
15, 16 (Switch Debounce) 18 (Unused States) 19 (VHDL for Unused States)

Switching and Logic

Spring 2008

jeg

16. State Machine Design (30 points)

Raw Score

With Bias

Part A: Derive a Moore style state diagram for a finite state machine that detects the input sequence X = 001. That is a zero followed by a zero followed by a one. The output, Z, is to be 1 at the end of the sequence and 0 otherwise. The value following the state name is the output, Z. Mark each transition arrow with the value of X. The following is an example sequence and output: X = 0 Z = 0 1 0 0 0 0 0 1 1 1 0 0 0 1 0 1 0 0 0 0 0 1 1 0 0 1 0 1 0 0 0 0 0 0 0 1 1 0 0

A/0

X=0

B/

C/

D/

E/

Part B: Translate the state diagram given below to the state table given below. The Boolean value below the state names of 0, 5 , 10, and 15 is the present output, Z. The input N stands for nickel and the input D stands for dime.

0 0

5 0

10 0
D N

N,D

15 1

Present State

Next N

State D

Present Output, Z

0 5 10 15

10
3

Switching and Logic

Spring 2008

jeg

16 Continued: Part C: Complete the following VHDL by filling in the twelve blank lines for the state table given below. Note S0 is the assumed reset state. Use proper VHDL syntax. Present State S0 S1 S2 Next Input=0 S0 S2 S0 State Input=1 S1 S0 S2

Output 00 01 10

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY FSM IS PORT( clk : IN STD_LOGIC; input : IN STD_LOGIC; reset : IN STD_LOGIC; output : OUT STD_LOGIC_VECTOR(1 downto 0)); END FSM; ARCHITECTURE behavioral OF FSM IS TYPE STATE_TYPE IS (s0, s1, s2); SIGNAL state : ________________________; BEGIN PROCESS (clk, reset) BEGIN IF reset = '1' THEN state <= ___; ELSIF (clk'EVENT AND clk = '1') THEN CASE state IS WHEN s0=> IF input = '1' THEN _________________; ELSE _________________; END IF; WHEN s1=> IF input = '1' THEN _________________;

ELSE _________________; END IF; WHEN s2=> IF input = '1' THEN _________________; ELSE _________________; END IF; END CASE; END IF; END PROCESS; PROCESS (__________) BEGIN CASE state IS WHEN s0 => _________________"; WHEN s1 => _________________; WHEN s2 => _________________; END CASE; END PROCESS; END behavioral;

Switching and Logic

Spring 2008

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17. Introduction to Sequential Logic (20 points) Part A: Complete the function table for a positive edge triggered J-K Flip-Flop

0 1

J 0 0 1 1 x x x

K Qt+1 Q't+1 Function1 0 No Change 1 0 1 x x x

Part B: For the following 3-bit counter determine the counting sequence. Assume the initial value (state) of the counter is Q0Q1Q2 = "000". Complete the table below. Hint: Determine signals in the following order, T0, Q0t+1,Q0t, T1, Q1t+1,Q1t, T2, Q2t+1,Q2t

T0 Q0

T1 Q1

T2 Q2

CLK

Q0 Q1 Q2 T0 T1 T2 Q0 0 0 0

t+1

Q1

t+1

Q2t+1

Your choices are Clear, Forbidden, Inhibited, No Change, Preset, Reset, Set and Toggle

Switching and Logic

Spring 2008

jeg

18. Counters and Shift Registers (20 Points) Part A: Sketch a 3-bit Ring Counter using three D Flip-Flops

Part B: Sketch a 3-bit Johnson Counter (Mbius Counter) using three D Flip-Flops

Part C: Complete the state table for a 3-bit Gray Code Counter2. Assume the initial state is "000". Note the solution is not unique and any valid Gray Code Counter will suffice.

Present State

Next State

0 0 0 0 0 1

Named after Frank Gray of IBM, see patent 2632058

Switching and Logic

Spring 2008

jeg

Example VHDL Statements

--Entity Example ENTITY __entity_name IS PORT( __input_name, __input_name : IN BIT; __input_vector_name : IN BIT_VECTOR(__high DOWNTO __low); __output_name, __output_name : OUT BIT); END __entity_name; --Architecture Example ARCHITECTURE a OF __entity_name IS SIGNAL __signal_name : BIT; SIGNAL __signal_name : BIT_VECTOR(__high TO __low); --Component Declaration goes here if used BEGIN -- Combinational statements END a; --Component declaration example COMPONENT __component_name PORT( ); -- same as entity END COMPONENT; --Component instance __instance_name : __component_name PORT MAP( __connect_port, __connect_port); --With-Select WITH __expression SELECT __signal <= __expression __constant_value, __expression __constant_value, __expression __constant_value, __expression OTHERS; CASE __expression IS WHEN __constant_value => __statement; __statement; WHEN __constant_value => __statement; __statement; WHEN OTHERS => __statement; __statement; END CASE; __process_label: PROCESS (__signal_name, __signal_name, __signal_name) VARIABLE __variable_name : STD_LOGIC; VARIABLE __variable_name : STD_LOGIC; BEGIN -- Signal Assignment Statement (optional) -- Variable Assignment Statement (optional) -- Procedure Call Statement (optional) -- If Statement (optional) -- Case Statement (optional) -- Loop Statement (optional) END PROCESS __process_label; __process_label: PROCESS VARIABLE __variable_name : STD_LOGIC; VARIABLE __variable_name : STD_LOGIC; BEGIN WAIT UNTIL __clk_signal = '1'; -- Signal Assignment Statement (optional) -- Variable Assignment Statement (optional) WHEN WHEN WHEN WHEN -- Procedure Call Statement (optional) -- If Statement (optional) -- Case Statement (optional) -- Loop Statement (optional) END PROCESS __process_label; IF __expression THEN __statement; __statement; ELSIF __expression THEN __statement; __statement; ELSE __statement; __statement; END IF;

Switching and Logic

Spring 2008

jeg

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