http://144.16.192.60/~isg/CAD/
Course Outline
Introduction: VLSI design flow, challenges. Verilog/VHDL: introduction and use in synthesis, modeling combinational and sequential logic, writing test benches. Logic synthesis: Two-level and multilevel gate-level optimization . Binary decision diagrams. Basic concepts of high-level synthesis: partitioning, scheduling, allocation and binding. Technology mapping. Synthesis of reversible logic circuits: Basic concepts of reversible circuits and synthesis. Exact, transformation based, and ESOP based synthesis methods. Physical design automation: Review of MOS/CMOS fabrication technology. VLSI design styles: full-custom, standard-cell, gate-array and FPGA. Physical design automation algorithms: floor-planning, placement, routing, compaction, design rule check, power and delay estimation, clock and power routing, etc. Special considerations for analog and mixed-signal designs.
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References
1. R.H. Katz, Contemporary logic design, Addison-Wesley Pub. Co., 1993. 2. M.J.S. Smith, Application-specific integrated circuits, Addison-Wesley Pub. Co., 1997. 3. S. Ramachandran, Digital VLSI systems design, Springer, 2007. 4. M.L. Bushnell and V.D. Agrawal, Essentials of Electronic Testing, Kluwer Academic Publishers, 2000. 5. J. Bhasker, Verilog VHDL synthesis: a practical primer, B S Publications, 1998. 6. D.D. Gajski, N.D. Dutt, A.C. Wu and A.Y. Yin, High-level synthesis: introduction to chip and system design, Kluwer Academic Publishers, 1992. 7. M. Sarrafzadeh and C.K. Wong, An introduction to physical design, McGraw Hill, 1996. 8. N.A. Sherwani, Algorithms for VLSI physical design automation, Kluwer Academic Publishers, 1999. 9. S.M. Sait and H. Youssef, VLSI physical design automation: theory and practice, World Scientific Pub. Co., 1999.
Design Idea Behavioral Design Flow Graph, Pseudo Code Data Path Design Bus/Register Structure Logic Design Gate/F-F Netlist Physical Design Transistor Layout Manufacturing Chip / Board
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Design Representation
A design can be represented at various levels from three different angles: 1. Behavioral 2. Structural 3. Physical Can be represented by Y-diagram.
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BEHAVIORAL DOMAIN
Programs Specifications Truth table
STRUCTURAL DOMAIN
Gates Adders Registers
PHYSICAL DOMAIN
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Behavioral Representation
Specifies how a particular design should respond to a given set of inputs. May be specified by
Boolean equations Tables of input and output values Algorithms written in standard HLL like C Algorithms written in special HDL like Verilog
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Structural Representation
Specifies how components are interconnected. In general, the description is a list of modules and their interconnects:
called netlist. can be specified at various levels.
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add4
add
add
add
add
carry
sum
carry
sum
carry
sum
carry
sum
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module add (cy_out, sum, a, b, cy_in); input a, b, cy_in; output sum, cy_out; sum s1 (sum, a, b, cy_in); carry c1 (cy_out, a, b, cy_in); endmodule module carry (cy_out, a, b, cy_in); input a, b, cy_in; output cy_out; wire t1, t2, t3; and g1 (t1, a, b); and g2 (t2, a, c); and g3 (t3, b, c); or g4 (cy_out, t1, t2, t3); endmodule
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Physical Representation
The lowest level of physical specification.
Photo-mask information required by the various processing steps in the fabrication process.
At the module level, the physical layout for the 4-bit adder may be defined by a rectangle or polygon, and a collection of ports.
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Floorplanning
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