Talus 1.

2 : The Look, Feel and Results from an Evaluation Exercise

Sharath Chandra L Ramakrishnan Varadhan Suriamoorthy Babu

Qualcomm India Pvt Ltd

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Bangalore, India | September 7, 2011

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Agenda

Introduction to Talus 1.2 Netlist and Constraints handling Placement CTS Post Route Optimization

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Design Information
Die area Technology Number of Blocks Number of components Top level stdcell count
: ~ 40mm2 : 28nm : 15 : > 50 : ~ 1.5 million

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Introduction to Talus 1.2

Talus 1.2 Looks similar to Talus 1.1 with most
steps/commands remaining same It has a new timer called Tekton It has a new router called GRX It has a new extractor QCP It supports multi corner CTS

TALUS 1.2 runs faster and gives better QOR

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Introduction to Talus 1.2

Tekton
The faster run times of Tekton is the key reason for the faster run times of Talus 1.2 MX timer is the implementation version of the Tekton Timer that comes with Talus 1.2 Tekton commands are similar to primetime commands Reads and understands PT tcl and SDC No post processing of any sort is required while reading the sdc Magma Timing commands are no longer supported (force timing ) Some config timing commands are still supported List of supported/unsupported is published

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Introduction to Talus 1.2

Traditional debug command report force timing is not supported power users of magma timing commands need to enhance their skill Scripts/Utilities written using magma timing commands need to be re
written using the new commands Some key commands which are no longer supported
data loop model_node - Need to use PT tcl to loop through the timer graph query node marks and query mark forces which were critical in debugging exceptions

A PD Engineer feels no change working on any implementation steps A PD Engineer feels like a STA engineer while analyzing timing

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Netlist and Constraints Handling

Maintain hierarchy
Design is flattened after reading the constraints Many exceptions get moved due to flattenning Difficult to load a constraint file at a later stage of the flow NOT ANYMORE : The original netlist hierarchy is remembered by the tool even after flattenning A sdc file can be loaded at any stage of the flow even if the design is flattened FYI : this was a part of later versions of talus 1.1 as well

Scenario is compulsory
No mode based timing handled by the tool

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Netlist and Constraints Handling

Build Correlation LESS -0.200 -0.180 -0.160 -0.140 -0.120 -0.100 -0.080 -0.060 -0.040 -0.020 +0.000 +0.020 +0.040 +0.060 +0.080 +0.100 +0.120 +0.140 +0.160 +0.180 +0.200 MORE Talus 1.1 Endpoints 1,158 0 1 3 6 52 27 2 2 1,910 10 718,323 989 2,300 6,628 816 15,721 462 79 39 59 76 1,892 Talus1.2 Endpoints 11 36 30 29 19 58 92 40 97 35 77 748,873 631 25 19 17 3 0 0 0 0 0 528

Constraints Correlation
Correlation AVERAGE STANDARD_DEV LOWEST HIGHEST LESSTHAN MORETHAN INF_PTSI INF_PNR TOTAL_SKIPPED Stats 0.008 0.258 -13.232 12.787 1158 1892 185 525 0 Stats 0.003 0.107 -19.162 4.091 11 528 25 54 0

All Endpoint Correlation Negative values indicate Talus

tool is pessimistic Zero Wire Load Correlation looks much better than talus 1.1

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Netlist and Constraints handling

Clock sense handling
set_clock_sense stop_propagation clock_phase < > Clock Data n1 n2

In talus 1.2 the clock does stop where the designer intends it to stop

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FixCell
GRX global router is the default GRX is a multilevel global router Scalable
The runtime benefit scales with the number of CPUs
This advantage is more in case of larger designs

Congestion / DRC
Generally better than HGR

Timing
Generally better than HGR

Auto scan abstract facility eliminates the dependency

on the library preparation

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FixCell
METRIC FEPs WNS (ns) Standard Cell Area (mm2) Cell Leakage (mW) Run Time (hours) Peak memory (GB) Talus 1.1 1218 -2 3.037 1.3270 50 42 Talus 1.2 133 -1.2 2.987 1.0861 36 42
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FixClock
setup Skew Group CLK_1 CLK_2 CLK_3 CLK_4 CLK_5 CLK_6 CLK_7 CLK_8 CLK_9 No. of Sinks 43977 14664 10959 7094 6930 5000 3920 3648 3470 Gskew MaxID MinID 275 367 254 272 163 204 200 189 175 3143 2797 3153 5830 5739 2868 2430 2899 5558 5576 hold Gskew MaxID MinID 229 214 204 369 237 261 96 92 121 1182 1089 953 875

1225 1020 2249 1880 2116 1880 4525 4264 1407 1311 818 726

11501 11297 1834 2281 5438 1633 2091 5263

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All delay numbers in ps

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Post Route Optimization

Four Scenarios fixwire_opt_final optimized with WNS func_pvt1_setup func_pvt2_setup func_pvt3_hold func_pvt4_hold test_pvt1_setup test_pvt2_setup test_pvt3_hold test_pvt4_hold runtime, hours peak memory, MB space/short -59.38 -57.96 -44.88 -52.46 -13.10 -9.85 -20.89 -22.53 88 126329 192/178 TNS -13021 -11477 -10586 -14348 -592 -455 -737 -790 FEP 10258 4167 14144 11812 220 118 1805 1428 optimized with WNS -59.50 -58.28 -44.88 -52.48 -12.80 -9.63 -20.92 -22.60 114 157692 199/126 TNS -12024 -11421 -10671 -14481 -556 -456 -756 -803 FEP 6270 3028 12182 9350 141 121 1895 1487 Eight Scenarios

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Data porting -1.1 to 1.2

From Talus 1.1
Dump constraint information for each mode Dump a constraints which is mode independent Delete all the timing information including corners and export a volcano
foreach corner [get_corners] { data delete corner $corner } clear timing all $m query timing mode $m -all export volcano <des>.fixclock_final.no_timing.volcano -object /work

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Data porting - 1.1 to 1.2

In Talus 1.2
Load the volcano setup corners and scenarios set v1.2 configs for xtalk etc. Read the two mode sdcs and then the mode independent sdc Set wire_model to constant
force wire model constant $m recur

update_timing full report_timing -summary

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Acknowledgements
Suresh A Srini Rangan Dan Taylor Joey Dacanay Shibashish Patel Shabeer Ibrahim Deepika Parimal Das TCS Reddy
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Pradeep B Deepti Kumar

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Thank You

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