Gemini Circuit Reference for POP-21408-001 B

Confidential
Originator: Jason Bridger Document #: Date Created: Mar. 16, 2009 Last Revised By: Jason Bridger Department: MFG Training Revision #: 1.0.1 Approvals: Last Date Revised: Mar. 19, 2009

POP-21408-001 B Gemini with WLAN

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Confidential
Originator: Jason Bridger Document #: Date Created: Mar. 16, 2009 Last Revised By: Jason Bridger Department: MFG Training Revision #: 1.0.1 Approvals: Last Date Revised: Mar. 19, 2009

1.0

Revisions
Rev: 1.0.0 1.0.1 Date: Mar. 16, 2009 Mar. 19, 2009 Name: Jason Bridger Jason Bridger

Description: Initial Draft Release to Production Second Draft Updated graphics to correctly reflect POP-21408-001 B Completed WLAN section information

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Originator: Jason Bridger Document #: Date Created: Mar. 16, 2009 Last Revised By: Jason Bridger Department: MFG Training Revision #: 1.0.1 Approvals: Last Date Revised: Mar. 19, 2009

2.0

Table of Contents

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Originator: Jason Bridger Document #: Date Created: Mar. 16, 2009 Last Revised By: Jason Bridger Department: MFG Training Revision #: 1.0.1 Approvals: Last Date Revised: Mar. 19, 2009

3.0
3.1

Gemini Overview
Specifications

3.2

Features

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Originator: Jason Bridger Document #: Date Created: Mar. 16, 2009 Last Revised By: Jason Bridger Department: MFG Training Revision #: 1.0.1 Approvals: Last Date Revised: Mar. 19, 2009

4.0
4.1.0

Quad Band GSM/EDGE Radio

GSM/EDGE Antenna and Front End Module (PA) Schematic (See Page 2, SCH-21408-001_revB.pdf)

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4.1.1
Originator: Jason Bridger Document #: Date Created: Mar. 16, 2009 Last Revised By: Jason Bridger Department: MFG Training Revision #: 1.0.1 Approvals: Last Date Revised: Mar. 19, 2009

GSM/EDGE Antenna and Front End Module Placement Diagram, SH401 (See Page 2, POP-21408-001_revB.pdf)

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4.1.2
Originator: Jason Bridger Document #: Date Created: Mar. 16, 2009 Last Revised By: Jason Bridger Department: MFG Training Revision #: 1.0.1 Approvals: Last Date Revised: Mar. 19, 2009

GSM/EDGE Antenna and Front End Module (PA) Information and Reference

RF Signal Lines: Line Designation

Description Signal on S201 (RF Spring Contact) side of SW201 (GSM BLT RF Interface) GSM_RF_CONN_IN C233 (DNP) Good location to check the signal leaving SW201 Signal on U201 (GSM Front End) side of SW201 (GSM BLT RF Interface) GSM_RF_CONN_OUT C211 (DNP) Good location to check the signal leaving U201 CAUTION! RF Coaxial Connectors (SW201) and RF Spring Contacts (S201) are Easily Damaged, Do Not Probe These Contacts! High Band (DCS1800/PCS1900) signal from U402 (GSM Transceiver) to U201 (GSM Front End) HB_OUT / GSM_TX_HB_IN C224 dBm varies based on Power Control Level (PCL) required Low Band (GSM850/GSM900) signal from U402 (GSM Transceiver) to U201 (GSM Front End) LB_OUT / GSM_TX_LB_IN C220 dBm varies based on Power Control Level (PCL) required No Access RX850, RX900, RX1800, RX1900 RX signals from U201 (GSM Front End) to FL401 (GSM SAW Filter Bank) Voltage Supplies: Line Designation VBAT GSM_PA_VBATT2 GSM_PA_VBATT3 GSM_PA_VBATT4 GSM_PA_VBATT5 V2_7RF_A

Reference

Reference C235 C234 C204 C202 C243 R415

Description 3.8V (Approx.), Voltage supplied directly from battery 3.8V (Approx.), Voltage supplied directly from battery Supplies the Power Amplifier (PA) control circuitry 3.8V (Approx.), Voltage supplied directly from battery May supply the Low Band (LB) internal Power Amplifier (PA), unconfirmed 3.8V (Approx.), Voltage supplied directly from battery Supplies the High Band (HB) internal Power Amplifier (PA) 3.8V (Approx.), Voltage supplied directly from battery Supplies the Power Amplifier (PA) control circuitry 2.8V, Supplied by U401 (2.8V LDO) Supplies the Power Amplifier (PA) control circuitry

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I/O Signal Lines and Clocks: Line Designation IPC_BCM LB_HB TX_ANT_SW_EN TX_EN US_EURO VDETECT
Originator: Jason Bridger Document #: Date Created: Mar. 16, 2009 Last Revised By: Jason Bridger Department: MFG Training Revision #: 1.0.1 Approvals: Last Date Revised: Mar. 19, 2009

Reference C242 C241 C240

No Access No Access

C214

Description 0V(0) or 1.8V(1), Signal line from U402 (GSM Transceiver) to U201 (GSM Front End) Selects the radio mode, GMSK (1) or EDGE (0) 0V(0) or 1.8V(1), Signal line from U402 (GSM Transceiver) to U201 (GSM Front End) Selects High Band (HB = 1) or Low Band (LB = 0) for RX/TX functions 1.8V, Active High, Enable line from U402 (GSM Transceiver) to U201 (GSM Front End) Enables U201 (GSM Front End) to transmit 1.8V, Active High, Enable line from U402 (GSM Transceiver) to U201 (GSM Front End) Enables the Power Amplifier (PA) on U201 (GSM Front End) 0V(0) or 1.8V(1), Signal line from U402 (GSM Transceiver) to U201 (GSM Front End) Selects the US (850/1900MHz = 0) or EUROpean (900/1800MHz = 0) bands for RX functions RF power detector linear output from U201 (GSM Front End) to U402 (GSM Transceiver) 1.25V @ 10dBm (RF output power), 2.0V @ 30dBm (RF output power), 40mV/dBm slope Power Amplifier (PA) control voltage from U402 (GSM Transceiver) to U201 (GSM Front End) Controls output power for GMSK modulated signals: EGSM (850MHz & 900MHz): VRAMP range is 0.1V to 2.1V, -10dBm POUT 33.0dBm POUT range is 5dBm POUT 33.0dBm, 25dB/V relationship DCS/PCS (1800MHz & 1900MHz): VRAMP range is 0.1V to 2.1V, -10dBm POUT 32.0dBm POUT range 0dBm POUT 32.0dBm, 25dB/V relationship Sets bias conditions for EDGE modulated signals: EGSM (850MHz & 900MHz): VRAMP range is 1.8V to 2.1V POUT is fixed at 27.0dBm, Error Vector Magnitude (EVM) is 5% DCS/PCS (1800MHz & 1900MHz): VRAMP range is 1.8V to 2.1V POUT is fixed at 26.0dBm, Error Vector Magnitude (EVM) is 5%

VRAMP

C213

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Key Components: Reference RIM Part Number FL401 U201 U401 U402 FIL-00231-001 ANA-00515-001 ANA-00641-001 ANA-00485-002 (No Datasheet on Matrix)
Originator: Jason Bridger Document #: Date Created: Mar. 16, 2009 Last Revised By: Jason Bridger Department: MFG Training Revision #: 1.0.1 Approvals: Last Date Revised: Mar. 19, 2009

Description 850 / 900 / 1800 / 1900 MHz SAW Filter Bank for Receiver Skyworks GSM/GPRS/EDGE Power Amplifier Front End Module 2.8V Ultra Low Noise, Dual 200mA Linear Regulator (LDO) Freescale GSM / GPRS / EDGE Transceiver

Notes and Applications:

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4.2.0
Originator: Jason Bridger Document #: Date Created: Mar. 16, 2009 Last Revised By: Jason Bridger Department: MFG Training Revision #: 1.0.1 Approvals: Last Date Revised: Mar. 19, 2009

GSM/EDGE Transceiver Schematic (See Page 4, SCH-21408-001_revB.pdf)

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Confidential
Originator: Jason Bridger Document #: Date Created: Mar. 16, 2009 Last Revised By: Jason Bridger Department: MFG Training Revision #: 1.0.1 Approvals: Last Date Revised: Mar. 19, 2009

4.2.1

GSM/EDGE Transceiver Placement Diagram, SH401 (See Page 2, POP-21408-001_revB.pdf)

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4.2.2
Originator: Jason Bridger Document #: Date Created: Mar. 16, 2009 Last Revised By: Jason Bridger Department: MFG Training Revision #: 1.0.1 Approvals: Last Date Revised: Mar. 19, 2009

GSM/EDGE Transceiver Information and Reference

RF Signal Lines: Line Designation RX850, RX900, RX1800, RX1900 GSM_RF_..._P, GSM_RF_..._N HB_OUT LB_OUT Voltage Supplies: Line Designation V1_8DIG V1_8DIG V1_8DIG V1_8DIG V2_7TCXO V2_7RF_A VSYS VSYS

Reference
No Access No Access

Description RX signals from U201 (GSM Front End) to FL401 (GSM SAW Filter Bank) Differential RX signals from FL401 (GSM SAW Filter Bank) to U402 (GSM Transceiver) High Band (DCS1800/PCS1900) signal from U402 (GSM Transceiver) to U201 (GSM Front End) dBm varies based on Power Control Level (PCL) required Low Band (GSM850/GSM900) signal from U402 (GSM Transceiver) to U201 (GSM Front End) dBm varies based on Power Control Level (PCL) required

C224
(Near U201)

C220
(Near U201)

Reference
SM0 Bus

Description 1.8V Main SM0 Supply Bus from U901 (Power Management) 1.8V, Supplies RF_ON_ENABLE signal line 1.8V, Supplies U402 (GSM Transceiver) digital I/O and digital RF processing sections 1.8V, Supplies U406 (Buffer) 2.8V, Supplied by U401 (2.8V LDO) Supplies the 52MHz TCXO 2.8V, Supplied by U401 (2.8V LDO) Supplies the 52MHz TCXO and U201 (GSM Front End) 2.85V Main SM2 Supply Bus from U901 (Power Management) 2.85V, Supplies U401 (2.8V LDO)

R411 C404 C428 C423 C402

SM2 Bus

C401

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I/O Signal Lines and Clocks: Line Designation AUX_CLK BT_CLK BT_CLK_REQ CLK_ON CNTRLCLK CNTRLDATA CNTRLEN DBG_DATA DEBUG_DATA IPC_BCM LB_HB MARS_EXTAL MARS_INT RESETB RF_ON RF_ON_ENABLE RXTXDATA RXTXEN STROBE SYSCLK
Originator: Jason Bridger Document #: Date Created: Mar. 16, 2009 Last Revised By: Jason Bridger Department: MFG Training Revision #: 1.0.1 Approvals: Last Date Revised: Mar. 19, 2009

Reference
No Access N/A N/A

Description Line Not Used Line Not Used Line Not Used 1.8V, Enable line from U601 (BB Processor) Enables the 26MHz system clock 1.8V, Synchronization clock for control lines 1.8V, Serial data line from U601 (BB Processor) to U402 (GSM Transceiver) 1.8V, Enable line from U601 (BB Processor) Enables the I/O control lines on U402 (GSM Transceiver) 1.8V, Data read control line from U402 (GSM Transceiver) to U601 (BB Processor) 1.8V, RX data line from U402 (GSM Transceiver) to U601 (BB Processor) 0V(0) or 1.8V(1), Signal line from U402 (GSM Transceiver) to U201 (GSM Front End) Selects the radio mode, GMSK (1) or EDGE (0) 0V(0) or 1.8V(1), Signal line from U402 (GSM Transceiver) to U201 (GSM Front End) Selects High Band (HB = 1) or Low Band (LB = 0) for RX/TX functions Line Not Used 0V(0) or 1.8V(1), Active Low, Reset signal from U601 (BB Processor) Resets U402 (GSM Transceiver) Line Not Used 1.8V, Active High, Enable line for U401 (2.8V LDO), pin A2 (V2_7RF_OUT) Permanently tied high by V1_8DIG via R411 1.8V, TX data line from U601 (BB Processor) to U402 (GSM Transceiver) 1.8V, Bidirectional communications line between U601 (BB Processor) and U402 (GSM Transceiver) for RX and TX enabling. 1.8V, Data framing signal for TX and RX data transactions 26MHz, System clock reference to U601 (BB Processor) Timing reference for transmit and receive operations between U601 (BB Processor) and U402 (GSM Transceiver)
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R409
(SH1001)

TP410 TP409 TP411 TP413

(SH1001)

TP401 C242 C241

N/A

TP403 TP405
N/A

R411 TP406 TP407 TP402 R419

Gemini Circuit Reference for POP-21408-001 B

Confidential
Originator: Jason Bridger Document #: Date Created: Mar. 16, 2009 Last Revised By: Jason Bridger Department: MFG Training Revision #: 1.0.1 Approvals: Last Date Revised: Mar. 19, 2009

I/O Signal Lines and Clocks Continued: Line Designation TCXO_52MHZ / MARS_XTAL TX_EN TX_ANT_SW_EN USB_CLK / MARS_SYS_CLK US_EURO V2_7_TCXO_EN VDETECT

Reference C426
No Access

Description 52MHz, Clock signal from X401 (52MHz TCXO) to U402 (GSM Transceiver) 1.8V, Active High, Enable line from U402 (GSM Transceiver) to U201 (GSM Front End) Enables the Power Amplifier (PA) 1.8V, Active High, Enable line from U402 (GSM Transceiver) to U201 (GSM Front End) Enables U201 (GSM Front End) to transmit 26MHz, System clock reference for U1404 (USB Transceiver), gated by U1405 (AND Gate) 0V(0) or 1.8V(1), Signal line from U402 (GSM Transceiver) to U201 (GSM Front End) Selects the US (850/1900MHz = 0) or EUROpean (900/1800MHz = 0) bands for RX functions 1.8V, Active High, Enable line from U402 (GSM Transceiver) to U401 (2.8V LDO) Enables the output at pin C2 (V2_7TCXO) on U401 (2.8V LDO) Linear output from U201 (GSM Front End) RF power detector to U402 (GSM Transceiver) 1.25V @ 10dBm (RF output power), 2.0V @ 30dBm (RF output power), 40mV/dBm slope Power Amplifier (PA) control voltage from U402 (GSM Transceiver) to U201 (GSM Front End) Controls output power for GMSK modulated signals: EGSM (850MHz & 900MHz): VRAMP range is 0.1V to 2.1V, -10dBm POUT 33.0dBm POUT range is 5dBm POUT 33.0dBm, 25dB/V relationship DCS/PCS (1800MHz & 1900MHz): VRAMP range is 0.1V to 2.1V, -10dBm POUT 32.0dBm POUT range 0dBm POUT 32.0dBm, 25dB/V relationship Sets bias conditions for EDGE modulated signals: EGSM (850MHz & 900MHz): VRAMP range is 1.8V to 2.1V POUT is fixed at 27.0dBm, Error Vector Magnitude (EVM) is 5% DCS/PCS (1800MHz & 1900MHz): VRAMP range is 1.8V to 2.1V POUT is fixed at 26.0dBm, Error Vector Magnitude (EVM) is 5%

C240
(Near U201)

R420
No Access No Access

C214

VRAMP

C213

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Key Components: Reference RIM Part Number FL401 U201 U401 U402 U406 U601 U901 U1404 U1405 X401 FIL-00231-001 ANA-00515-001 ANA-00641-001 ANA-00485-002 (No Datasheet on Matrix) DIG-00151-001 DIG-00179-004 ANA-00614-006 ANA-00533-002 DIG-00213-001 XTL-00035-001
Originator: Jason Bridger Document #: Date Created: Mar. 16, 2009 Last Revised By: Jason Bridger Department: MFG Training Revision #: 1.0.1 Approvals: Last Date Revised: Mar. 19, 2009

Description 850 / 900 / 1800 / 1900 MHz SAW Filter Bank for Receiver Skyworks GSM/GPRS/EDGE Power Amplifier Front End Module 2.8V Ultra Low Noise, Dual 200mA Linear Regulator (LDO) Freescale GSM / GPRS / EDGE Transceiver Dual Buffer Baseband Processor (Argon LV) BQ Huge Power Management IC USB / Mass Storage Controller Dual AND Gate 52.000000MHz Voltage Controlled Crystal Oscillator

Notes and Applications:

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4.3.0
Originator: Jason Bridger Document #: Date Created: Mar. 16, 2009 Last Revised By: Jason Bridger Department: MFG Training Revision #: 1.0.1 Approvals: Last Date Revised: Mar. 19, 2009

GSM/EDGE 52MHz TCXO Schematic (See Page 4, SCH-21408-001_revB.pdf and SCH-21407-001_revB.pdf)

4.3.1

GSM/EDGE Temperature Sensor Schematic (See Page 4, SCH-21408-001_revB.pdf and SCH-21407-001_revB.pdf)

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4.3.2
Originator: Jason Bridger Document #: Date Created: Mar. 16, 2009 Last Revised By: Jason Bridger Department: MFG Training Revision #: 1.0.1 Approvals: Last Date Revised: Mar. 19, 2009

GSM/EDGE 52MHz TCXO Placement Diagram (See Page 2, POP-21408-001_revB.pdf and POP-21407-001_revB.pdf)

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4.3.3
Originator: Jason Bridger Document #: Date Created: Mar. 16, 2009 Last Revised By: Jason Bridger Department: MFG Training Revision #: 1.0.1 Approvals: Last Date Revised: Mar. 19, 2009

GSM/EDGE 52MHz TCXO Information and Reference

Voltage Supplies: Line Designation V1_8DIG V1_8DIG V2_7RF_A V2_7TCXO / TCXO_DAC_VDD V2_7TCXO / VCC_TCXO_52MHZ I/O Signal Lines and Clocks: Line Designation AFC_DAC_FRM EDGE_CTL_AFC_CTL_CLK EDGE_CTL_AFC_DO TCXO_DAC_OUT/TCXO_52MHZ_VCON TCXO_TEMP

Reference
SM0 Bus

Description 1.8V Main SM0 Supply Bus from U901 (Power Management) 1.8V, Supplies U403 (52MHz TCXO DAC) digital I/O 2.8V, Supplied by U401 (2.8V LDO) Supplies the bias voltage for RT401 (Thermistor) 2.8V, Supplied by U401 (2.8V LDO) Supplies VDD and positive voltage reference for U403 (52MHz TCXO DAC) 2.8V, Supplied by U401 (2.8V LDO) Supplies X401 (52MHz Crystal)

C417 R407 R405 C415

Reference TP408 TP410 TP409 R404 C419

Description 1.8V, Active Low, Signal from U601 (BB Processor) to U403 (52MHz TCXO DAC) Signals the beginning of a serial data frame for U403 (52MHz TCXO DAC) 1.8V, Control line synchronization clock from U601 (BB Processor) Note: Also known as CNTRLCLK 1.8V, Serial data input from U601 (BB Processor) to U403 (52MHz TCXO DAC) Note: Also known as CNTRLDATA Control line from U403 (52MHz TCXO DAC) to X401 (52MHz Crystal) Provides feedback to U403 (52MHz TCXO DAC) Outputs a voltage representation of the TCXO temperature to U901 (Power Management)

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Key Components: Reference RIM Part Number RT401 U401 U403 U601 U901 X401 RES-10017-001 ANA-00641-001 ANA-00311-001 DIG-00179-004 ANA-00614-006 XTL-00035-001
Originator: Jason Bridger Document #: Date Created: Mar. 16, 2009 Last Revised By: Jason Bridger Department: MFG Training Revision #: 1.0.1 Approvals: Last Date Revised: Mar. 19, 2009

Description 47k Thermistor, part of Temperature Compensation System 2.8V Ultra Low Noise, Dual 200mA Linear Regulator (LDO) 12bit Voltage Output DAC Baseband Processor (Argon LV) BQ Huge Power Management IC 52.000000MHz Voltage Controlled Crystal Oscillator

Notes and Applications:

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Originator: Jason Bridger Document #: Date Created: Mar. 16, 2009 Last Revised By: Jason Bridger Department: MFG Training Revision #: 1.0.1 Approvals: Last Date Revised: Mar. 19, 2009

5.0
5.1.0

Bluetooth (BT) Section

Bluetooth Transceiver and Antenna Schematic (See Page 5, SCH-21408-001_revB.pdf and SCH-21407-001_revB.pdf)

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5.1.1
Originator: Jason Bridger Document #: Date Created: Mar. 16, 2009 Last Revised By: Jason Bridger Department: MFG Training Revision #: 1.0.1 Approvals: Last Date Revised: Mar. 19, 2009

Bluetooth Transceiver and Antenna Placement Diagram (See Page 2, POP-21408-001_revB.pdf and POP-21407-001_revB.pdf)

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5.1.2
Originator: Jason Bridger Document #: Date Created: Mar. 16, 2009 Last Revised By: Jason Bridger Department: MFG Training Revision #: 1.0.1 Approvals: Last Date Revised: Mar. 19, 2009

Bluetooth Information and Reference

RF Signal Lines: Line Designation

Description Signal at BT Antenna (After TP203) RF_BT C232 Note: RF_BT is the same as BT_ANT Signal from BT Antenna to FL501 (BT Filter) BT_ANT C523 Note: BT_ANT is the same as RF_BT CAUTION! RF Spring Contacts (TP203) are Easily Damaged, Do Not Probe These Contacts! BT_RF_N BT_RF_P Voltage Supplies: Line Designation 1.5VPOWERPLANE BT_VDD_CORE V1_8DIG V1_8DIG V1_8DIG / BT_VREG_IN I/O Signal Lines and Clocks: Line Designation BT_ACTIVE BT_CLK BT_CLK26M BT_CLK_REQ
No Access No Access

Reference

Differential signal from FL501 (BT Filter) to U501 (BT Transceiver) Differential signal from FL501 (BT Filter) to U501 (BT Transceiver)

Reference C509 C510

SM0 Bus

C521 (DNP) C504 (DNP)

Description 1.5V, Supply from U501 (BT Transceiver) internal 1.5V regulator to FL501 (BT Filter) Also supplies BT_VDD_CORE 1.5V, Supply from U501 (BT Transceiver) internal 1.5V regulator to U501 internal circuitry 1.8V Main SM0 Supply Bus from U901 (Power Management) 1.8V, Supplies U501 (BT Transceiver) digital I/O 1.8V, Supplies U501 (BT Transceiver) internal 1.5V regulator

Reference TP503 C522 (DNP)

N/A

R505

Description 0V(0) or 1.8V(1), Active High, Signal line from U501 (BT Transceiver) Signals U1501 (WLAN) that U501 (BT Transceiver) is actively transmitting 0.8Vp-p to 1.5Vp-p 26.0MHz clipped sine wave, Clock signal from X1501 (WLAN TCXO) Same as TCXO_26MHZ Line Not Used 0V(0) or 1.8V(1), Active High, Signal line from U501 (BT Transceiver) to U1508 (OR Gate) Signals U1508 (OR Gate) to assert a high on TCXO_VCC_EN (in WLAN Section) Enables TCXO_26MHZ / BT_CLK

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Originator: Jason Bridger Document #: Date Created: Mar. 16, 2009 Last Revised By: Jason Bridger Department: MFG Training Revision #: 1.0.1 Approvals: Last Date Revised: Mar. 19, 2009

I/O Signal Lines and Clocks: Line Designation BT_FREQ BT_LO_REF BT_PRIORITY BT_RSTB BT_SPI_CLK BT_SPI_CSB BT_SPI_MISO BT_SPI_MOSI BT_UART_CTS BT_UART_RTS BT_UART_RX BT_UART_TX BT_VREG_EN PCM_CLK PCM_IN PCM_OUT PCM_SYNC WLAN_ACTIVE TCXO_26MHZ

Reference TP515 C511 TP502 R508 TP506 TP505 TP508 TP507 TP513 TP514 R510 R509 C504 (DNP) TP509 TP511 TP510 TP512 TP504 R516

Description 0V(0) or 1.8V(1), Active High, Signal line from U501 (BT Transceiver) Bluetooth reserved channel indication Reference voltage decoupling 0V(0) or 1.8V(1), Active High, Signal line from U501 (BT Transceiver) Bluetooth priority signal 1.8V, Active Low, BT Reset Permanently tied high by V1_8DIG via R508 Line Not Used Line Not Used Line Not Used Line Not Used 1.8V, Active Low, UART clear to send line from U601 (BB Processor) 1.8V, Active Low, UART request to send line to U601 (BB Processor) 1.8V, Active High, UART RX communications data line from U601 (BB Processor) 1.8V, Active High, UART TX communications data line to U601 (BB Processor) 1.8V, Active High, Enable line Enables U501 (Bluetooth) internal voltage regulators 1.8V, Pulse Code Modulation (PCM) clock reference from U601 (BB Processor) 1.8V, Pulse Code Modulation (PCM) audio data from U601 (BB Processor) 1.8V, Pulse Code Modulation (PCM) audio data to U601 (BB Processor) 1.8V, Pulse Code Modulation (PCM) frame synchronization signal 0V(0) or 1.8V(1), Active High, Signal line from U1501 (WLAN Transceiver) Disables U501 (BT Transceiver) when WLAN is active 0.8Vp-p to 1.5Vp-p 26.0MHz clipped sine wave, Clock signal from X1501 (WLAN TCXO) Same as BT_CLK

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Key Components: Reference RIM Part Number FL501 U601 U1501 U1508 X1501 FIL-00271-001 DIG-00179-004 ANA-00537-002 DIG-00193-001 XTL-00018-001
Originator: Jason Bridger Document #: Date Created: Mar. 16, 2009 Last Revised By: Jason Bridger Department: MFG Training Revision #: 1.0.1 Approvals: Last Date Revised: Mar. 19, 2009

Description Bluetooth Bandpass Filter 2450MHz 50MHz Baseband Processor (Argon LV) WLAN Transceiver (MAC Baseband Processor) Dual OR Gate 26.0MHz Crystal Oscillator for WLAN TCXO

Notes and Applications:

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Originator: Jason Bridger Document #: Date Created: Mar. 16, 2009 Last Revised By: Jason Bridger Department: MFG Training Revision #: 1.0.1 Approvals: Last Date Revised: Mar. 19, 2009

6.0

Global Positioning System (GPS) Section

Gemini POP-21408-001 B does not support GPS functionality.

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Originator: Jason Bridger Document #: Date Created: Mar. 16, 2009 Last Revised By: Jason Bridger Department: MFG Training Revision #: 1.0.1 Approvals: Last Date Revised: Mar. 19, 2009

7.0
7.1.0

Wireless b/g LAN (WLAN) Section

WLAN Antenna Schematic (See Page 2, SCH-21408-001_revB.pdf )

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7.1.1
Originator: Jason Bridger Document #: Date Created: Mar. 16, 2009 Last Revised By: Jason Bridger Department: MFG Training Revision #: 1.0.1 Approvals: Last Date Revised: Mar. 19, 2009

WLAN Transceiver and Front End Module (PA) Schematic (See Page 15, SCH-21408-001_revB.pdf )

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7.1.2
Originator: Jason Bridger Document #: Date Created: Mar. 16, 2009 Last Revised By: Jason Bridger Department: MFG Training Revision #: 1.0.1 Approvals: Last Date Revised: Mar. 19, 2009

WLAN Transceiver (Power) and 26MHz TCXO Schematic (See Page 15, POP-21408-001_revB.pdf )

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7.1.3
Originator: Jason Bridger Document #: Date Created: Mar. 16, 2009 Last Revised By: Jason Bridger Department: MFG Training Revision #: 1.0.1 Approvals: Last Date Revised: Mar. 19, 2009

WLAN Power Management IC (PMIC) Schematic (See Page 15, POP-21408-001_revB.pdf )

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7.1.5
Originator: Jason Bridger Document #: Date Created: Mar. 16, 2009 Last Revised By: Jason Bridger Department: MFG Training Revision #: 1.0.1 Approvals: Last Date Revised: Mar. 19, 2009

WLAN Section Placement Diagram (See Page 2, POP-21408-001_revB.pdf )

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7.1.6
Originator: Jason Bridger Document #: Date Created: Mar. 16, 2009 Last Revised By: Jason Bridger Department: MFG Training Revision #: 1.0.1 Approvals: Last Date Revised: Mar. 19, 2009

WLAN Information and Reference

RF Signal Lines: Line Designation

Reference

Description

GPS_WLAN_RF_CONN_IN C236 Signal from GPS/WLAN Antenna (After TP204, Before SW202) GPS_WLAN_RF_CONN_OUT R216 Signal from GPS/WLAN Antenna (After SW202) CAUTION! RF Coaxial Connectors (SW202) and RF Spring Contacts (TP204) are Easily Damaged, Do Not Probe These Contacts! WLAN_ANT_2G WLAN_RF_IO WLAN_RF_RXN / WLAN_RF_RXP WLAN_RF_TXN / WLAN_RF_TXP Voltage Supplies: Line Designation V1_2WLAN V1_8DIG V1_8DIG V1_8DIG V1_8DIG V1_8DIG V1_8DIG V1_8DIG V1_9WLAN VPWR_SYS VPWR_SYS VSYS VSYS VSYS R213 L1502
No Access No Access

Signal from Antenna to FL1501 (SAW Filter) Signal from FL1501 (WLAN SAW Filter) to U1502 (WLAN Front End) Received Signal, Differential outputs to U1501 (WLAN Transceiver) Transmitted Signal, Differential inputs from U1501 (WLAN Transceiver)

Reference C1509
SM0 Bus

Description 1.2V, Supply from U1506 (WLAN Power IC) to U1501 (WLAN Transceiver) VDD12 inputs 1.8V Main SM0 Supply Bus from U901 (Power Management) 1.8V, Supplies U1501 (WLAN Transceiver) VDDIO inputs 1.8V, Supplies U1501 (WLAN Transceiver) VIOXIO input 1.8V, Supplies U1506 (WLAN Power IC) VIO input 1.8V, Supplies U1501 (WLAN Transceiver) NC input 1.8V, Supplies U1504 (OR Gate) 1.8V, Supplies U1508 (OR Gate) 1.9V, Supply from U1506 (WLAN Power IC) to U1501 (WLAN Transceiver) VDD19 inputs ?V, Supply Bus from U901 (Power Management) ?V, Supplies U1506 (WLAN Power IC) 2.85V Main SM2 Supply Bus from U901 (Power Management) 2.85V, Supplies U1506 (WLAN Power IC) 2.85V, Supplies U1507 (2.85V LDO)

C1511 C1512
No Access No Access No Access No Access

C1505 C1520
SM2 Bus

C1515 C1521

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Originator: Jason Bridger Document #: Date Created: Mar. 16, 2009 Last Revised By: Jason Bridger Department: MFG Training Revision #: 1.0.1 Approvals: Last Date Revised: Mar. 19, 2009

I/O Signal Lines and Clocks: Line Designation ABAND BT_ACTIVE BT_CLK_REQ BT_FREQ BT_PRIORITY STBY TCXO_26MHZ TCXO_26MHZ_VCC TCXO_VCC_EN VDB VDPA WLAN_26MHZ_TCXO WLAN_ACTIVE WLAN_ACTIVITY WLAN_DETN / WLAN_FE_DETN WLAN_DETP / WLAN_FE_DETP WLAN_EN

Reference
No Access

TP503
(Near U501)

R504 (DNP) TP515

(Near U501)

TP502
(Near U501) No Access

C1523 C1522 R1504 (DNP) C1501 C1503 C1508 TP504

No Access No Access No Access

TP1503

Description 0V(0) or 1.8V(1), Active High, Signal line from U1501 (WLAN Transceiver) Signals U1506 (WLAN Power IC) to switch on U1502 (WLAN Front End) 0V(0) or 1.8V(1), Active High, Signal line from U501 (BT Transceiver) Signals U1501 (WLAN Transceiver) that U501 (BT Transceiver) is actively transmitting 0V(0) or 1.8V(1), Active High, Signal line from U501 (BT Transceiver) to U1508 (OR Gate) Signals U1508 (OR Gate) to assert a high on TCXO_VCC_EN 0V(0) or 1.8V(1), Active High, Signal line from U501 (BT Transceiver) Bluetooth reserved channel indication 0V(0) or 1.8V(1), Active High, Signal line from U501 (BT Transceiver) Bluetooth priority signal 1.8V, Active High, Puts U1506 (WLAN Power IC) into standby mode (all LDOs on) 0.8Vp-p to 1.5Vp-p 26.0MHz clipped sine wave, Clock signal from X1501 (WLAN TCXO) 2.8V, Supplies X1501 (WLAN TCXO) 0V(0) or 1.8V(1), Active High, Signal line from U1508 (OR Gate) Enables U1507 (2.85V LDO) to turn on X1501 Supply from U1506 (WLAN Power IC) to U1502 (WLAN Front End) VLNA input Controls U1502 (WLAN Front End) LNA bias High current supply from U1506 (WLAN Power IC) to U1502 (WLAN Front End) VPA inputs Controls U1502 (WLAN Front End) PA bias 0.8Vp-p to 1.5Vp-p 26.0MHz clipped sine wave, Clock signal from X1501 (WLAN TCXO) Provides the clock signal reference for U1501 (WLAN Transceiver) 0V(0) or 1.8V(1), Active High, Signal line from U1501 (WLAN Transceiver) Disables U501 (BT Transceiver) when WLAN is active 1.8V, Output from U1504 (OR Gate) Active when WLAN_LNAEN or WLAN_PAEN is asserted high Signals U601 (BB Processor) that the WLAN LNA or PA are enabled Negative RF power detector output from U1502 (WLAN Front End) Positive RF power detector output from U1502 (WLAN Front End) 0V(0) or 1.8V(1), Active High, Signal line from U601 (BB Processor) Enables or disables U1506 (WLAN Power IC) and the WLAN subsystem

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Originator: Jason Bridger Document #: Date Created: Mar. 16, 2009 Last Revised By: Jason Bridger Department: MFG Training Revision #: 1.0.1 Approvals: Last Date Revised: Mar. 19, 2009

I/O Signal Lines and Clocks Continued: Line Designation WLAN_HFCLK_EN WLAN_INT WLAN_LFCLK WLAN_LNAEN

Reference R1505
No Access No Access

No Access

WLAN_PAEN

No Access

WLAN_RESET_N WLAN_REXT WLAN_SD_CLK WLAN_SD_CMD WLAN_SD_DAT0 WLAN_SD_DAT1 WLAN_SD_DAT2 WLAN_SD_DAT3 WLAN_VSW_OUT WLANRS

No Access

R1503
No Access No Access No Access No Access No Access No Access

C1516
No Access

Description 1.8V, Active High, Enables the WLAN 26.0MHz TCXO via U1508 (OR Gate) Signals U601 (BB Processor) Interrupt signal from U1501 (WLAN Transceiver) to U601 (BB Processor) 32.768kHz slow clock signal from U901 (Power Management) to U1501 (WLAN Transceiver) Signal is called EXT_32K at U901 (Power Management) 1.8V, Active High Signal from U1501 (WLAN Transceiver) to U1506 (WLAN Power IC) and U1504 (OR Gate) Enables WLAN_ACTIVITY and the LNA in U1502 (WLAN Front End) 1.8V, Active High Signal from U1501 (WLAN Transceiver) to U1506 (WLAN Power IC) and U1504 (OR Gate) Enables WLAN_ACTIVITY and the PA in U1502 (WLAN Front End) 0V(0) or 1.8V(1), Active Low, Reset line from U601 (BB Processor) Resets U1506 (WLAN Power IC), U1501 (WLAN Transceiver) is reset via the WLANRS signal line External reference, datasheet does not specify the purpose 1.8V ?MHz, SD clock from U601 (BB Processor) to U1501 (WLAN) Note: Line is called WLAN_CLK at U601 1.8V, SD command I/O line to/from U601 (BB Processor) and U1501 (WLAN Transceiver) Note: Line is called WLAN_CMD at U601 1.8V, SD data I/O line to/from U601 (BB Processor) and U1501 (WLAN Transceiver) Note: Line is called WLAN_DAT0 at U601 1.8V, SD data I/O line to/from U601 (BB Processor) and U1501 (WLAN Transceiver) Note: Line is called WLAN_DAT1 at U601 1.8V, SD data I/O line to/from U601 (BB Processor) and U1501 (WLAN Transceiver) Note: Line is called WLAN_DAT2 at U601 1.8V, SD data I/O line to/from U601 (BB Processor) and U1501 (WLAN Transceiver) Note: Line is called WLAN_DAT3 at U601 Routes output from U1506s (WLAN Power IC) internal switching power supply pin A1 (VSW) to the switcher input to the chips internal LDOs pin E1 (VFB) Active Low, Resets U1501 (WLAN Transceiver)

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Confidential
Originator: Jason Bridger Document #: Date Created: Mar. 16, 2009 Last Revised By: Jason Bridger Department: MFG Training Revision #: 1.0.1 Approvals: Last Date Revised: Mar. 19, 2009

I/O Signal Lines and Clocks Continued: Line Designation Reference Description Note: There are currently no fixtures or engineering software tools provided to support the following debug lines: WLAN_GPIO8 WLAN_RS232_RX WLAN_RS232_TX WLAN_UART_RX Key Components: Reference RIM Part Number FL1501 U601 U901 U1501 U1502 U1504 U1506 U1507 U1508 X1501 FIL-00155-001 DIG-00179-004 ANA-00614-006 ANA-00537-002 ANA-00358-003 DIG-00193-001 ANA-00355-004 ANA-00463-001 DIG-00193-001 XTL-00018-001 R1502 TP1502 TP1501 TP1511 Debug UART transmit, Pulled Low by R1502 Debug RS232 receive line Debug RS232 transmit line Debug UART receive line

Description 2.4GHz Bandpass Filter, 100MHz Bandwidth Baseband Processor (Argon LV) BQ Huge Power Management IC WLAN Transceiver (MAC Baseband Processor) WLAN Front End Module Dual OR Gate WLAN Power Management IC 2.85V 150mA Linear Regulator (LDO) Dual OR Gate 26.0MHz Crystal Oscillator for WLAN Transceiver Generates 26.0MHz clock signal at 0.8Vp-p to 1.5Vp-p

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Notes and Applications:
Originator: Jason Bridger Document #: Date Created: Mar. 16, 2009 Last Revised By: Jason Bridger Department: MFG Training Revision #: 1.0.1 Approvals: Last Date Revised: Mar. 19, 2009

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