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ACKNOWLEDGEMENT
It is with the profound feelings of gratitude I would like to express my thanks to my institution SJB Institute of Technology for providing excellent infrastructure for the successful completion of my project. I would like to express my profound grateful to his divine soul Jagadguru Padmabhushan Sri Sri Sri Dr. Balagangadharanatha Mahaswamiji and his holiness Jagadguru Sri Sri Sri Nirmalanandanatha Swamiji for providing me an opportunity to pursue my studies in this esteemed institution. I would also like to express my profound thanks to his holiness Reverend Sri Sri Prakashnath Swamiji, Managing Director, SJB Institute of Technology, for his continuous support in providing amenities to carry out this project in this admired institution. I like to take immense pleasure in thanking Dr. Puttaraju, principal, SJB Institute of Technology, for giving me the best facilities which helped me in satisfactory completion of project work. I extend my immense pleasure in thanking Dr. Nagaraj K R., Head of the Department, Electronics and Communication Engineering, for providing me invaluable guidance for the project. My hearty thanks are also due towards my guide Dr. K. V. Mahendra Prashanth Professor., whose timely support and guidance helped me immensely in the completion of the project. I wish to express my heartfelt thanks to the project coordinator Mr. Bhaskar B., Department of Electronics and Communication, SJB Institute of Technology, for his valuable suggestions and cheerful encouragement to carry out my technical project. Lastly, I take this opportunity to extend my full hearted thanks, gratitude and respect to my Guardians, lecturers, library staff and all my friends, for giving me valuable advices and support at all times in all possible ways.

Akash V Hulkod

Dept., Of ECE, SJBIT, Bangalore

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LIST OF FIGURES
FIGURES
Fig 2.1 Iterative method multiplier. Fig 2.2 Linear Array multiplier. Fig 2.3 Tree Structure. Fig 3.1 Ripple Carry Adder Fig 3.2 Carry Save Adder Structure. Fig 3.3 Carry Look Ahead Adder. Fig 3.4 CLA using two parallel connection Fig 4.1 Wallace Reduction Flow. Fig 4.2 8*8 Wallace tree multiplier Fig 4.3. The algorithm for 8-bits x 8-bits multiplication performs by Wallace tree multiplier Fig 4.4. The block diagram for the 8-bits x 8-bits Wallace tree multiplier Fig 4.5: Logic circuit for a 1- bit half adder Table 4.1: Truth table for 1-bit half adder Fig 4.6 Full Adder(can be utilized as a CSA) Fig 4.7 Logic circuit for 1-bit full adder. Table 4.2: Truth table for 1- bit full adder Fig 4.8 Creation of an n-bit carries save adder Table 4.3: A Carry-save adder as a 1s counter Fig 4.9 A Carry- save adder also known as (3, 2) counter Fig 5.1 Simulated Output

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LIST OF ACRONYMS

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CONTENTS
Page No Acknowledgement..................................................................................................................... i Details

Contents. List of figures and tables........................................................................................................ Chapter 1: Introduction 1.1 Overview .. 1.2 Power Optimization..

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1.3 Multiplier Design.. 1.4 Languages and tools used..

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Chapter 2: Multiplication Architectures 2.1Iterative method... 2.2 Linear arrays .. 2.3 Parallel tree 3 4 5

Chapter 3: The Adders 3.1 Ripple carry adders... 3.2 Carry save adders 3.3 Carry Look Ahead adders ... 3.4 Analysis of adders Chapter 4: The Wallace Tree Multiplier 4.1 Overview.. 4.2 Simplest Implementation 4.3 Implementation of N-bit carry save adders . Chapter 5: Simulation Results 5.1 Purpose of simulation...... 5.2 Simulated results... 21 21 6 7 9 11 12 16 19

Chapter 6: Conclusion 6.2 Advantages ... 6.3 Disadvantages... 22 22

REFERENCES.
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