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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 31, NO. 1, JANUARY 1996

Low-Noise, High-Gain Si-Bipolar Preampliers for 10 Gb/s Optical-Fiber LinksDesign and Realization
Michael Neuh user, Hans-Martin Rein, Member, IEEE, and Horst Wernz a
Abstract Design principles and circuit congurations of Sibipolar transimpedance preampliers for 10 Gb/s optical-ber links are discussed. The target specications of the amplier are near the limit achievable by the available technology. Therefore, the different amplier stages had to be carefully optimized with respect to both at magnitude and constant group delay of the total transimpedance up to about 7.5 GHz. Two different versions of preampliers were fabricated in an advanced production technology (fT  23 GHz). High transimpedance (710
) and low p equivalent input noise current density (averaged:  9 pA/ Hz) were achieved.

I. INTRODUCTION PTICAL-FIBER links with data rates around 10 Gb/s are just under development. In the receivers of such links usually high-sensitivity transimpedance preampliers are required which should additionally have a high gain in order to avoid degradation of the signal-to-noise ratio by the succeeding main amplier. The aim of this paper is twofold. First, design considerations and circuit congurations of such ampliers are discussed. It is shown how the performance of a given technology can be exhausted with respect to maximum operating speed and low noise (at given gain). Second, a silicon bipolar preamplier IC is presented. It stands out for the highest transimpedance and the lowest equivalent input noise current density reported for 10 Gb/s Si-bipolar preampliers (cf., [1] and the references given there). In addition, a modication of this circuit with differential output is presented. The ampliers were fabricated by use of a Si-bipolar production technology (advanced version of Motorolas MOSAIC V) [2]. It is characterized by a self-aligned double-polysilicon process, an effective emitter width of 0.4 m, selective collector implantation, 4 metallization layers, and a transistor transit frequency of about 23 GHz. II. DESIGN CONSIDERATIONS Fig. 1(a) shows the circuit diagram of the basic transimpedance amplier (TIA) discussed in this paper. It consists of a transimpedance stage (TIS) at the input and a transadmittance stage (TAS) at the output. These stages are
Manuscript received February 16, 1995; revised June 25, 1995. M. Neuh user was with Ruhr-University Bochum, AG Halbleiterbauelea mente, D-44780 Bochum, Germany. He is now with Siemens Entwicklungszentrum f r Mikroelektronik, A-9500 Villach, Austria. u H.-M. Rein is with Ruhr-University Bochum, AG Halbleiterbauelemente, D-44780 Bochum, Germany. H. Wernz is with ANT Nachrichtentechnik, D-71522 Backnang, Germany. Publisher Item Identier S 0018-9200(96)00112-6.

connected by two emitter-follower stages, which are required for both level shifting and decoupling and which can be additionally used for gain peaking at the upper frequency limit. The driving photodiode (PD) is modeled by a simple equivalent circuit. Due to their strong inuence, all bond are inserted in the gure, together with inductances . and are external decoupling the bond pads capacitors. The amplier in Fig. 1(a) is based on the principle of strong impedance mismatching between the different stages. This principle is highly recommended for all kinds of (dc coupled) broadband ampliers. In simplied circuit theories the cascaded emitter-follower stages are often assumed to decouple the input of the TAS ideally from the output of the TIS. This would require a constant voltage gain ( 1), a very high input impedance, and a very low output impedance up to the maximum operating frequency. Based on this assumption it is sometimes stated that the low-pass characteristic of the ( total TIS, given by the time constant collector-base capacitance), could be simply compensated by . the high-pass characteristic of the TAS, given by However, this simplication fails in the present case. The reason is that due to the high bandwidth required, the transistor is drastically reduced at the cutoff current gain frequency of the amplier so that the decoupling capability of an emitter follower is considerably degraded. For the same reason, the (originally low) output impedance of the TIS increases with increasing frequency and the (originally high) input impedance of the TAS decreases. Both facts further degrade the desired impedance mismatching. Another reason for the failing of the simple theory is the essential inuence of the bond inductances which have, therefore, to be considered carefully in the design. This is why measurement results must be given for the mounted chip (Section IV) instead of wafer-prober results usually resubstrate ported. In the technology applied, a low-ohmic is used. Consequently, the substrate resistances in series to the metallization-substrate capacitances (including bond pads) and to the collector-substrate capacitances of the transistors are low. This fact makes the design and the mounting of the IC (including decoupling on the measuring substrate) more critical because of potential high-Q resonances caused by the and ) and the bond inductances (especially at pads parasitic capacitances. Achieving maximum bit rates requires a at response of the and an approximately magnitude of the transimpedance constant group delay within the frequency range of interest.

00189200/96$05.00 1996 IEEE

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(a)

(b)

(c) Fig. 1. Basic transimpedance preamplier (TIA): (a) circuit diagram (RF = 735
, RE = 24
), (b) frequency response of the total transimpedance (simulated), and (c) transfer functions of the different stages versus frequency (simulated). The results without the adjustable peaking network NW are given by dashed lines.

These conditions have to be met at least up to an upper roughly given by frequency (1) Here is the maximum bit frequency which is dened by GHz data rate (Gb/s) . Approximation (1) is based on the following considerations. From the designs of various linear broadband ampliers, operating near the speed limit of a given technology, we learned that the opening of an pseudo random eye diagram can be roughly approximated by an eye diagram generated by superimposing the pulse sequences 1010 and 11001100 only (e.g., [3]). These periodic sequences are composed of their fundamental (freand , respectively) and their (odd-numbered) quency harmonics. For the 1010 sequence only the fundamental with frequency must be considered. The harmonics are negligible since they are far beyond the cutoff frequency of the amplier and, moreover, have a very small amplitude (due to the limited pulse steepness of the input signal). However, for the 11001100 the rst harmonic with frequency has still to be considered [cf., relation (1)], while the higher harmonics have only small amplitudes. A data rate of 10 Gb/s ( GHz) thus requires an upper amplier frequency of GHz, at least.

The deviation of the group delay from the constant (lowresults in a deviation of the phase frequency) value from the ideal value with (2)

where . In this paper is used for characterizing the phase distortion. The following discussion is based on the transfer functions of the different stages of the TIA, shown in Fig. 1(c). These stages are distinguished by the index . Here, both the magnitudes and the phase deviations of a (complex) transfer function are shown.1 The deviations from the ideal responses have to compensate one another with respect to both a at total and a small total at least up to [cf., Fig. 1(b)]. The solid lines represent the simulation results of the nominal design with an active on-chip peaking network (NW) at the output buffer stage, which can be adjusted still after chip mounting via external potentiometers [1], [4]. For comparison, the results without this network are shown as dashed lines. Note that for characterizing the total transimpedance correctly, the output voltage must be related to the internal current of the PD rather than to the input current of the amplier [cf., Fig. 1(a)].
1 Note

that the currents and voltages given in Fig. 1 are phasors.

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 31, NO. 1, JANUARY 1996

Fig. 2. Simulated equivalent input noise current density versus frequency with and without the input bond inductance L1 (= 2 nH).

Now design aspects will be briey discussed regarding the frequency response of the different stages, shown in Fig. 1(c). Here, we proceed from the input to the output of the amplier. Between the PD and the amplier input an overlength bond wire is used. Its inductance is adjusted to the photodiode capacitance in such a way that the resonance frequency of the input circuit (3) approximates . The resulting peaking of near this frequency, shown in Fig. 1(c), improves the performance of the amplier in the following manner. First, the equivalent input noise current density is reduced as shown in Fig. 2. Second, the low-pass characteristic of the transimpedance stage (TIS) is partly compensated. The transfer function of the unloaded TIS, , is shown in Fig. 1(c). Its frequency response is dominated by the time constant , as mentioned before. Usually, the output impedance of the TIS grows comparatively high in the upper frequency range, which let us expect a drop of the related to the unloaded case ( ). However, output voltage since the real part of dominates near , it can be compensated by the negative real part of the input impedance of the two (loaded) emitter followers. As a result, even an increase of with frequency (at a decrease of the phase deviation) can be observed, which helps to compensate the low-pass characteristic of the TIS. The transfer function of the two cascaded emitterfollower stages shows only a weak dependence on frequency. However, the magnitude of the transfer function of the TAS normally decreases strongly with frequency [Fig. 1(c)]. , This decrease, which is caused by the bond inductance is partly equalized by the on-chip capacitor . The phase deviation of partly compensates that of . In addition to , gain peaking is obtained by a series and the peaking connection of the on-chip capacitor network NW, which is shunted to the series connection of and [1]. Due to the inductive output impedance of NW, which mainly consists of two cascaded emitter followers, series-resonance peaking occurs in the upper frequency range further increasing [solid lines in Figs. 1(b) and 1(c)]. The frequency response of can be optimized in a comparatively

wide range after chip mounting by simply adjusting external potentiometers connected to the pads to in Fig. 1(a). In this way, the output impedance of NW can be changed by varying the currents through the emitter followers of NW, and, moreover, the junction capacitance can be varied via its bias voltage. The at frequency response of the total transimpedance , shown in Fig. 1(b), demonstrates the efciency of the compensation technique used. It should be mentioned that in this design has been chosen as high as possible in order to obtain maximum gain and input sensitivity. Note that a high not only reduces the noise contribution of this resistance but also of the following stages due to the increased gain of the rst stage (TIS). is the highest value reported for 10 Gb/s preampliers. At the end of this section the optimum choice of operating points and dimensions of the different transistors shall be discussed briey. Since the data rate demanded is near the limit given by the available technology the main aim of the design was to reach 10 Gb/s at the desired input dynamic range. Thus, the collector currents through the transistors and the transistor dimensions were mainly optimized regarding this aim rather than to squeeze out the last percents of input sensitivity. The minimum emitter area of a transistor is given by (4) is the worst-case value of the (voltage and temHere, perature dependent) critical collector current density, above which the transit time of the transistor increases due to highcurrent effects (e.g., [9]). At the minimum emitter stripe width m we get for the total emitter length (5) and [cf., Fig. 1(c)] and For for and was optimal with respect to maximum data rate. has the strongest From all transistors the TIS transistor inuence on circuit performance. For the reasons mentioned above, its collector current was doubled compared to that value which was optimal for minimum noise. However, the increase of the averaged equivalent input noise current density, , was 6% only. Moreover, it was found that also the optimum emitter length must be nearly doubled compared to the , despite the fact that (because of minimum value ) the dominating time constant is now higher than the lowest possible value. The reason for this surprising dimensioning is that this was the most effective way to reduce the total phase deviation and thus the time jitter. The reduced cutoff frequency of the TIS was compensated by increased peaking in the other stages. Of course, the comparatively long emitter of is also advantageous with respect to low noise, due to the low base resistance ( ). III. CIRCUIT CONFIGURATIONS The circuit diagram of the TIA in Fig. 1(a) is one of the fastest [1] as well as most robust and exible approaches. As

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Fig. 3. Transimpedance amplier with differential output (STIA).

a certain disadvantage, two additional decoupling capacitors and are required. Sometimes an extra emitter follower is connected is used in the feedback loop of the TIS or to the emitter of the rst emitter-follower stage. There are advantages and disadvantages of these approaches [4]. Two problems in very-high-speed designs are the stronger peaking due to the increased phase delay in the feedback loop (which must be compensated) and the more critical interface at the output of the TIS. Fig. 3 shows a transimpedance amplier with differential output, shortened STIA ( stands for symmetrical). In this case the inactive side of the differential transadmittance stage is connected with a dummy consisting of the transimpedance stage (TIS) and the two emitter followers (2 EF), which do not need a decoupling capacitor. Therefore, for the total STIA one decoupling capacitor less than for the standard TIA is required. Such an output conguration allows a differential interface between the preamplier and the succeeding main amplier (e.g., [5]), which might be advantageous at very high data rates. IV. EXPERIMENTAL RESULTS For measuring, the chips were mounted on ceramic test xtures with 50 striplines and SMA-connectors, using a conventional bonding technique. Fig. 4 shows the measured magnitude and the phase deviation of the transimpedance of the TIA [Fig. 1(a)] versus frequency for different adjustments of the peaking network NW. The lowis 710 , and the maximum 3 dB frequency value of cutoff frequency is GHz. As discussed above, the frequency response can be varied within a wide range by adjusting few external potentiometers. This option allows a ne-adjustment of the preamplier to the overall transmission system, e.g., with respect to optimum eye diagrams or input sensitivity (cf., [1]). Note, that for this and the other entirely electrical measurements the PD is modeled as shown in Fig. 1(a) and the output signal is related to the internal current of the PD.2 Fig. 5 shows the output eye diagrams of the TIA at 10 Gb/s which corresponds to the solid-line small-signal characteristics
2 In this case, the PD capacitance is modeled by a thin lm capacitor on the substrate and the current source of the PD is realized by a 50 loaded pulse generator with 1 k in series to the output [1].

Fig. 4. Measured magnitude and phase deviation of the transimpedance of the TIA for different adjustments of the peaking network NW.

(a)

(b)

Fig. 5. Measured output eye diagrams of the TIA at 10 Gb/s for two different signal sources: (a) pulse generator and (b) modulated PD. In this example the input current swing is II Ap-p .

1 = 155

in Fig. 4. The left diagram is obtained by electrical measurements alone. In the right diagram the TIA is driven by a pin photodiode which is illuminated by the modulated light of a laser diode using an external modulator. In both cases a pseudorandom pulse generator with a word length of bits is used [6]. In these examples the input current swing is 155 - . However, as conrmed by measurements, there is no perceptible change of the eye diagrams within the total demanded dynamic range ( - ). of The measured equivalent input noise current density the TIA is shown in Fig. 6 in dependence of frequency. If GHz we get pA/ Hz. This averaged up to is the best value reported for bipolar 10 Gb/s transimpedance ampliers. Using a PD with a responsivity of 1 A/W an input sensitivity of the front end of 23 dBm has been estimated. It should be mentioned that the measured operating speed of both ampliers is about 10% below the simulation predictions. This difference might be a consequence of slightly too optimistic preliminary transistor parameters used for circuit design and of some uncertainties in modeling the parasitics caused by chip mounting and measuring substrate (cf., Section II). On the other hand, the measured equivalent input noise current density is slightly lower than the simulated one. This result might be caused by the fact that the correlations between the noise sources were not considered in the SPICE simulation.

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 31, NO. 1, JANUARY 1996

input dynamic range of 33 dB, and two differential outputs with a constant output voltage swing of 500 mV - . V. SUMMARY By use of a Si-bipolar production technology two different transimpedance preampliers for 10 Gb/s optical-ber links were realized. The measured data of both ampliers are summarized in Table I. The high transimpedance ( ) and the low equivalent input noise current density ( pA/ Hz) are record values for Si ICs operating at such a high data rate. These results were achieved by a careful design of the different stages of the amplier in such a way that their frequency responses compensate one another as far as possible. Moreover, a peaking network allows ne-adjustment after chip mounting. Simulations based on an advanced laboratory technology [8] let us expect that Si-bipolar preampliers with similar data but twice the operating speed (i.e., data rates of about 20 Gb/s) will be available in the near future. ACKNOWLEDGMENT
(a) (b)

Fig. 6. Measured equivalent input noise current density of the TIA versus frequency.

Fig. 7. Measured output eye diagrams of the STIA: (a) 10 Gb/s and (b) 12 Gb/s. In this example the input current swing is II Ap-p .

1 = 170

TABLE I MEASURED DATA OF THE PREAMPLIFIERS

The authors would like to thank J. Lehmann and A. Ghazinour for preliminary studies, and W. Bambach for valuable suggestions. Moreover, they thank the staff members of Motorola in Phoenix and Toulouse for fabricating the chips. They are also indebted to U. Langmann and M. Bumann, RuhrUniversity Bochum, for making available the pseudorandom pulse generator.

REFERENCES
[1] M. Neuh user, H.-M. Rein, H. Wernz, and A. Felder, A 13 Gbit/s Si a bipolar preamplier for optical front ends, Electron. Lett., vol. 29, pp. 492493, Mar. 1993. [2] V. de la Torre, J. Foerstner, B. Lojek, K. Sakamoto, S. L. Sundaram, N. Tracht, B. Vasquez, and P. Zdebel, MOSAIC VA very high performance bipolar technology, in Proc. IEEE 1991 BCTM, Minneapolis, MN, Sept. 1991, pp. 2124. [3] R. Reimann, Monolithic integrated wide-band ampliers in silicon bipolar technology for optical transmission systems in the Gbit/s range (in German), Ph.D. dissertation, Ruhr-University Bochum, Germany, 1990. [4] H.-M. Rein, M. Neuh user, H. Wernz, and V. Flan cker, A 6.5 a o Gbit/s transimpedance preamplier in silicon bipolar technology for optical-ber transmission links, Frequenz, vol. 46, pp. 174176, May 1992. [5] M. M ller, H.-M. Rein, and H. Wernz, 13 Gb/s Si-bipolar AGC o amplier IC with high gain and wide dynamic range for optical-ber receivers, IEEE J. Solid-State Circuits, vol. 29, pp. 815822, July 1994. [6] M. Bumann, U. Langmann et al., PRBS generation and error detection above 10 Gb/s using a monolithic Si bipolar IC, IEEE J. Lightwave Tech., vol. 12, pp. 353359, Feb. 1994. [7] M. Neuh user, M. M ller, H.-M. Rein, and H. Wernz, Low-noise, a o high-transimpedance Si-bipolar AGC amplier for 10 Gb/s optical-ber links, IEEE Photonics Technol. Lett., vol. 7, pp. 549551, May 1995. [8] T. F. Meister et al., Sub-20 ps silicon bipolar technology using selective epitaxial growth, in Proc. IEDM 92, San Francisco, Dec. 1992, pp. 401404. [9] H. St bing and H.-M. Rein, A compact physical large-signal model u for high-speed bipolar transistors at high current densities, part I: One-dimensional model, IEEE Trans. Electron Devices, vol. 34, pp. 17411751, Aug. 1987.

Finally, the amplier with differential output (STIA, Fig. 3) was measured. The eye diagrams at 10 and 12 Gb/s are shown in Fig. 7. In this example the input current swing is - resulting in an output current swing of mV ). Again, the amplier is driven by the electrical equivalent circuit of the PD. The eye diagrams look even better compared to those of the TIA. However, the input noise is somewhat higher (by about 1 pA/ Hz). In [7] it was shown that this preamplier can be mounted together with an automatic-gain-control (AGC) main amplier [5], on a single ceramic substrate without any stability problem. The total (two-chip) AGC amplier operates up to 10 Gb/s and stands out for a total transimpedance of 45 k , an

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Michael Neuh user was born in Bochum, Gera many, in 1963. He received the Dipl.-Ing. degree in electrical engineering from the Ruhr-University Bochum, Germany, in 1988. From 1990 to 1995 he was with the Institute of Electronics (AG Halbleiterbauelemente) at the Ruhr-University as a Research Assistant, where he was involved in the design of high-speed silicon bipolar ampliers for present and future optical communication systems. In May 1995, he joined the Siemens Development Center for Microelectronics, Villach, Austria, where he is engaged in the development of analog BiCMOS circuits for telecommunication.

Horst Wernz was born in Ziegelhausen near Heidelberg, Germany, in 1952. He received the Dipl.Ing. degree in electrical engineering from the Technical University Darmstadt, Germany, in 1977. In 1978 he joined the Fiber Optic Systems group at ANT Nachrichtentechnik, Backnang, Germany, where he initially was involved in the development of analog ber TV-distribution system. Since 1980 he developed digital systems for optical communications in the Advanced Development Division. Currently he is working on the design of high speed integrated circuits for those systems with data rates up to 10 Gb/s.

Hans-Martin Rein (M92) received the Dipl.-Ing. and Dr.-Ing. degrees in electrical engineering from the University of Stuttgart, Germany, in 1964 and 1968, respectively. From 1968 to 1973 he worked in the eld of integrated circuit technologies for the Semiconductor Division of AEG-Telefunken, Heilbronn, Germany. As Head of the Departments Fundamentals of Integrated Circuits and MOS Circuits, he was responsible for the development of very fast bipolar circuits, CMOS time-piece ICs, ion-implanted MOS LSI circuits, and others. In 1973 he became Professor at Ruhr-University Bochum, Bochum, Germany, where he is teaching integrated circuits. Presently, his main elds of research are analog and digital high-speed bipolar ICs (especially for optical communication systems) and their fundamental limits, optimization techniques for integrated circuits, and modeling of very fast bipolar transistors (including SiGe HBTs). He is the author or co-author of more than 100 technical publications and of a textbook on integrated bipolar circuits.