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Electric Tutorial 1 from CMOSedu.com

Electric VLSI Design System Tutorials from CMOSedu.com (Return)

Tutorial 1 Layout and simulation of a resistive voltage divider
This tutorial will introduce you to the Electric VLSI design system. Its assumed that Electric (version 8.10 or later) and LTspice have been installed properly on your computer following the instructions here and here. With this assumption all layout and simulation work will be done (saved) in C:/Electric (where the Electric jar file resides). Ensure that you have increased the memory in your JVM as instructed above. Start Electric. You should see the following window. Note that this shouldnt be the first time youve started Electric since youve followed the instructions above and have set LTspice up for use with Electric and have increased the JVM. This is mentioned since its possible to simply save the Electric jar file to the desktop, double-click on it, to start/use Electric as discussed here.

Next go to menu item Window -> Color Schemes -> White Background Colors Using a white background will be useful in these tutorials so that ink is minimized if they are printed out Its often preferable to use a black background colors to ease the stress on your eyes ;-) Adjust the sizes of the windows to fill the available space as seen below.

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Well set Electric up for use in ON Semiconductors C5 process and fabrication through MOSIS. This process has two layers of polysilicon to make a poly1-poly2 capacitor, 3 layers of metal, and a hi-res layer to block the implant, and thus decrease in resistance, of poly2 to fabricate higher-value (than what we would get with poly1) poly2 resistors. Further, this process uses the MOSIS scalable CMOS (SCMOS) submicron design rules. While the C5 process is an n-well process well still draw the p-well, which will be ignored during fabrication, just to make the layouts more portable between processes. Next, go to File -> Preferences (or just hit the wrench/screwdriver menu icon) then Technology -> Technology to get to the window seen below. Change the information to match what is seen below. Note that the Analog Technology is selected. This selection shows the resistor and capacitor Nodes in the Component menu (discussed shortly).

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Next, the scale (lambda) for the C5 process is 300 nm using the MOSIS Scalable CMOS (mocmos technology in Electric, see image above) submicron design rules. To set the scale go to File -> Preferences -> Technology -> Scale and set mocmos scale to 300 nm as seen below.

Press OK to exit. Select Mark All Libs in the next Window to indicate you want all of the libraries marked with these changes. Here are my preferences (right click and save as), electricPrefs.xml which can be loaded if there are problems or to ensure consistency through the remainder of the tutorial. File -> Import -> User Preferences followed by navigating to where my preferences were saved imports these preferences if there are problems. We now have Electric set up to fabricate a chip in the C5 process via MOSIS (technology code is SCN3ME_SUBM with a lambda of 0.3 um, see the
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MOSIS page here at CMOSedu.com). Go to File -> Save Library As -> tutorial_1.jelib Next lets begin to draw the schematic of a resistive divider. Go to Cell -> New Cell and enter the cell name (R_divider) and view (schematic) seen below.

After selecting the Component tab on the left side of the window we get the following. The library name and cell name are seen above the Components, Explorer (for looking at the cells in your library), and Layers (useful in layouts to turn on/off the display of certain layers).

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In the Component menu there is a box containing a resistor and the word Normal. Click on the arrowhead in this box and select N-Well. This selects the N-Well schematic resistor Node. In Electric-speak a Node is a component used in a schematic or layout. Examples of Nodes include transistors, resistors, capacitors, etc. An Arc, which well discuss shortly, is used to connect Nodes together to form schematics or layouts. A wire is an example Arc in a schematic. Place the N-Well schematic resistor Node into the drawing area as seen below (left click the mouse button to place the Node). Use the Window menu commands to zoom in/out, fit, etc. the view after placing the Node.

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All Nodes have a highlight box that turns on, to indicate that the Node may be selected, when the cursor is placed over it. When a layout/schematic contains Nodes whose highlight boxes overlap the selection of a particular Node can be cycled through by pressing the Ctrl+mouse click (very useful in complex layout). Pressing Shift while clicking the left mouse button selects/de-selects an item (again, very useful). Select, by clicking on Node, the N-Well resistive Node. Next go to Edit -> Properties -> Object Properties (or simply Ctrl+I) to edit the properties of this Node, see below. The sheet resistance of n-well in the C5 process is roughly 800 ohms. The minimum width of n-well is 12 lambda so lets make a 10k resistor using a width of 15 and a length 187.5 (since sheet resistance varies we could round to 185). Enter the values as seen below. If the field for the Well resistance isnt showing hit the More button. Well use these same values when doing the corresponding layout.

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After pressing OK (not the X in the top right side of the window which would ignore your changes) we get the following. This is a schematic representation of a 10k N-Well resistor.

Before moving on go to Tools -> DRC -> Check Hierarchically (or just hit F5) to check the schematic for errors. The Electric Message window will indicate that there arent any errors.
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Its a good idea to get used to looking at the messages in this window. Listening to Electric can really save time ;-) Lets next make a layout corresponding to this schematic-view cell. Again, go to the menu item Cell -> New Cell and enter the Name and View seen below.

This will create a group of cells. Clicking on the + sign adjacent to the cell group (R_divider) name gives the following.

The red circle indicates a schematic view while the yellow circle indicates the cells layout view.
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Blue indicates an icon while black may indicate a Verilog view (among others). Notice, above the tabs, that the library name is tutorial_1 while the active cell name is R_divider{lay}. Also notice at the bottom of the screen is an indication of the technology and scale. When we start doing layout this area will also the indicate x and y position of the cursor. Next, go to the Components tab and select the N-well resistor Node in the bottom left-hand side of the menu (click on the arrowhead). Note that if this menu item isnt available, as seen below, then you didnt select the Analog option in the preferences near the beginning of this tutorial.

Set the size (Edit -> Properties -> Object Properties or better yet simply hit Ctrl+I) of the N-Well resistor to, as above, L=15, W=187.5, and a resistance of 10k. After fitting the display using the Window menu item we get the following. Notice, like the schematic N-Well resistor Node, that this Node is selected by moving the mouse over the Nodes highlight box and left clicking on the Node. Also note, again like the corresponding schematic Node, that this Node has two ports for connection to Arcs. In the figure below we moved the cursor towards the left port of the Node so that clicking on the Node selects this port.

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To verify the layout doesnt contain design rule errors go to Tools -> DRC -> Check Hierarchically (or just hit F5) to perform a design rule check. From this point on pressing F5 will be equivalent to saying that we are doing a design rule check of a layout or checking a schematic. After pressing F5 we see in the Electric Message window that there arent any errors (so lets make one). Edit the properties of the N-Well resistor Node above so that the width is 5. Press F5 to run the DRC. We get the following.

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Notice how the Electric Message window tells us that to step through the errors we press the greater-than key, >, to go forward through the errors or the lessthan key, < to go backwards through the errors Pressing OK above and then > gives the following view (after zooming in around the flashing red and black box indicating the errors location). Notice the type of error is indicated in the Message window.

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Pressing Ctrl+Z a few times gets back to the case where W =15 (or selecting the resistor Node and hitting Ctrl+I allows us to change it back manually) Press F5 to verify the layout is DRC free. Then use the menu item Window -> Fill Window to zoom back out. At this point lets verify that the schematic and layout views of the R_divider cells are equivalent. This layout versus schematic (LVS) verification is performed in Electric using Network Consistency Checking (NCC). To perform an NCC go to Tools -> NCC -> Schematic and Layout Views of Cell in Current Window. There shouldnt be any errors. However, if there are a table pops up that allows you to click on the error to view it in a new window. Since well be doing an NCC quite often lets setup a key that we can press on the keyboard to perform this menu selection. In other words lets bind a key to this menu selection. In the menu go to File -> Preferences -> General -> Key Bindings as seen below

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On the right, navigate to Tools -> NCC -> Schematic and Layout Views of Cell in Current Window Once this menu item is selected Add and bind L to this menu item (so we can do an NCC, aka LVS, each time we press L) Note that although we pressed lowercase l it shows up as uppercase L below. So lower case l will be bound to the NCC command. Press Add again in the window seen below. This next part is important. If a conflict exists when binding a key then Electric will tell you after you have added the key and pressed Add. You need to Remove All conflicts (important). If you dont select Remove All Conflicts then a key may be bound to two or more menu items causing crazy behavior!

Before connecting resistors together to form a voltage divider lets talk about the connection of the n-well and p-substrate. Since the C5 process used in this tutorial is an n-well process the p-type substrate is common to all NMOS devices and grounded. One of the electrical rule checks (ERCs) is to verify that the p-well (in our case this means p-substrate) is always connected to ground. Further, in this n-well process, if the design contains only digital circuits then we always want the n-well to be connected to VDD.

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