Reverse Short Channel Effect and Channel Length Dependence of Boron Penetration in PMOSFETs

Chitra Subramanian, Jim Hayden, William Taylor, Marius Orlowski and Tom McNelly
Advanced Products Research and Development Laboratory, Motorola 3501 Ed Bluestein Boulevard, Austin, TX78721.

ABSTRACT
The anomalous increase in reverse-short-channel effect of PMOSFETs, in the presence of boron penetration from the gate, is examined here. Based on an extensive simulation and experimental study, we demonstrate that the degree of boron penetration is a function of the channel length and that long channel transistors are more susceptible to boron penetration compared to short channel devices. This leads to the observed decrease in threshold voltage with increasing channel length and hence, an enhanced reverse-short-channel-like behavior in PMOSFETs. Using length scale arguments, we propose that silicon interstitial absorption into the gate oxide is responsible for blocking boron penetration at the edges of the channel as compared to the middle, thus making the short channel length transistors more immune to boron penetration as compared to long channel length ones.

RSCE is observed in the presence of boron penetration. To determine if this RSCE is caused by length dependent differences in nwell phosphorus profiles, fixed oxide charge, and/or boron concentration in the channel, Figure 2 shows MOSFET inversion channel capacitance (measured between gate and source/drain) for NMOS and for PMOS with boron penetration. with boron penetration

INTRODUCTION
-0.8 Boron penetration in surface channel PMOS transistors is becoming an increasingly important issue for scaling gate oxide thickness to 70A and below. PMOSFETs show a significant increase in threshold voltage (Vt) related reverseshort-channel effect (RSCE) in the presence of boron penetration [l]. Although there have been numerous papers discussing Vt dependence on boron penetration, this channel length dependenceofvt, which is important to PMOS scaling, has not been adequately addressed in the literature. This work constitutes the first in-depth look into this anomalous increase in reverse-short-channel Vt behavior of PMOS transistors that use thin gate oxides.
1

10

Channel Length (pm) Fig. 1 Measured PMOS Vt versus channel length (L) for . 50A gate oxides using nitrided oxide (no boron penetration) and regular oxide (with boron penetration).

DISCUSSION OF PMOS Vt VS. L

We first demonstrate that in the presence of boron penetration, the mechanism responsible for the reverse-short-channellike Vt behavior in PMOSFETs is not channel dopant movement but varying degrees of boron penetration with channel length (L).
Figure I shows Vt versus channel length (L) for PMOSFig.

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1 10 1 D

Channel Length (Dm)

2 .
Measured MOSFEf
inversion

channel

FETs with P+ polysilicon gate and 50A gate oxide (GOX), using either nitrided oxide (no boron penetration) or regular oxide (with boron penetration). A marked increase in- Vt

capacitance (Cinv) for NMOS and PMOS (with B penetration), for L=0.6, 1, 15pm.

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The inversion channel capacitance value of the L=15pm PMOS transistor (see Figure 2. inset) is 23% lower than that of the NMOS transistor of the same size, whereas, the L=0.6pm PMOS and NMOS transistor values are nearly identical (It was verified that this effect was not caused by poly depletion in the P+ gates by driving the poly into inversion). This implies that the L=15pm PMOS inversion layer is formed at an estimated 40A depth below the oxide interface unlike the L=15pm NMOS, which behaves like a regular surface channel device with the inversion layer forming at the silicon interface. Thus, the PMOS channel appears to be partially buried, indicating presence of a P-N junction in the channel due to boron penetration. This buried channel effect is reduced for L=lpm, while the L=0.6pm PMOSFET behaves essentially like a surface channel device. This indicates that reduction in channel boron concentration with decreasing L is the dominant factor in causing enhanced PMOS RSCE. While there have been several papers addressing PMOS Vt dependence on boron penetration, only 2 have addressed the length dependence issues [2,3]. The authors suggest that the amount of boron penetration is the same for all gate lengths, but that subsequent lateral out-diffusion at the gate edges during poly reox (due to segregation into the growing oxide, or due to concentration gradients and oxidation enhanced diffusion) results in less boron in the short gates compared to long gates. To examine the effect of gate poly reox on the boron in the channel, different reoxidation times/thicknesses were studied. Based on [2,3], the Vt would be expected to increase with increasing poly reox due to greater boron loss, but in our experiments the opposite was observed (see Figure 3).
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30 40 50 60 70 80 Poly Reox Time (min.) F g 4 Simulated long channel Vt vs poly reox time, for i. . various enhancements of B diffusivity in oxide. [ lx=3.16E-4 exp(-3.53eV/kT) cm2/s] 10 20 sistent with estimates from long channel MOSFET inversion capacitance. Figure 6 shows dopant profiles right after gate poly reox: no boron has penetrated into the channel at this time for 45X or even lOOX, so none would be available for segregation and removal during the reox as proposed in [2,3]. The final boron concentrations, therefore, are not dominated by the poly reox step, but rather reflect the total accumulated process heat. 1020

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Channel Length (wm)

0.02 0.04 0. 1 6 Depth (um) F g 5 Simulated final doping profiles in silicon in the i. . center of long gates for various B diffusivity enhancements.

0.00

F g 3 Measured Vt vs L for 2 poly reox times (15 min and i. . 40min) and thicknesses (50A and 75A).
Process and device simulations were performed, varying boron diffusivity through the oxide. To match experimental results, a 45x enhancement of boron diffusivity in the oxide was necessary (Figure 4). The resulting dopant profile cross-sections in Figure 5 show the P-N junction depth to be <loop\, con-

For each reox thickness two different back end heats were included (see Figure 7). With increasing back end heat, the Vt of the L=15pm device drops by 150mV, whereas that of the L=0.3pm drops less than 30mV, indicating a bigger increase in channel boron concentration for the longer device. Since this heat step does not involve oxidation at the gate edges and the source/drain (BF2) P+ implants are already in place, the differences in channel boron concentration could only be a

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direct consequence of greater boron penetration for a longer device. To further support this conclusion, Figure 8 shows that increasing boron penetration is accompanied by increas1020
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ing Vt scatter. Similarly in Figure 1, the L=15pm device, shows not only greater Vt drop compared to the L=lpm or OSpm, but the Vt scatter is greater as well. This suggests e that there is indeed more boron penetration in the longer d vice, and previous theories suggesting uniform boron penetration for all channel lengths cannot explain the variation in scatter. We have thus established that the observed PMOS RSCE is due to increasing susceptibility to boron penetration with length.

DISCUSSION OF BORON PENETRATION VS. L

The next step is to uncover the mechanism causing the dependence of boron penetration on gate length. The greater number of gate polysilicon grain boundaries (1500A grain size) could cause the increased boron penetration in the large device. This would lead to RSCE-like Vt increase with d e creasing width as well, but this is not the case (see Figure 9). Therefore, the observed dependence of boron penetration on device size is not an area effect, but is directly related to proc-

10'2

Gate Oxide

-0.02 0 0.02 0.04 Vertical position (pm) Fig. 6. Simulated doping profile in the center of a long gate immediately following poly reox step. No B is through the oxide even for a lOOx enhancement. +0.2 r -0.04

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Channel Length (pm) Fig. 7. Measured Vt vs L for different back end heats.

Channel Width (pm) Fig. 9. Measured PMOS Vt vs W, showing no width dependence in boron penetration.
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1 with boron penetration

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50 60 7b 80 Gate oxide thickness Ang Fig 8. Measured PMOS Vt vs gate oxide thickness for L=lSpm device. Shows increasing boron penetration in thinner oxides results in more Vt scatter as well.

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Fig. 10. Measured lVtl vs L for NMOS and PMOS. Shows similarity in length scales of RSCE, with length dependence of Vt even for L>=lpm
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esses originating at the edges of the channel in the length direction. We now note that: (a) the length scales over which the RSCE occurs in NMOS and PMOS transistors are very similar, i.e. differences in Vt are present between devices with L=15pm and L=lpm (see Figure lo), (b) the mechanism responsible for RSCE in NMOS is lateral diffusion of silicon interstitials 141 which can be readily absorbed into the gate oxide 151, (c) incorporation of foreign atoms (such as nitrogen) into the bottom of the oxide layer has been shown to block boron diffusion 161. Based on these observations we propose that, in the case of PMOS transistors, the interstitials captured similarly in the gate oxide inhibit boron penetration at the edges of the channel (see Figure 11). One important feature in support of this theory is the length scale over which the PMOS RSCE is observed. From Figure 10, we see a Vt difference between L=15pm and even devices with channel lengths as long as lpm. This indicates that the lengths over which the differences in boron penetration occur, extend at least several tenths of a micron. Simula-

tions were performed using a net lower boron concentration at the channel edges and varying the extent of the boron depleted region (E) (see Figure 12). For E=O.OSpm we observe no enhanced RSCE, from Figure 13. To match the experimental data, E>0.5pm is required. Penetrated boron itself, for the amount of heat in the process, cannot diffuse any more than 0.05pm. Silicon interstitials are the only available species capable of diffusing distances of the order of OSpm, which is needed to explain the observed RSCE.
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E=O.OSpm

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CONCLUSIONS

-L/2 Short Gate L/2 -L/2 Long Gate L/2 Fig. 11. Schematic of proposed mechanism for PMOS RSCE, with Si interstitials (I) that are absorbed into the gate oxide at the edges, blocking boron penetration

In conclusion, we have demonstrated that enhanced RSCE in PMOSFETs is caused by differences in the degree of boron penetration with channel length. Long channel transistors are more susceptible to boron penetration compared to short channel devices. Based on the length scales over which these Vt differences occur, the most likely explanation is that boron penetration is linked to interstitial absorption into the gate oxide, which reduces boron penetration at the edges of the channel compared to the middle, and this leads to the observed anomalous PMOS RSCE.
ACKNOWLEDGMENTS The authors thank the APRDL pilot line, process engineering and test areas for device fabrication, J.R. Pfiester for technical discussions, Bob Yeargain and Lou Parrillo for their support. REFERENCES 1. J. M. Sung, et al., IEDM Tech. Dig., p.447, 1989. 2. J. R. Pfiester, et al., IEEE EDL, p.247, V. 11, Jun. 1990. 3. C-Y. Chang, et al., IEEE EDL, p.437, V.15, Nov. 1994. 4. M. Orlowski et al., IEDM Tech. Dig., 632 (1987) 5. S.T. Dunham, et al., J. Appl. Phys. 3, p.2541 (1986) 6. H. Huang et al., IEDM Tech. Dig., p.421, 1990.

Fig. 12. Plot showing net channel doping used in 2D simulations. Boron penetration has been blocked to an extent E from the channel edge.

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