Auroras Scientific & Technological Institute

Gagillapur(V), Quthubullapur (M), R. R Dist, Hyderabad-43.

The Complete Manual for ECAD LAB

Written By

ECE Department

Content

Page no 1) 2) 3) 4) 5) 6) 7) 8) 9) 10) 11) 12) Gates DFF 7474 Decade counter 7490 and decade counter 7490 (beh) 4-bit counter 7493 Shift Register 7495 Universal shift Register 74195 3x8 decoder 74138 4 bit comparator 7485 8x1 mux 74151 and 1x8 DE-Multiplexer (BEH Style) 16x1 mux 74150 16x4 RAM 74189 Stack using 16x4 RAM 74189 Queue using 16x4 RAM 74189 3 4 6 9 12 14 16 18 21 23 25 27

1) gates
AND OR XOR NOT NAND NOR

---Add Truth tables and VHDL codes for All gates Separately.

2) Ic7474 (DFF with async active low clr and set)

Circuit Diagram:

Truth table:

block diagram:

D Clk

library ieee; use ieee.std_logic_1164.all; entity dff is port(d,clk,set,clr:in std_logic; q:buffer std_logic; qbar:out std_logic); end dff; architecture df of dff is begin process(clk,set,clr) begin if (clr = '0') then q <= '0';qbar<='1'; elsif(set = '0') then q <= '1';qbar<='0'; elsif rising_edge(clk) then q <= d;qbar<=not(d); end if; end process; end df;

3) decade counter 7490

circuit diagram:

block diagram:

LOGIC DIAGRAM:

Truth table: count 0 1 2 3 4 5 6 7 8 9

Q0 0 0 0 0 0 0 0 0 1 1

Q1 0 0 0 0 1 1 1 1 0 0

Q2 0 0 1 1 0 0 1 1 0 0

Q3 0 1 0 1 0 1 0 1 0 1

library ieee; use ieee.std_logic_1164.all; entity ic7490 is port(clk,s1,s2,r1,r2:in std_logic; q1,q2,q3,q4:out std_logic); end ic7490; architecture decount of ic7490 is component jkff port(j,k,clk,set,clr:in std_logic; q:buffer std_logic); end component; component rsff port(r,s,clk,set,clr:in std_logic; q:buffer std_logic); end component; signal se,cl,q11,q22,q33,q44:std_logic; signal one,qb44,q55:std_logic; begin one <= '1'; se <= not(s1 and s2); qb44<=not(q44); q55<=q22 and q33; cl <= not(r1 and r2);q1<=q11;q2<=q22;q3<=q33;q4<=q44; u1 : jkff port map ( one,one,clk,se,cl,q11 ) ; u2 : jkff port map ( qb44,one,q11,se,cl,q22 ) ; u3 : jkff port map ( one,one,q22,se,cl,q33 ) ; u4 : rsff port map ( q44,q55,q11,se,cl,q44 ) ; end decount;

--------------------------------------------------------------------

jk flip-flop---neg edge with set and clr --------------------------------------------------------library ieee; use ieee.std_logic_1164.all; entity jkff is port(j,k,clk,set,clr:in std_logic; q:buffer std_logic); end jkff; architecture jkf of jkff is begin process(clk,set,clr) begin if (clr = '0') then q <= '0'; elsif(set = '0') then q <= '1'; elsif falling_edge(clk) then q <= (not (j) and not(k) and q)or (j and not(k)) or (j and k and not(q)); end if; end process; end jkf; _____________________________________________________________________________

-----decade counter 7490 behavioral model----------------______________________________________________________________

library IEEE; use IEEE.std_logic_1164.all; entity AsynCounter4 is port( CLK, RESET, EN : in std_logic; count : out std_logic_vector(3 downto 0) ) ; end AsynCounter4; architecture arch_AsynCounter4 of AsynCounter4 is signal count_t : std_logic_vector(3 downto 0) ; begin process(RESET,CLK) begin if (RESET = '1' or count_t=1001) then count_t <= "0000" ; elseif (CLK'event and (CLK='1') and (EN = '1') then count_t <= count_t + "0001" ; end if ; end process ; count <= count_t ; end arch_AsynCounter4; ________________________________________________________________________

4)binary

ripple counter 7493

pin diagram:

block diagram:

Logic diagram:

Truth table: count 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Q0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Q1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Q2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Q3 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

library ieee; use ieee.std_logic_1164.all; entity ic7493 is port(clk,r1,r2:in std_logic; q1,q2,q3,q4:out std_logic); end ic7493; architecture bincount of ic7493 is component jkff port(j,k,clk,set,clr:in std_logic; q:buffer std_logic); end component; signal cl,q11,q22,q33,q44:std_logic; signal one:std_logic; begin one <= '1'; cl <= not(r1 and r2);q1<=q11;q2<=q22;q3<=q33;q4<=q44; u1 : jkff port map ( one,one,clk,one,cl,q11 ) ; u2 : jkff port map ( one,one,q11,one,cl,q22 ) ; u3 : jkff port map ( one,one,q22,one,cl,q33 ) ; u4 : jkff port map ( one,one,q33,one,cl,q44 ) ; end bincount; ------Add jk flip-flop---neg edge with set and clr ___________________________________________________________________________

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-------------------------------------------------------------------

4-bit UP counter with enable signal and asynchronous RESET Behavioral model ----------------------------------------------------------library IEEE; use IEEE.std_logic_1164.all; entity AsynCounter4 is port( CLK, RESET, EN : in std_logic; count : out std_logic_vector(3 downto 0) ) ; end AsynCounter4; architecture arch_AsynCounter4 of AsynCounter4 is signal count_t : std_logic_vector(3 downto 0) ; begin process(RESET,CLK) begin if (RESET = '1') then count_t <= "0000" ; elseif (CLK'event and (CLK='1') and (EN = '1') then count_t <= count_t + "0001" ; end if ; end process ; count <= count_t ; end arch_AsynCounter4;

________________________________________________________________________

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5) shift register ic7495 Pin diagram:

library ieee; use ieee.std_logic_1164.all; entity ic7495 is port(ds,p0,p1,p2,p3,s,cp1bar,cp2bar:in std_logic; q0,q1,q2,q3:out std_logic); end ic7495; architecture sftrg of ic7495 is component rsff port(r,s,clk,set,clr:in std_logic; q:buffer std_logic); end component; signal d0,d1,d2,d3,db0,db1,db2,db3,clk:std_logic; signal one,q11,q22,q33,q44:std_logic; begin one <= '1'; clk <= cp2bar when s = '1' else cp1bar; d0<= not((not(s) and ds)or(s and p0)); d1<= not((not(s) and q11)or(s and p1)); d2<= not((not(s) and q22)or(s and p2)); d3<= not((not(s) and q33)or(s and p3));

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db0<=not(d0);db1<=not(d1);db2<=not(d2);db3<=not(d3); q0<=q11;q1<=q22;q2<=q33;q3<=q44; u1 u2 u3 u4 end sftrg; : : : : rsff rsff rsff rsff port port port port map map map map ( ( ( ( d0,db0,clk,one,one,q11 d1,db1,clk,one,one,q22 d2,db2,clk,one,one,q33 d3,db3,clk,one,one,q44 ) ) ) ) ; ; ; ;

--rs flip-flop--neg edge with set and clr

library ieee; use ieee.std_logic_1164.all; entity rsff is port(r,s,clk,set,clr:in std_logic; q:buffer std_logic); end rsff; architecture rsf of rsff is begin process(clk,set,clr) begin if (clr = '0') then q <= '0'; elsif(set = '0') then q <= '1'; elsif falling_edge(clk) then q <= (not(r) and s)or(r and s)or(not(r) and not(s) and q); end if; end process; end rsf; _________________________________________________________________________

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6) universal shift register ic74195

block diagram:

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library ieee; use ieee.std_logic_1164.all; --use ieee.std_logic_unsigned.all; --use ieee.std_logic_arith.all; --use ieee.numeric_std.all; entity ic74195 is port(j,kbar,a,b,c,d,sh_ld,clk,clbar:in std_logic; qa,qb,qc,qd,qdbar:buffer std_logic); end ic74195; architecture unisftrg of ic74195 is component rsff port(r,s,clk,set,clr:in std_logic; q:buffer std_logic); end component; signal da,db,dc,dd,clkbar:std_logic; signal dba,dbb,dbc,dbd,one:std_logic; begin one <= '1'; clkbar <= not(clbar and clk); da<= not((sh_ld and j and not(qa))or(sh_ld and kbar and qa)or(not(sh_ld) and a)); db<= not((sh_ld and qa)or(not(sh_ld) and b)); dc<= not((sh_ld and qb)or(not(sh_ld) and c)); dd<= not((sh_ld and qc)or(not(sh_ld) and d)); qdbar<=not(qd);dba<=not(da);dbb<=not(db);dbc<=not(dc);dbd<=not(dd); u1 : rsff port map ( da,dba,clkbar,one,clbar,qa ) ; u2 : rsff port map ( db,dbb,clkbar,one,clbar,qb ) ; u3 : rsff port map ( dc,dbc,clkbar,one,clbar,qc ) ; u4 : rsff port map ( dd,dbd,clkbar,one,clbar,qd ) ; end unisftrg;

--ADD rs flip-flop---neg edge with set and clr

_________________________________________________________________________

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7) 3-8 decoder 74138

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library ieee; use ieee.std_logic_1164.all; entity ic74138 is port(a:in std_logic_vector (2 downto 0); en1bar,en2bar,en3:in std_logic; o:out std_logic_vector(7 downto 0)); end ic74138; architecture decoder3x8 of ic74138 is signal enable:std_logic; begin enable <= not(en1bar) and not(en2bar) and en3; process(a,enable) begin if(enable='1') then case a is when "000" => o <= "11111110"; when "001" => o <= "11111101"; when "010" => o <= "11111011"; when "011" => o <= "11110111"; when "100" => o <= "11101111"; when "101" => o <= "11011111"; when "110" => o <= "10111111"; when "111" => o <= "01111111"; when others => o <= "11111111"; end case; else o <= "11111111"; end if; end process; end decoder3x8;

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8) 4 bit comparator 7485

library ieee; use ieee.std_logic_1164.all; entity ic7485 is port(a,b:in std_logic_vector (3 downto 0); altbin,agtbin,aeqbin:in std_logic; altbout,agtbout,aeqbout:out std_logic); end ic7485; architecture comp4bit of ic7485 is begin process(a,b,altbin,agtbin,aeqbin) begin altbout <='0';agtbout<='0';aeqbout<='0'; if(a(3)>b(3)) then agtbout <= '1'; elsif(a(3)<b(3)) then altbout <= '1'; elsif((a(3)=b(3))and a(2)>b(2)) then agtbout <='1'; elsif((a(3)=b(3))and a(2)<b(2)) then altbout <='1'; elsif((a(3)=b(3))and(a(2)=b(2))and a(1)>b(1)) then agtbout <='1'; elsif((a(3)=b(3))and(a(2)=b(2))and a(1)<b(1)) then altbout <='1'; elsif((a(3)=b(3))and(a(2)=b(2))and(a(1)=b(1))and a(0)>b(0)) then agtbout <='1'; elsif((a(3)=b(3))and(a(2)=b(2))and(a(1)=b(1))and a(0)<b(0)) then

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altbout <='1'; elsif((a(3)=b(3))and(a(2)=b(2))and(a(1)=b(1))and(a(0)=b(0))and (agtbin='1') and (altbin='0') and (aeqbin='0')) then agtbout <='1'; elsif((a(3)=b(3))and(a(2)=b(2))and(a(1)=b(1))and(a(0)=b(0))and (agtbin='0') and (altbin='1') and (aeqbin='0')) then altbout <='1'; elsif((a(3)=b(3))and(a(2)=b(2))and(a(1)=b(1))and(a(0)=b(0))and (aeqbin='1')) then aeqbout <='1'; elsif((a(3)=b(3))and(a(2)=b(2))and(a(1)=b(1))and(a(0)=b(0))and (agtbin='0') and (altbin='0') and (aeqbin='0')) then altbout <='1'; agtbout <='1'; end if; end process; end comp4bit;

IC 7485 Comparator in other way( Behaviaral model)

------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity comparater is Port ( a : in STD_LOGIC_VECTOR (3 downto 0); b : in STD_LOGIC_VECTOR (3 downto 0); iagb : in STD_LOGIC; ialb : in STD_LOGIC; iaeb : in STD_LOGIC; agb : out STD_LOGIC; alb : out STD_LOGIC; aeb : out STD_LOGIC); end comparater; architecture Behavioral of comparater is begin process(iagb,ialb,iaeb,a,b) begin if(a>b) then agb<='1'; aeb<='0'; alb<='0'; elsif(a<b)then alb<='1'; agb<='0'; aeb<='0'; elsif (a=b) then if(iagb='1')then agb<='1'; alb<='0'; aeb<='0'; elsif(ialb='1')then alb<='1'; agb<='0'; aeb<='0';

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elsif(iaeb='1')then agb<='0'; aeb<='1'; alb<='0'; end if; end process;

end Behavioral;

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9) 8x1 mux 74151

library ieee; use ieee.std_logic_1164.all; entity ic74151 is port(d:in std_logic_vector (7 downto 0); s,c,b,a:in std_logic; y:buffer std_logic; w:out std_logic); end ic74151; architecture mux8x1 of ic74151 is signal sel:std_logic_vector (2 downto 0); begin sel <= c&b&a; w<=not(y); process(d,sel,s) begin

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if(s='1') then y <= '0'; case sel is when "000" => y <= d(0); when "001" => y <= d(1); when "010" => y <= d(2); when "011" => y <= d(3); when "100" => y <= d(4); when "101" => y <= d(5); when "110" => y <= d(6); when "111" => y <= d(7); when others => y <= '0'; end case; end if; end process; end mux8x1; else

1x8 DE-Multiplexer (BEH Style)

library IEEE; use IEEE.std_logic_1164.all; entity demux1x8 is port ( S : in STD_LOGIC_VECTOR(2 downto 0); --- sel lines data_in : in STD_LOGIC; Y : out STD_LOGIC_VECTOR(7 downto 0) end mux8x1; architecture arch_demux8x1 of demux8x1 is begin process(S,data_in) begin case S is when 000 => Y(0) <= data_in ; when 001 => Y(1) <= data_in ; when 010 => Y(2) <= data_in ; when 011 => Y(3) <= data_in ; when 100 => Y(4) <= data_in ; when 101 => Y(5) <= data_in ; when 110 => Y(6) <= data_in ; when 111 => Y(7) <= data_in ; when others => Y(7 downto 0) <= (others =>U) ; end case ; end process; end arch_demux8x1 ;

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10) 16x1 mux 74150

library ieee; use ieee.std_logic_1164.all; entity ic74150 is port(e:in std_logic_vector (15 downto 0); gbar,d,c,b,a:in std_logic; w:out std_logic); end ic74150; architecture mux16x1 of ic74150 is signal sel:std_logic_vector (3 downto 0); begin sel <= d&c&b&a; process(sel,gbar)

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begin if(gbar='1') then case sel is when "0000" when "0001" when "0010" when "0011" when "0100" when "0101" when "0110" when "0111" when "1000" when "1001" when "1010" when "1011" when "1100" when "1101" when "1110" when "1111" when others end case; end if; end process; end mux16x1; else w <= '1'; => => => => => => => => => => => => => => => => => w w w w w w w w w w w w w w w w w <= <= <= <= <= <= <= <= <= <= <= <= <= <= <= <= <= not(e(0)); not(e(1)); not(e(2)); not(e(3)); not(e(4)); not(e(5)); not(e(6)); not(e(7)); not(e(8)); not(e(9)); not(e(10)); not(e(11)); not(e(12)); not(e(13)); not(e(14)); not(e(15)); '1';

dataflow model library ieee; use ieee.std_logic_1164.all; entity icmux is port(I0,I1:in std_logic; gbar,a:in std_logic; w:out std_logic); end icmux; architecture mux2x1 of icmux is begin w <= ((not gbar)and (not a) and I0) or ((not gbar)and (a) and I1); end mux2x1;

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11) 16x4 RAM 74189

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; --use ieee.std_logic_arith.all; --use ieee.numeric_std.all; entity ic74189 is port(addr: in std_logic_vector (3 downto 0); datin:in std_logic_vector (3 downto 0); cs,we:in std_logic; datout:out std_logic_vector(3 downto 0)); end ic74189; architecture ram of ic74189 is type RAMtype is array(0 to 15) of std_logic_vector(3 downto 0); signal RAM1:RAMtype:=(others=>(others=>'0')); signal wena: std_logic; begin wena<= cs and we; datout <= RAM1(conv_integer(addr)) when ((cs='1')and(we='0')) else "ZZZZ";

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process (wena,addr,datin) begin if wena'event and wena = '1' then RAM1(conv_integer(addr)) <= datin; end if; end process; end ram;

8x4 SRAM Behavioral style Program with enable signal

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity SRAM8x4 is generic( width: integer:=4; depth: integer:=8; addr: integer:=3); port( Clock: in std_logic; Enable: in std_logic; Read: in std_logic; Write: in std_logic; Read_Addr: in std_logic_vector(addr-1 downto 0); Write_Addr: in std_logic_vector(addr-1 downto 0); Data_in: in std_logic_vector(width-1 downto 0); Data_out: out std_logic_vector(width-1 downto 0) ); end SRAM8x4; architecture behavRAM of SRAM8x4 is -- use array to define the bunch of internal temparary signals type ram_type is array (0 to depth-1) of std_logic_vector(width-1 downto 0); signal tmp_ram: ram_type; begin -- Read Functional Section process(Clock, Read) begin if (Clock'event and Clock='1') then if Enable='1' then if Read='1' then -- buildin function conv_integer change the type -- from std_logic_vector to integer Data_out <= tmp_ram(conv_integer(Read_Addr)); else Data_out <= (Data_out'range => 'Z'); end if; end if; end if; end process; -- Write Functional Section process(Clock, Write) begin if (Clock'event and Clock='1') then if Enable='1' then if Write='1' then

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tmp_ram(conv_integer(Write_Addr)) <= Data_in; end if; end if; end if; end process; end behavRAM;

12)

stack using 16x4 RAM 74189

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity stack is port(datin:in std_logic_vector (3 downto 0); clk,rst,rd,wr:in std_logic; full,empty,half:out std_logic; datout:out std_logic_vector(3 downto 0)); end stack; architecture lifo of stack is component ic74189 port(addr: in std_logic_vector (3 downto 0); datin:in std_logic_vector (3 downto 0); cs,we:in std_logic; datout:out std_logic_vector(3 downto 0)); end component; signal dati,dato: std_logic_vector (3 downto 0); signal addr,pointer: std_logic_vector (3 downto 0); signal nwrds: std_logic_vector (4 downto 0); signal ena: std_logic; begin ena <= rd or wr; full <= '1' when (nwrds = 16) else '0'; empty <= '1' when (nwrds = 0) else '0'; half <= '1' when (nwrds = 8) else '0'; addr <= pointer; u1: ic74189 port map (addr,dati,ena,wr,dato); process (clk) begin if rising_edge(clk) then if (rd = '1') then datout <= dato; end if; if (wr = '1') then dati <= datin; end if; end if; end process; process (clk,rst) begin if(rst = '0') then pointer <= "0000"; nwrds <= "00000"; elsif rising_edge(clk) then if (rd = '1') then pointer <= pointer-1;

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if (wr = '0') then nwrds <= nwrds - 1; end if; end if; if (wr = '1') then pointer <= pointer+1; if (rd = '0') then nwrds <= nwrds + 1; end if; end if; end if; end process; end lifo;

Queue using 16x4 RAM 74189

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity queue is port(datin:in std_logic_vector (3 downto 0); clk,rst,rd,wr:in std_logic; full,empty,half:out std_logic; datout:out std_logic_vector(3 downto 0)); end queue; architecture fifo of queue is component ic74189 port(addr: in std_logic_vector (3 downto 0); datin:in std_logic_vector (3 downto 0); cs,we:in std_logic; datout:out std_logic_vector(3 downto 0)); end component; signal dati,dato: std_logic_vector (3 downto 0):="0000"; signal addr,rp,wp: std_logic_vector (3 downto 0):="0000"; signal nwrds,nwords: std_logic_vector (4 downto 0);--integer range 0 to 17; signal read,ena: std_logic; begin --ena <= read or wr; full <= '1' when (nwrds = 16) else '0'; empty <= '1' when (nwords = 0) else '0'; half <= '1' when (nwrds = 8) else '0'; ena <= read or wr; u1: ic74189 port map (addr,dati,ena,wr,dato); process (clk) begin if rising_edge(clk) then read <= rd; nwords <= nwrds; end if; end process; process (rd,wr,rp,wp) begin if (rd = '1') and (wr = '0') then addr <= rp;

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else addr <= wp; end if; end process; --if (((rd = '0') and (wr = '1')) or ((rd = '0') and (wr = '0'))) then process (clk,dato,datin) begin if rising_edge(clk) then if (read = '1') then datout <= dato; end if; end if; if falling_edge(clk) then if (wr = '1') then dati <= datin; end if; end if; end process; process (clk,rst,rd,wr) begin if(rst = '0') then rp <= "0000"; wp <= "0000"; nwrds <= "00000"; elsif rising_edge(clk) then if (rd = '1') then rp <= rp+1; --if (wr = '0') then nwrds <= nwrds - 1; --end if; end if; elsif falling_edge(clk) then if (wr = '1') then wp <= wp+1; --if (rd = '0') then nwrds <= nwrds + 1; --end if; end if; end if; end process; end fifo;

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