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VLSI Testing and Design for Testability

Cheng-Wen Wu
Lab for Reliable Computing Dept. Electrical Engineering National Tsing Hua University

Introduction to VLSI testing Fault simulation Test pattern generation Design for testability (DFT): scan design Logic built-in self-test (BIST) Memory testing Memory BIST Memory diagnostics Boundary scan (IEEE 1149 family) & board-level test *Analog and mixed-signal circuit testing Core-based system-on-chip (SOC) testing *Delay test *Iddq test Array & FPGA testing *Concurrent error detection Test economics
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Chapter 1: Introduction
Cheng-Wen Wu
Lab for Reliable Computing Dept. Electrical Engineering National Tsing Hua University

Scope of testing Defect level and fault coverage Fault models
Classical faults Switch-level faults Timing faults Memory faults

Testing and test


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Typical IC Production Flow

Wafer Wafer Probe Test Probe Test Packaging Packaging

Visual Inspection Visual Inspection

Final Test Final Test

Marking Marking

QA Sample Test QA Sample Test

Shipping Shipping


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Why Testing?
Product quality Product reliability

Defect detected during IC test

Defect detected during system test

Defect detected during field test


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Test Cost
90 80 70 60 50 40 30 20 10 0 0.5um 0.35um 0.25um 0.18um

Test cost Package cost Silicon cost


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Scope of Testing
Engineering Test
Diagnostic Test Fault location Failure analysis Design and/or process debugging

Manufacturing Test
Characterization Test Performance characterization: parametric test Reliability characterization: bathtub curve (aging) Production Test Simple parametric test Functional test Reliability screening (burn-in)
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Fault: a physical defect in a circuit/system
Permanent fault: a fault that is continuous and stable, whose

nature do not change before, during, and after testing

Affecting the functional behavior of the system permanently A.k.a. hard fault or solid fault Usually quite localized Can be modeled

Temporary fault: a fault that is present only part of the time,

occurring at random moments and affecting the system for finite, but unknown, intervals of time
Transient fault: caused by environmental conditions No well-defined fault model Called soft error in RAM Often assumed no permanent damage was done

Intermittent fault: caused by non-environmental conditions Often repeatable Can use permanent fault models and repeated test with stress
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Fault Model and Error

Fault model: logical effect of a fault
Structure faults Stuck-at faults: stuck-at-0 and stuck-at-1 Bridging (short) fault Open (break) fault Transistor stuck-on and stuck-open faults Transition and delay faults Functional faults RAM coupling and pattern-sensitive faults PLA cross-point faults

Error: manifestation of a fault that results in an incorrect module output or system state
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Failure: deviation of a system from its specified behavior
Fault error failure

Failure mechanism: physical or chemical process that causes devices to malfunction; they manifest themselves on the circuit level as failure modes Failure mode: the cause of rejection of failed device (effect of failure mechanism), such as open/short interconnections, or degraded parameter values
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Testing and Fault Coverage

Testing is the process of determining whether a device functions correctly or not
How much testing of an IC is enough?

Yield (Y) is the ratio of the number of good dies per wafer to the number of dies per wafer Fault coverage (FC) is the measure of the ability of a test set T to detect a given set of faults that may occur on the DUT
FC = (#detected faults)/(#possible faults)


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Defect Level and Fault Coverage

Defect level (DL) is the fraction of bad parts among the parts that pass all tests and are shipped
DL = 1 Y**(1-FC)

FC refers to the real defect coverage (probability that T detects any possible fault---in F or not) DL is measured in terms of DPM (defects per million), and typical values claimed are less than 200 DPM, or 0.02%


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Defect Level and Fault Coverage

Required FC for DL = 200 DPM.

Y (%)






FC(%) 99.99






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The Testing Problem

Given a set of faults in the circuit under test (CUT), how do we obtain a certain (small) number of test patterns which guarantees a certain (high) fault coverage?
What faults to test? (fault modeling) How are test patterns obtained? (test pattern

How is test quality (fault coverage) measured?

(fault simulation)
How are test vectors applied and results evaluated?

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Fault Modeling: Stuck-at Fault

a b c c stuck-at 0; c s-a-0; c s/0, or c/0

a 0 0 1 1

b 0 1 0 1

c 0 0 0 1

c(a/0) c(a/1) c(b/0) c(b/1) c(c/0) c(c/1) 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1

Single (line) stuck-at fault: line has a constant value (0/1) Multiple stuck fault: several single stuck-at faults occur at the same time
For a circuit with k lines, there are 2k single stuck faults, and 3 -1

multiple stuck faults

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A test for a fault f in circuit C is an input combination for which the output(s) of C is different when f is present than when it is not
A.k.a. test pattern, test vector, or experiment A test x detects fault f iff C(x)Cf(x)=1

A test set for a class of faults F is a set of tests T such that for any fault fF, there exists tT such that t detects f
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Fault Diagnosis
Fault detection: tells only whether a circuit is fault-free or not Fault identification (location; isolation): provides the location and the type of the detected fault and other related information Fault diagnosis: includes both fault detection and fault identification


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Testing is a process which includes test pattern generation, test pattern application, and output evaluation
The quality of a test set depends on its fault

coverage (FC) as well as its size

FC (typically 98-99% single stuck faults) can

be determined by fault simulation


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