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RESEARCH

Computer-aided
Hanliang Zhu

NOTE

analysis for digital counters

Huazhong (Central China) University of Science and Technology, Wuhan, Hubei, China

Ta-MingFang
Boston University, Boston, MA 02215, USA (Received February 1982; revised November 1982)

An effective is presented. realized matrix method. Key words:

method

of analysing reduced without

digital

counters

with the help of a matrix flip-flops,

operation may be

The counters

are composed

of simple J-K

having one J and

one K, with connections straightforwardly

to the simplest complicated

mode so that digital counting logic circuits. techniques,

This computer-aided e.g. the waveform

analysis is easier to use than are the traditional

computer

aided design, digital

counters,

matrix

analysis, J-K flip-flops

Introduction
The digital counters to be discussed here consist of simple
J-K flip-flops, having only one J and one K. Simple connec-

any column of A. The matrix derived from Figure 2 is as follows: J3 0 0 1


A= 0 0 0 0 0

K3 0 0 1

J2 0 0 0

K2

Jl 0 1 0 0 0 0

Kl 0 0 1 0 0 0,Ql Q3 Q3 Q2 Q2 Ql

tions are used so that the counting may be performed without intricate logic circuits. Traditionally the waveform method has been used to analyse such digital counters (see Figure I). We are proposing, however, a matrix operational method which will prove to be much more effective. Once the mathematical model is developed, the analysis may be performed directly by the computer, so that the results may be obtained more quickly and accurately.

1 0 0 0 0 0

1 0

-0

Mathematical modelling
A three-bit digital counter which consists of three simple
J-K flip-flops is shown in Figure 2. Without any compli-

(2) The initial state of the counter is decided by the original states of the flip-flops in it, so that: So=

Q~oQ~oQIo

cated logical circuits it may count in cycles of certain beats endlessly. Using a matrix operation we can analyse such a digital counter. The procedure for constructing this mathematical model is as follows. (1) We write out a matrix A which reflects the circuit connections of the counter. A is a square matrix. The number of rows or columns is twice the number of counter bits. The rows are called Q3, @, Q2, D, Ql and Ql and columns are J3, K3, J2, K2, Jl and Kl in the present example. Each element in A has its Boolean value which shows the citcuit connection status: 1 means connection, 0 otherwise. For example, since J2 is connected to Ql the value of the element in the fifth row (Ql) and the third column (J2) should be 1. The rest may be similarly deduced. In accordance with circuit principles there is usually only one 1 in
0307-904X/83/04295-07/$03.00 0 1983 Butterworth & Co. (Publishers) Ltd

Here So is the initial state of the counter and Qso, Q20 and QIo are the original status of flip-flops Q3, Q2 and QI. Let us create a matrix Bo to use in an intermediate operation: Bo = IQ30 Q30 Q20 Q20 Qlo

&lo1

In the example given, if we set So = 000 thenBo= [OlOlOl]. (3) The next state of a particular counter after receiving a clock pulse is determined by its recent state and by the signals appearing at the J and K inputs of each flip-flop, and these signals are determined by the recent state of the counter and the circuit connections. The product of matrices B and A can indicate those signals mentioned above. Suppose that the matrix indicating the signals on the J and K is called P, so:
P=[J, K3 J2 K2 J1 K,]

and

P=BA

Appl.

Math.

Modelling,

1983,

Vol. 7, August

295

Research Note
-J 4 --K d K Q -J 3 d K Q J 2 8, K Q J 1 a Q-

In our example the next state (state 1) must be: Sl=

Q~IQzIQ,, 001 =

This means that flip-flops 3 and 2 have not changed their status and flip-flop 1 has changed from 0 to 1 after receiving a clock pulse.
Q4

(5) Following the same procedure, B1 = [OlOl IO]


Q,

B1 is written from S,:

PI = BIA 000100 000010 110001 000000 001000 000000

= [OlOl lo]
Q2

= [001010]

then
Q,

Sa=Oll Bz = [Ol lOlO] P,=B*A= [lllOll]

CP

then
s3=

110
=

Figure

A simple feedback

shift counter

and its output

waveform

B3

[101001] [IlOlOl]

P3=B3A= then Sq = 000


I-J
3

+,

Here state S4 is the same as Se; thus it can be seen that the counter shown in Figure 2 works with a 4-beat cycle and can function as a divide-by-four counter. (6) A counting cycle graph can be written down as in Figure 3, where an octal digit is being used. It is easy to describe the counting process when the initial state of a counter has been changed. For example, if we set the counter to another initial state Se as: Se=5 = 101

-K

figure

Three-bit

digital counter

For the initial state mentioned P,, = BOA 000100 I = [010101] 000010 :, :,

above, we have:

then Ba= [100110] therefore P,, = BOA = [OOllOO]

1 then : i ; :, = [000010] si= 111 B1 = [lOlOlO] 0 0 0

001000

Lo

0-l

therefore P1=BIA=[llllO1] then Sz = 000


o-1

Therefore Jae=O, K3e=0,JzO= K1e=O.

0, KzO= O,JlO=O and

(4) Then the next state of the counter can be determined by the value of the elements in PO and the excitation logic of the J-K flip-flop:

Qil= &Jio + QioKio


Here Qie is the original status of the ith flip-flop, Qi, is the next state of the ith flip-flop, Ji, is the signal on J of the ith flip-flop during its original status, and Ki, is the signal on K of the ith flip-flop during its original status.

i
6-3 Figure 3 Counting

cycle graph for octal digit

296

Appl.

Math.

Modelling,

1983,

Vol.

7, August

Research Note
5

(2) If we set

se = 000 $
2-7-o-1

then

4 figure 4 Assembled counting

6 -3

T I
3
I

Be = [010101] therefore PO = BOA 0100 0000 0010 0001 1000 0000

cycle graph from figure

= [010101]

= [OOOl]

:
I

Fill two elements into their proper places in POto correspond to the two Js which are connected to level 1. Then the revised P is obtained:
Pb = [101001]

figure

Digital counter

with some fixed

high-level inputs

so Thereafter, counting will repeat the process previously explained. The assembled counting cycle graph can be obtained after considering all the possible initial states. For the given example, it will be as shown in Figure 4. It is necessary to point out that if the initial state is: &=4= then
B,,=

si=

110

B1 = [lOlOOl]

therefore Pi = BIA = [OllO] Then fill in elements in PI:


P,= [101110]

100

[lOOlOl] 3

then s2 = 101
B1=

therefore P,, = BOA = [OOOlOO] then sr = 100 So the counter will ignore any clock pulse and will not change its state of Se = 100. A special symbol (4) is used (see Figure 4) to indicate that state 4 ignores the clock pulse.
Modification for fixed high-level signals

[lOOllO]

therefore
P2=B2A= Pi=

[llOl]

[llllOl]

then sa = 010
B3 = [OllOOl]

If some of the J and/or the K are connected with fixed logic signal 1 (high level), the respective columns in A will be blanked and A will be a non-square matrix. After finding P, these respective terms should be put into their proper place. The counter shown in Figure 5 is another example. The J of flip-flops 2 and 3 are connected with level 1. The same procedures are needed in order to find its counting cycle graph. (1) The non-square 0 0
A=

P3 = B3A = [OOlO] P; = [101010]

then sq=
B4=

111 [lOlOlO] [lllO]

P4=B4A= Pi=

[lllllO]

matrix A is: 0 0 1 0 0 0 cl 0 0 1 0 0

then & = 001


B5=

1 0 0 0 0 0

[OlOllO]

0 0 1 0

P, = B,A = [lOOl] p;=

[111001]

then sg= 110 =sr

APPI.

Math. Modelling,

1983,

Vol. 7,

August

297

Research Note
O-6-5-2

Figure 6

Counting

cycle graph for counter

I,+ !
of Figure 5

therefore
P,, = &,A

= [010101]

After POis revised, we obtain:


PA = [001001]

$
0.6-5.2

then Sr = 010 Br = [011001]


PI = B1A = [OOlO]

-14 Figure 7 Assembled counting

i-3 cycle graph from Figure 6

and
P1= [001010]

then &=Oll Ez = [011010]


P2 =&A = [lOlO]

and
1
Figure8 Digital counter with a fixed low-level input

P; = [Ol lOlO]

then

Hence the digital counter shown in Figure 5 works with a 5-beat cycle. It is a divide-by-five counter. The counting cycle graph is as shown in Figure 6. Set various initial states and then the assembled counting cycle is as shown in Figure 7.

After setting all the necessary initial states, it is a straightforward matter to get the total (assembled) counting cycle of this counter (see Figure 9). This shows that the circuit shown in Figure 8 is not actually a counter - it is not able to respond unceasingly to a clock pulse. The general case More generally, there is a digital counter which contains B bits and its initial state is: So = QB,,Q(B-I)~Q(B-z), Then Bo must be: Bo=
[QB~~B~Q(B-~)~,~(B-~)o . ..

Modification for fixed low-level signal

If some of the J and/or K are connected to logic level 0 (low level), the respective items in A are blanked and A must again be a non-square matrix. In the same way as was described in the previous section, it is necessary to fill some items into Plater. The counter shown in Figure 8 provides another example. Here the J of flip-flop 2 is connected to level 1 and the J of flip-flop 3 to level 0. (1) The matrix A is:
-0 0 A= 0 0 0 0 0 1 0 O_

... QIO

QIOQIOI

In accordance with the given circuit of this counter a matrix A can be written out and POcan then be calculated as a product of B. and A. The Boolean values of the elements in POtell us the logic level of the J and K of the given counter: Po=BoA =
[JB,KB~J(~--),K(B--), ...

JIOKIOI

7-1

1 -0

+
O-2-3

(2) If the initial state of the counter is set as: Se = 000 then Brj = [010101]
Figure 9 4-6~ Assembled counting 5 cycle graph from Figure 8

298

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Math.

Modelling,

1983,

Vol.

7, August

Research Note

and the next state Sr is determined Sr =

accordingly

as:

QB,Q(B-I), Q(E-2), . . . QU
l,...,B:

We decide S,+, asfollows.Fori=

Qi(n+,, = &An + Qi&in so that


&+l=

QB(~+I)Q(E-II)(~+I). . . Q,(n+,, + QB&~) + Q(B--l@p--lpA @(B-1)&i--I)n

= @don

. . @wbn + Q&n)
After getting each Si (j E (1, 2, . . . , n, n + 1, . . .>), it is necessaryto compare Si with the Se, Sr,. . . , Si_r obtained previously. j - 2, then we say this counter IfSj=Si,fori=O,..., works with (j - i) beats, or that it is a divide-by-0 -i) counter. If Si = Sj_r then we know that this counter will not count any more. It fails to be a counter. If Sj is not equal to any one of Se, Sr , . . . , Si_r, then Sj+r should be found continuously. After setting all the necessary initial states of this counter, a total (assembled) counting cycle can be obtained

150 155 160 165 170 175 180 185 190 195 200 205 210 215 220 225 230 235 240 245 255 260 265 270 275 280 285 290 295 300 305 310 315 320 325 330 335 340 345 350 355 360 365 370 375 380 385 390 395 400 405 410 415 420 425 430 435 440 445 450 455 460 465

Computer The program

simulation

The following program simulating the process of analysing a digital counter was written in BASIC and run successfully on an HP-85 microcomputer: REM *ANALYSIS COUNTER BY MATRIX * 10 REM *PROGRAM NAMED COUNT0 * 15 DISP BITS OF COUNTER B= 20 REM *IF THE COUNTER DISCUSSED HAS 3 BITS, LET B = 3 * 25 INPUT B 30 DIM Q2( 10,20), S(20) 35 DIM A(20,20), B(1,20), P(1,20) 40 FORJ=lTOB*2 45 FORI=lTOB*2 50 A(I,J) = 0 55 NEXT I 60 NEXT J 65 I=1 70 FOR W=B to 1 STEP-l 75 Q(w) = 1 80 1=1+2 85 NEXT W 90 I=1 95 FORW=Bto 1 STEP-l 100 DISP WHERE DOES J ( ;W:) GO TO 105 REM *IF 53 GOES TO Q2, LET J(3) = Q(2), IF IT GOES TO -02, LET J (3) =-O(2)* 110 REM *IF 53 GOES TO LEVEL iOR 0, LET J(3)=Al ORAO* 115 Al=B*2+1 120 AO=O 125 INPUT J(W) 130 IF J(W)< 0 THEN J(W) = ABS(J(W)) + 1 135 IF J(W) = Al THEN 155 140 IF J(W) = A0 THEN 170 145 NJW), I>= 1
5

GOT0 170 FORU=lTOB*2 A(U,l) = 1 NEXT U 1=1+1 DISP WHERE DOES K(W;W;) GO TO REM *THE SAME AS FOR J* INPUT K(W) IF K(W)< 0 THEN K(W) = ABS(K(W)) + 1 IF K(W)=Al THEN 215 IF K(W) = A0 THEN 230 A(K(W),I) = 1 GOT0 230 FOR U= 1 TO B*2 A(U,I) = 1 NEXT U I=Ifl NEXT W REM *INPUT ORIGINAL STATE OF COUNTER* I=1 REM *THE ORIGINAL STATE OF BIT 3 (FROM RIGHT TO LEFT) IS Q2(3,0)* S(0) = 0 FORW=BTO 1 STEP-l DISP THE ORIGINAL STATE Q2 (;W;,O) IS INPUT Q2(W,O) S(O)=S(O)+Q2(W,O)*2-(W1) B(1 ,I) = Q2P,O) B(l ,I + 1) = (Q2(W,O) + 1) MOD 2 1=1+2 NEXT W REM *MULTIPLY B BY A* Y=l FORK=lTOB*2 M=O FORJ=lTOB*2 M=M+B(l,J)*A(J,K) NEXT J P(l,K)=M IFM>lTHENP(l,K)=l NEXT K REM *THE NEXT STATES OF BIT 3 ARE ~2(3,1), ~2(3,2). . .* S(Y) = 0 FORW=lTOB C=B(l,W*2)ANDP(l,W*2-1) D=(P(l,W*2)+1)MOD2 E=B(l,W*2-1)ANDD Q2(B-W+l,Y)=CORE S(Y) = S(Y)+ Q2(B-W+ l,Y)*2-(B-W) B(l,W*2-l)=CORE B(l,W*2)=(B(l,W*2-l)+MOD2 NEXT W I=0 FOR W=Y TO 1 STEP-l IF S(Y) <> S(1) THEN 430 GOT0 445 1=1+1 NEXT W GOT0 500 REM *GET THE CARRY SYSTEM * IFY-I=lTHEN475 DISP THIS IS A; Y-I; BEATS COUNTER. PAUSE REM *PUSH CONTINUE KEY *

Appl. Math. Modelling,

1983,

Vol. 7, August

299

Research Note 470 GOT0 260 475 DISP IT IS NOT A COUNTER. 480 DISP TRY TO SET ANOTHER ORIGINAL STATE. 485 PAUSE 490 REM *PUSH CONTINUE KEY * 495 GOT0 260 500 Y=Y+ 1 505 GOT0 315 510 END THIS IS A 4 BEATS COUNTER S(0) 0 S(1) 1 S(2) 3 S(3) Z(4) 0 S(5) Warning 7 : NULL DATA 0 Set initial state as Se = 010: BITS OF COUNTER B= ? 3 WHERE DOES J(3) GOT0 L(2) WHERE DOES K(3) GOT0 L(2) WHERE DOES J(2) GOT0 L(l) WHERE DOES K(2) GOT0 k(3) WHERE DOES J( 1) GOT0 ? -Q(3) WHERE DOES K( 1) GOT0 k(2) THE ORIGINAL ? 0 THE ORIGINAL ? 1 THE ORIGINAL
0

Notes on the program The number of bits and the original state of the counter are set by the operator. When the program is running, all successive states of the counter after receiving a series of clock pulses are recorded in time. The last conclusion is given to show whether the circuit is a counter or not. If it really is a counter, the question of the number of beats of the counting cycle is answered. After the program has been executed, the operator may consult all the successive states of the counter with the help of the keyboard. Entering necessary initial states appropriately, the operator can get the total (assembled) counting cycle. The program used is suitable for counters which have fewer than 10 bits and fewer than 20 successive counting states. If it is not large enough a revision of the statements may be made to meet the requirements.

Results of using the program (1) The program was used to analyse the digital counter in Figure 2. The initiation state of the counter was set as Se= 000: BITS OF COUNTER B= WHERE DOES J(3) GOT0 J Q(2) WHERE DOES K(3) GOT0 L(2) WHERE DOES J(2) GOT0 k(l) WHERE DOES K(2) GOT0 L(3) WHERE DOES J(1) GOT0 ? -Q(3) WHERE DOES K( 1) GOT0 a(2) THE ORIGINAL STATE Q2(3 ,O) IS ? 0 THE ORIGINAL STATE Q2(2,0) IS ? 0 THE ORIGINAL STATE Q2( 1 ,O) IS )
0

STATE Q2(3 ,O) IS

STATE Q2(2,0) IS

STATE Q2(1 ,O) IS

THIS IS A 4 BEATS COUNTER S(B) 2 S(1) 7 S(2) 0 S(3) 1 S(4) 3 S(5) z(6) 0 (2) Execute the program to analyse the digital counter shown in Figure 5 and set the initial state as Se = 000: BITS OF COUNTER B=

300

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Math.

Modelling,

1983,

Vol.

7, August

Research Note 3

WHERE DOES K(2) GOT0 L(3) WHERE DOES J( 1) GOT0

WHERE DOES J(3) GOT0 ? Al WHERE DOES K(3) GOT0 a,l) WHERE DOES J(2) GOT0 ? Al WHERE DOES K(2) GOT0 L(3) WHERE DOES J( 1) GOT0 k(2) WHERE DOES K( 1) GOT0 ?

a(2)
WHERE DOES K( 1) GOT0 ? -Q(2) THE ORIGINAL STATE Q2(3,0) IS ? 1 THE ORIGINAL STATE Q2(2,0) IS ?
0

-Q(2)
THE ? 0 THE ? 0 THE ? 0 THIS S(0) i(l) i(2) 5 S(3) i(4) i(5) i(6) 6 (3) Execute the program to analyse the digital counter shown in Figure 8 and set the initial state as Se = 100: BITS OF COUNTER B= ? WHERE DOES J(3) G0~0 ? A0 WHERE DOES K(3) GOT0 L(l) WHERE DOES J(2) GOT0 ? Al ORIGINAL STATE Q2(3 ,O) IS

THE ORIGINAL STATE Q2( 1 ,O) IS ? 0 IT IS NOT A COUNTER TRY TO SET ANOTHER OR IGINAL STATE S(O) i(l) Z(2) 5 S(3) 2 S(4) 3 S(5) 3

ORIGINAL

STATE Q2(2,0) IS

ORIGINAL

STATE Q2( 1,O) IS

IS A 5 BEATS COUNTER

Conclusions
The computer-aided method of analysis of certain digital counters presented in this paper, with an algorithm based mainly on matrix operation, should be a replacement for the traditional methods, e.g. the waveform method. With the help of computers, the analysis becomes much easier and faster. With the help of the method presented all the circuits in reference 1 were tested and verified. They are all right except one. Circuit D shown in Lo is wrong. It is easy to find that J2 and K3 are supposed to be connected to Ql rather than 01 for constructing a divide-by-five counter, otherwise it is divide-by-four only. In addition, Lo says only 18 basic circuits satisfy all the conditions mentioned. Using the method discussed in Computer-aided design of digital counters, which is written on the basis of this paper, and we found another four circuits satisfied all the conditions required in Lo. So it tells us that the method presented in this paper is really useful and effective.

References
1 Lo, S. N. Decade counters, Instrum. 1977,24,213 IEEE Trans. Ind. Electron. Control

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