Introduction to

RF VCO Design

Sung Tae Moon

Nov. 2004

A M S C

Analog and Mixed-Signal Center

Contents

n Introduction
n VCO design procedure
n Quadrature generators
n Measurement
n Inductor measurement using microprobe

2
Introduction to VCO

n VCO stands for Voltage Controlled Oscillator.

n VCO is an Oscillator of which frequency can
be Controlled by external Voltage stimulus.

Vc Vo
control voltage output signal
VCO

3
VCO in Frequency Synthesizer

n One of major applications for VCO is a frequency

synthesizer.
n Frequency synthesizer provides sinusoidal/pulse
signals at predetermined frequencies that is
precisely controllable by digital words.
n Frequency synthesizer is a core building block of
any system that has to work at multiple frequencies
such as wireless communication transceivers.

4
VCO in Frequency Synthesizer cont.

n Frequency synthesizer usually consists of a

VCO, a PLL and a frequency divider.

fref
Vc Vo
PLL
output signal
phase lock loop VCO

%N

frequency divider

5
Requirements for VCO Design

n Frequency tuning range

q Tuning range must cover the entire band of operation.
n Phase noise
q Close to the oscillation frequency due to spontaneous jitter.
n Harmonic distortion
q Spectral impurity of the signal
n Signal power
q Must be high enough to drive the load.
n Power consumption

6
VCO for Bluetooth transceiver

n Frequency tuning range : 2.402 ~ 2.479GHz

n Phase noise : -128dBc/Hz@3MHz
n Harmonic distortion : less than 20dB
n Signal power : more 0dBm
n Power consumption : less than 8mA

7
Procedure 1. Specification Study

n Relatively low tuning range : 3.3%

n High frequency of oscillation : >2.4GHz
n Very high phase noise requirement

à LC tuned oscillator is most suitable

8
Procedure 2. LC Tuned Oscillator
n Oscillation frequency is
L tuned by resonant frequency
C
of LC tank.
1
ωo ≈
LC
M1 M2
n Cross-coupled transistors
work as a negative
resistance that sustains
oscillation by compensating
loss in the LC tank.
gm n Frequency is controlled by
L C R -R varying the capacitance of
the tank.

9
Procedure 3. On-chip Inductor

ωL n Specifications
Q≈
R q L = 2nH L R
q Q>5
n On-chip spiral inductor
must be simulated with
EM(Electro-Magnetic)
simulator such as
ASITIC.

ß ASITIC EM simulator

10
Inductance and Q

L ∝ Metal area Total area

Q ∝ Metal width
f self _ resonant ∝ 1 Metal area

n Q can be improved by increasing metal width.

n To keep L same, total area has to be increased.
n Increased metal area reduces self resonant
frequency

11
Procedure 4. MOSFET Varactor

n Back gate controlled PMOS varactor

n Accumulation mode G G G
VBG < 0
p+ p+
Cox
n

n Depletion mode B B B

G G G
0 < VBG < Vth
p+ p+
Cox
n
Cd

B B B

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Procedure 4. MOSFET Varactor (cont.)

n Inversion mode G
VBG > Vth
G G

p+ p+
Cox
n

B B B

13
Procedure 4. MOSFET Varactor (cont.)

n Accumulation/Depletion only varactor

G

n+ n+
n

B
n Inversion only varactor
G
VB = VDD

14
Procedure 5. Active Elements

n gm of the cross-coupled MOS pairs must be

high enough to compensate the loss of the
tank.
n It is a good idea to have plenty of margin in
design.
n The length of the transistors must be
minimum in order to minimize parasitics.

15
 Procedure 5. Active Elements (cont.)
gm

L C -R n Sources of the loss

1/go q Quality of L (QL)
RL RC q Quality of C (QC)
q Output impedance of the
transistor. (go)
 1 ωo C 
gm > α go + +  n Gm of the transistor must
 QLωo L QC 
be larger than total loss.
ωo L 1
QL = , QC = n α is safety margin for
RL ωo CRC
starting oscillation.
α >3
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Series-parallel conversion

L
C L C RP
RS

(ωo L) 2 RP (ωo L)
2
RS = = 2 RP = = QL RS
2

RP QL RS
n Only valid close to resonant frequency

17
Phase Noise

n Phase noise is uncertainty of center

frequency of VCO output
n The spectrum looks as if it has finite power in
certain frequency offset away from the center
frequency
n In time domain, phase noise is also referred
to as timing jitter

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Phase Noise (cont.)
n Signal amplitude
I tail (ωo L) 2
VA = I tail RP = = I tail QL RS
2

RS
n Noise power
4kTγg m RP  ωo  2  ωo 
2 2 2

vn =   = kTγg mQL RS  
2

 ∆ω   ∆ω 
2
4QL
n Phase noise
8kTγg m  ωo 
2 2
8vn
PN = 2 = 2  
I tail Q L  ∆ω 
2
VA
19
Phase Noise (cont.)

n Signal power can be increased either by

higher Q or by higher L
n Only high Q improves phase noise
n High power dissipation also improves phase
noise

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 Quadrature Signal Generation 1

n Two identical coupled

oscillators
q Immune to mismatch - I− I+

the coupled oscillators

synchronize to exactly
the same frequency
q Large area and power
dissipation
Q− Q+

n Lam, C.; Razavi, B. “A 2.6 GHz/5.2 GHz CMOS voltage-controlled

21
oscillator”, ISSCC, 1999, pp. 402-403
 Quadrature Signal Generation 2

n RC-CR network
q Low power : passive
element only
q Sensitive to mismatch
q Amplitude mismatch VOUT 1
VIN
VOUT 2

n Orsatti, P.; Piazza, F.; Huang, Q., “A 20-mA-receive, 55-mA-transmit, single-chip

22
GSM transceiver in 0.25 CMOS”, JSSC, vol 34, Dec. 1999 , pp. 1869-880
 Quadrature Signal Generation 3

n Polyphase network
+
q Low power VI I+
q Amplitude matching
q Insertion loss
Q+

−
VI I−

Q−

n Parssinen, A.; Jussila, J.; Ryynanen, J.; Sumanen, L.; Halonen, K.A.I., “A 2-GHz wide-band
direct conversion receiver for WCDMA applications,” JSSC, vol. 34, Dec. 1999, pp. 1893-903 23
Quadrature Signal Generation 4

n Divide-by-two circuit
q Relatively immune to Latch

mismatch
V
OUT 2 VIN VOUT 1
q Requires 2x frequency
oscillation which leads to Latch
high power dissipation

24
Layout of Bluetooth VCO

Phase shifter

Spiral Inductors

Varactor

MOS
Drivers
25
Chip Microphotograph

26
Another Layout (for 802.11b+BT)

27
PC Board

28
Using Spectrum Analyzer
FSE-K4 Phase noise
Spectrum Analyzer measurement software
Device Under Test Matching Network

on PCB

n A matching network to make the output impedance of

the VCO to match 50Ω is recommended
n The phase noise measurement can be automated by
using FSE-K4 software

29
Testing Results

n Since the frequency of oscillation is too high

for any oscilloscope available in the lab, the
spectrum analyzer is the only option for
testing the circuit.
n Measured parameters:
q Frequency tuning range : 2.37 ~ 2.72GHz
q Signal power : -12dBm
q Phase noise : -130dBc/Hz @ 3MHz

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Testing Results

n Tuning Range n Phase noise

q 2.37 ~ 2.72GHz q -130dBc/Hz @ 3MHz
offset

31
Inductor Measurement using Microprobe

Spiral
Pads for Inductor
microprobes

G S G

n Measurement instruments
q Probe Mount Station
q Microprobe (150µm pitch)
q Network Analyzer (HP 8719ET)
q SMA Coaxial cable

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Calibrating Network Analyzer
Standards
Probe Network
(open, short, 50Ω,
Station Analyzer
through)

Calibration

Coax

n Calibration is required to compensate the effect of

microprobes, coaxial cables and network analyzer itself.
n The effect of pads for microprobe landing cannot be
calibrated out. De-embedding after measurement is
required.

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Measurement Setup
Chip
Probe Network
(TSMC 0.35u
Station Analyzer
Spiral inductor) s-parameters

 s11 s12 
s s22 
 21

Coax

n The device under test is measured after calibration

n Network analyzer extracts the s-parameters

34
s-parameter to y-parameter Conversion
(1 − s11 )(1 + s22 ) + s12 s21
y11 =
Zo∆
− 2s12
y12 =
Zo∆
− 2s21
y21 =
Zo∆
(1 + s11 )(1 − s22 ) + s12 s21
y22 =
Zo∆
∆ = (1 + s11 )(1 + s22 ) − s12 s21
35
Modeling Inductor from y-parameter
i1
i1 i2 y11 = = Y1 + Y2
Y1 v1 v2 = 0

v1 Y2 Y3 v2 i1
y12 = = −Y1
v2 v1 = 0

i2
y21 = = −Y1
L

v1 v2 = 0

i2
y22 = = Y1 + Y3
z

v2 v1 = 0

36
Conclusion

n Basic concept of VCO is discussed.

n Design procedure of a 2.4GHz VCO for
Bluetooth application is presented.
n Testing result of the circuit is provided.

37