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GO TO ➢ Chapter 12
Table of ORCA FPSC/FPGA EXPRESS INTERFACE
Contents

This chapter covers the following topics:

Index
• OVERVIEW

Cover
• RELATED DOCUMENTATION
Page • SOFTWARE REQUIREMENTS
• SETTING THE DESIGN ENVIRONMENT
FPSC
Home
• DESIGN FLOW
• DESIGN ENTRY
List of • DESIGN IMPLEMENTATION
Docs
• THE ORCA FOUNDRY ENVIRONMENT

FPSC • DESIGN VERIFICATION

Tutorials

OVERVIEW
This chapter describes the ORCA Field Programmable System Chip (FPSC)
design interface between Synopsys FPGA Express design tool and the ORCA
Foundry™ place and route tools. Together, the tools provide a powerful and
integrated high-level design environment for ORCA FPSCs.

FPSC User’s Guide Version 1.2 12-1

ORCA FPSC/FPGA Express Interface
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GO TO ➢ RELATED DOCUMENTATION
Table of
This chapter assumes that you are familiar with ORCA-Series FPGAs and
Contents
FPSCs. This chapter is meant to be used with the following documents:

Index • ORCA Foundry/Synopsys FPGA Express Interface Manual

• Lucent Technologies FPSC Data Sheet
Cover
Page • Lucent Technologies FPGA Data Book
• Lucent Technologies ORCA Foundry Libraries Manual
FPSC • ORCA Foundry User’s Guide
Home
• FPGA Express User’s Guide
• FPGA Express Online Help
List of
Docs

FPSC
Tutorials SOFTWARE REQUIREMENTS
The ORCA FPSC/Synopsys FPGA Express Interface is compatible with the
following software:

• ORCA FPSC Design Kit

• ORCA Foundry version 9.35
• Synopsys FPGA Express 3.1

FPSC User’s Guide Version 1.2 12-2

ORCA FPSC/FPGA Express Interface
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GO TO ➢ SETTING THE DESIGN ENVIRONMENT

Table of
Contents
This section helps you customize your environment for designing an ORCA FPSC
using the Synopsys FPGA Express tool.

Index
Environment Variables
Cover Make sure you have installed the ORCA Foundry 9.35 software CD and that the
Page FOUNDRY environment variable is set. Also make sure that you have installed
the ORCA FPSC kit and that the FPSC environment variable is set. The
FPSC FOUNDRY variable points to the ORCA Foundry software installation directory.
Home
On the workstation, the FOUNDRY variable should be set as follows:
List of
$ setenv FOUNDRY <library_installation_directory>
Docs
$ setenv FPSC<fpsc_design_kit_installation_directory>

FPSC
Tutorials Note

This chapter assumes that you are using the c-shell. If not, use the
appropriate syntax and procedures to set the environment variable for
your shell.

This command may be entered into your .cshrc or .login file so that the
environment is properly set upon login.

FPSC User’s Guide Version 1.2 12-3

ORCA FPSC/FPGA Express Interface
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GO TO ➢ DESIGN FLOW
Table of
This section describes the interface between Synopsys FPGA Express and
Contents
ORCA Foundry for designing with the ORCA FPSC devices. The interface allows
you to:
Index
• Synthesize an ORCA FPSC design using Synopsys FPGA Express.
Cover • Use the ORCA Foundry tools to read in the EDIF file, map the design into a
Page selected ORCA FPSC device, then place and route the design.
• Perform a static timing analysis using the ORCA Foundry TRCE tool.
FPSC
Home • Program the final design into the selected ORCA device.

Figure 1 shows a typical design flow for generating logic designs with Synopsys
List of FPGA Express and the ORCA Foundry software. For additional information on the
Docs synthesis flow, consult your Synopsys FPGA Express documentation. For
information on the ORCA Foundry Development System, consult your ORCA
FPSC Foundry manuals and tutorials.
Tutorials

FPSC User’s Guide Version 1.2 12-4

ORCA FPSC/FPGA Express Interface
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GO TO ➢ Figure 1. ORCA FPSC/Synopsys FPGA Express Interface Design Flow

Table of
Contents
SCUBA
CREATE HDL/
EDIF .edn FILE
Index FPSC DESIGN
SHELL
Cover
Page SYNOPSYS CREATE ORCA
FPGA PROJECT FOUNDRY MAP DESIGN
EXPRESS ENVIRONMENT (mapsh)
FPSC ENVIRONMENT
ANALYZE
Home DESIGN IN
FPGA EXPRESS STATIC
TIMING
List of ANALYSIS
Docs CREATE IMPLE (trcesh)
-MENTATION
(TARGET
FPSC ORCA3FPSC) PLACE AND
Tutorials ROUTE
SYNTHESIZE DESIGN
DESIGN (parsh)

ESTABLISH STATIC
DESIGN TIMING
CONSTRAINT Netlist Writer ANALYSIS
(ngd2vhd/ (trcesh)
ngd2ver)
COMPILE/
OPTIMIZE
DESIGN Write VHDL, GENERATE
Verilog SDF BIT FILE
Netlists (bitsh)
WRITE WRITE EDIF
VHDL/ NETLIST
Verilog

ORCA Backend
Frontend Simulation using
Simulation using VHDL/ ORCA
Verilog Verilog/VHDL Device
Verilog/VHDL Simulator
Simulator FPSC CORE
VHDL/
Verilog NeoPrim
MT350CDE VITAL/
VITAL/ Verilog
Verilog

FPSC User’s Guide Version 1.2 12-5

ORCA FPSC/FPGA Express Interface
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GO TO ➢ DESIGN ENTRY
Table of
Contents
The following steps outline how to synthesize designs for ORCA with Synopsys
FPGA Express and ORCA Foundry:

Index 1. Generate the FPSC Interface module (including the core and the interface
buffers) by running the FPSC Configuration Manager, fpscsh and selecting
Cover the appropriate module and the relevant configuration.
Page
2. Create the design in Verilog HDL, VHDL, or EDIF. The designs may be
technology-independent or contain ORCA-specific functions; however, they
FPSC cannot contain instances of functions from other technology libraries. If it
Home
contains ORCA cells then make sure that the cells are ORCA Series 3
components only. Please refer to the Lucent Technologies ORCA Foundry
List of Libraries Manual for a list of valid ORCA Series 3 components.
Docs
3. Create a top level design file which includes the FPGA portion of the design
FPSC and the FPSC portion of the design. To help the designer construct the FPSC
Tutorials portion of the design, VHDL and Verilog templates have been provided for the
FPSC in the $FPSC/or3tp12/misc dir.

4. For Verilog designs, the FPSC core library model has to be included from the
$FPSC/or3tp12/express/lib/verilog dir.

5. (Optional) Verify that the design description is correct by simulating the HDL
description.

6. Set up the design by creating a project in FPGA Express and identifying the
source files. The design files are automatically analyzed when they are added
to the project.

7. Double click on the top level design file and Create Implementation by right
clicking on the architecture. Select the target architecture and device,
including the exact package and speed grade.

8. Optimize for Speed (Optimize for Area when smallest implementation is

desired for design). Select a Map Effort of High.

FPSC User’s Guide Version 1.2 12-6

ORCA FPSC/FPGA Express Interface
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GO TO ➢ 9. Turn ON Preserve Hierarchy if you want to keep the hierarchy intact for the
entire design. On the other hand the designer can selectively Preserve/
Table of Eliminate hierarchy on a per-module basis using the Modules window in the
Contents
Constraints window.

Index 10. Create (Synthesize) the design implementation.

11. Specify the Design Constraints using the design implementation

Cover
Page spreadsheets. The design implementation spreadsheets enable the designer
to control the optimization of specific modules, entities, and sub-designs. The
tables are customized for the ORCA device family. The tables will help you
FPSC capture the period, rise time, and fall time for each system clock, the input and
Home output delays at each port, and other design-specific port attributes such as
built-in I/O registers and pull-up and pull-down registers. The designer can
List of also lock the I/Os by specifying a pad location in the Pad Loc column for the
Docs corresponding port. The optimization controls for hierarchy, primitives, and
arithmetic operator sharing have a strong effect on the final results. The
FPSC
designer should preserve hierarchical boundaries during optimization.
Tutorials
12. After the constraints and controls are fully captured, close the design
implementation window and Optimize the design.

13. Finally, export the design netlist as an EDIF file for ORCA Foundry, and
generate a design report for documentation and review.

For more detailed information, refer to the Synopsys FPGA Express User’s
Guide and Online Help.

FPSC User’s Guide Version 1.2 12-7

ORCA FPSC/FPGA Express Interface
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GO TO ➢ Instantiating the FPSC Module in Verilog

Table of The following code provides a way to instantiate the FPSC Module and other
Contents ORCA library components into a design. Note that the pin order information is
specified in the ORCA library manual.
Index
module FPSC_Test(
// PCI Signals
Cover PciClk, PciRstN, PciAD, PciC_BeN,PciPar,
Page PciFrameN,PciIrdyN,PciTrdyN,PciStopN,PciIdSel,
PciDevSelN,PciReqN,PciGntN,PciPerrN,PciSerrN,
PciIntAN, PciReq64N,PciAck64N,PciPar64,
FPSC
Home // FPGA Signals
FPGA_RSTN,GSR_RESET,
// I/O Test Points
List of FB_MCLK1,FB_RETRYN);
Docs

inout [63:0] PciAD;

FPSC inout [7:0] PciC_BeN;
Tutorials
input PciClk, PciRstN, PciIdSel, PciGntN;
output PciReqN, PciSerrN, PciIntAN;
inout PciPar, PciFrameN, PciIrdyN, PciTrdyN,
PciStopN, PciDevSelN, PciPerrN, PciReq64N,
PciAck64N, PciPar64;
input FPGA_RSTN; // External FPGA(LSR) soft reset

// I/O Test Points

output FB_MCLK1;
output FB_RETRYN;

//Interconnect Busses
wire [17:0] FB_MDATA;
wire [17:0] PCIM_MDATA;
wire [17:0] FB_SDATA;
wire [17:0] PCIM_SDATA;
wire [3:0] PCIM_MWSLICE;
wire [3:0] PCIM_TWSLICE;
wire [1:0] PCIM_MRSLICE;
wire [1:0] PCIM_TRSLICE;

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ORCA FPSC/FPGA Express Interface
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GO TO ➢ // Instantiation of the FPSC core

PCI_INTF PCI_INTF (
Table of .CLK(PciClk), .RSTN(PciRstN),.AD(PciAD),
Contents
.C_BEN(PciC_BeN),.PAR(PciPar),
.FRAMEN(PciFrameN),.IRDYN(PciIrdyN),
Index .TRDYN(PciTrdyN),.STOPN(PciStopN),
.IDSEL(PciIdSel),.DEVSELN(PciDevSelN),
.REQN(PciReqN) ,.GNTN(PciGntN),
Cover
Page .PERRN(PciPerrN),.SERRN(PciSerrN),
.INTAN(PciIntAN),.REQ64N(PciReq64N),
.ACK64N(dummy),.PAR64(dummy1),
FPSC .EJECTSW(PciEjectSW),
Home .ENUMN(PciEnumN),
.LEDN(PciLEDN),
List of .MAENN(FB_ADRFINN),
Docs .MA_FULLN(PCIM_MAFFULLN),
.MWDATAENN(FB_MDATAFINN),
FPSC
.DATAFMFPGAX0(FB_MDATA[16]),
Tutorials .DATAFMFPGAX1(FB_MDATA[17]),
.DATAFMFPGAX2(FB_SDATA[16]),
.DATAFMFPGAX3(FB_MDATA[16]),
.MW_AFULLN(PCIM_MWFFULL_4N),
.MW_FULLN(PCIM_MWFFULLN),
.MSTATECNTR(PCIM_MWSLICE),
.MRDATAENN(FB_MDATAFINN),
.DATATOFPGAX0(PCIM_MDATA[16]),
.DATATOFPGAX1(PCIM_MDATA[17]),
.DATATOFPGAX2(PCIM_SDATA[16]),
.DATATOFPGAX3(PCIM_SDATA[17]),
.MR_EMPTYN(PCIM_MRFEMPTYN),
.MRLASTCYCN(PCIM_MRLASTCYCN),
.MSTATECNTR(PCIM_MRSLICE),
.FIFO_SEL(FB_TW_MR_SEL),
.TAENN(FB_ADRFOUTN),.TREQN(PCIM_REQN),
.TWDATAENN(FB_SDATAFOUTN),
.TW_AEMPTYN(PCIM_SFEMPTY_4N),
.TW_EMPTYN(PCIM_SFEMPTYN),
.TSTATECNTR(PCIM_TWSLICE),
.TWBURSTPENDN(PCIM_WBSTONN),
.TRDATAENN(FB_SDATAFINN),
.TWDATAENN(FB_SDATA),

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ORCA FPSC/FPGA Express Interface
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GO TO ➢ .TR_AFULLN(PCIM_SFFULL_4N),
.TR_FULLN(PCIM_SFFULLN),
Table of .TFIFOCLRN(FB_PCIFFCLRN),
Contents
.MFIFOCLRN(FB_FBFFCLRN),
.TRPCIHOLD(FB_TPCIHOLD),
Index .MWPCIHOLD(FB_MPCIHOLD),
.TRBURSTPENDN(FB_RDDATAAVAILN),
.PCI_INTAN(FB_IRQN),
Cover
Page .FPGA_MBUSYN(FB_BUSYN),
.FPGA_MSYSERROR(PCIM_SYSERROR),
.MCLK(FB_MCLK1),.TCLK(FB_TCLK),
FPSC .PCICLK(PCIM_PCICLK),
Home .FPGA_SYSERROR(FB_SYSERROR),
.M_READY(M_READY),.T_READY(T_READY),
List of .PCI_CFG_STAT(PCIM_CFGSTS_OUT)
Docs );
// Instantiate the FPGA design
FPSC
FPGA_TAR FPGA_TAR(
Tutorials .FB_MCLK1(FB_MCLK1),.FB_BUSYN(FB_BUSYN),
.FB_PCIFFCLRN(FB_PCIFFCLRN),
.FB_FBFFCLRN(FB_FBFFCLRN),
.FB_ADRFINN(FB_ADRFINN),
.FB_ADRFOUTN(FB_ADRFOUTN),
.FB_MDATAFINN(FB_MDATAFINN),
.FB_MDATAFOUTN(FB_MDATAFOUTN),
.FB_SDATAFINN(FB_SDATAFINN),
.FB_SDATAFOUTN(FB_SDATAFOUTN),
......................);

// Reduce the PCI clock /2

CLKCNTLB BMIDTOP (.CLKIN(PCIM_PCICLK),.CLKOUT(PCICLK),
.SHUTOFF(1’b0)
);
FD1P3DX FB_MCLK1_FF (.D(FB_MCLK1_inv),.SP(1’b1), .CK(PCICLK),
.CD(~FPGA_RSTN),.Q(FB_MCLK1)
);
assign FB_MCLK1_inv = ~FB_MCLK1;

endmodule

FPSC User’s Guide Version 1.2 12-10

ORCA FPSC/FPGA Express Interface
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GO TO ➢ Instantiating Components in VHDL

Table of The following code provides a way to instantiate the FPSC Module and other
Contents ORCA library components into a VHDL design. Note that the pin order information
is specified in the ORCA library manual.
Index
library IEEE;
use IEEE.std_logic_1164.all;
Cover
Page entity FPSC_Test is

port( PciClk, PciRstN : in std_logic;

FPSC
Home PciAD: inout std_logic_vector (64 downto 0);
PciC_BeN: inout std_logic_vector (7 downto 0);
PciPar, PciFrameN, PciIrdyN,
List of PciTrdyN, PciStopN: inout std_logic;
Docs
PciIdSel: in std_logic;
PciDevSelN: inout std_logic;
FPSC PciReqN: out std_logic; PciGntN: in std_logic;
Tutorials
PciPerrN: inout std_logic;
PciSerrN, PciIntAN: out std_logic;
PciReq64N, PciAck64N, PciPar64: inout std_logic;
FPGA_RSTN: in std_logic;
FB_MCLK1, FB_RETRYN : out std_logic);

end FPSC_Test;

architecture FPSC_Test_arch of FPSC_Test is

component PCI_INTF
port( CLK, RSTN : in std_logic;
AD : inout std_logic_vector (63 downto 0);
C_BEN : inout std_logic_vector (7 downto 0);
PAR, FRAMEN, IRDYN, TRDYN, STOPN : inout std_logic;
IDSEL : in std_logic; DEVSELN : inout std_logic;
REQN : out std_logic; GNTN : in std_logic;
PERRN: inout std_logic; SERRN, INTAN: out std_logic;
REQ64N, ACK64N, PAR64 : inout std_logic;
EJECTSW: in std_logic; ENUMN, LEDN: out std_logic;
MAENN : in std_logic; MA_FULLN : out std_logic;
MWDATAENN: in std_logic; MW_AFULLN, MW_FULLN: out

FPSC User’s Guide Version 1.2 12-11

ORCA FPSC/FPGA Express Interface
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GO TO ➢ std_logic; MRDATAENN : in std_logic; MR_AEMPTYN,

MR_EMPTYN : out std_logic; FIFO_SEL, TAENN : in
Table of std_logic; TREQN : out std_logic; TWDATAENN:
Contents
in std_logic; DATATOFPGA : out std_logic_vector
(31 downto 0); DATATOFPGAX2, DATATOFPGAX3, DATATOFPGAX0,
Index DATATOFPGAX1 : out std_logic; DATAFMFPGA : in
std_logic_vector (31 downto 0); DATAFMFPGAX2,
DATAFMFPGAX3, DATAFMFPGAX0, DATAFMFPGAX1 : in
Cover
Page std_logic; TW_AEMPTYN, TW_EMPTYN : out std_logic;
TRDATAENN : in std_logic; TR_AFULLN, TR_FULLN : out
std_logic; TFIFOCLRN, MFIFOCLRN, TRPCIHOLD, MWPCIHOLD,
FPSC TRBURSTPENDN : in std_logic; DISCTIMEREXPN : out
Home std_logic; PCI_INTAN, FPGA_MBUSYN : in std_logic;
FPGA_MSYSERROR : out std_logic; FCLK1, FCLK2 : in
List of std_logic; PCICLK, PCI_RSTN : out std_logic;
Docs T_ABORT, MR_STOPBURSTN, T_RETRYN, FPGA_SYSERROR : in
std_logic; M_READY, T_READY, PCI_CFG_STAT : out
FPSC
std_logic; TCMD, MSTATECNTR, TSTATECNTR : out
Tutorials std_logic_vector (3 downto 0); BAR : out
std_logic_vector (2 downto 0); TWLASTCYCN, TRLASTCYCN,
MRLASTCYCN, PCI_64BIT : out std_logic; DELTRN,
MWLASTCYCN, TWBURSTPENDN, CFGSHIFTENN : in std_logic);
end component;

component FPGA_TAR
port( FB_MCLK1: in std_logic; FB_BUSYN, FB_PCIFFCLRN,
FB_FBFFCLRN,FB_ADRFINN, FB_ADRFOUTN, FB_MDATAFINN,
FB_MDATAFOUTN, FB_SDATAFINN,FB_SDATAFOUTN, FB_IRQN,
FB_SYSERROR, FB_TARABORT, FB_RDDATAAVAILN,
FB_RETRYN: out std_logic;
FB_MDATA: out std_logic_vector (17 downto 0);
FB_WBSTONN, FB_STOPTXN: out std_logic;
FB_SDATA: out std_logic_vector (17 downto 0);
FB_TW_MR_SEL, FB_MPCIHOLD,
FB_TPCIHOLD: out std_logic;
PCIM_PCICLK, PCIM_RSTN, PCIM_REQN, PCIM_SYSERROR,
PCIM_DISCTMR_EXPN: in std_logic;
PCIM_MDATA: in std_logic_vector (17 downto 0);
PCIM_MAFFULLN, PCIM_MRFEMPTYN, PCIM_MRFEMPTY_4N,
PCIM_MWFFULLN, PCIM_MWFFULL_4N: in std_logic;
PCIM_SDATA: in std_logic_vector (17 downto 0);

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ORCA FPSC/FPGA Express Interface
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GO TO ➢ PCIM_SFEMPTYN, PCIM_SFEMPTY_4N, PCIM_SFFULLN,

PCIM_SFFULL_4N, PCIM_WBSTONN, PCIM_RDBSTONN,
Table of PCIM_MRDBSTONN: in std_logic;
Contents
PCIM_MWSLICE: in std_logic_vector(3 downto 0);
PCIM_MRSLICE: in std_logic_vector(1 downto 0);
Index PCIM_TWSLICE: in std_logic_vector(3 downto 0);
PCIM_TRSLICE: in std_logic_vector (1 downto 0);
PCIM_CFG_STS_OUT, PCIM_TWFFULLN,
Cover
Page PCIM_TRFEMPTYN, PCIM_MWFEMPTYN, PCIM_MRFFULLN,
T_READY, FPGA_RSTN,PWRUPRST: in std_logic);
end component;
FPSC
Home component CLKCNTLB
port( CLKIN, SHUTOFF: in std_logic;
List of CLKOUT: out std_logic);
Docs end component;

FPSC
component FD1P3DX
Tutorials port( D, SP, CK, CD: in std_logic; Q : out std_logic);
end component;

signal FB_MDATA_17, PCIM_SDATA_17, PCIM_RDBSTONN,

PCICLK_port, FB_SDATA_5, PCIM_MDATA_9, FB_WBSTONN,
PCIM_SDATA_3, FB_SYSERROR, PCIM_SFEMPTYN, FB_MDATA_6,
PCIM_MDATA_15, PCIM_MDATA_0, FB_SDATA_15,
PCIM_TWSLICE_0, FB_FBFFCLRN, PCIM_MDATA_12,
PCIM_MDATA_7, FB_SDATA_12, FB_RDDATAAVAILN: std_logic;

begin

PCI_INTF_INST: PCI_INTF port map( CLK => PciClk,

RSTN => PciRstN, AD => PciAD, C_BEN => PciC_BeN,
FRAMEN => PciFrameN, IRDYN => PciIrdyN, TRDYN =>
PciTrdyN,STOPN => PciStopN, IDSEL => PciIdSel,
DEVSELN => PciDevSelN, REQN => PciReqN, GNTN =>
PciGntN, ..............
);

FPGA_TAR_INST: FPGA_TAR port map( FB_MCLK1 => FB_MCLK1_port,

FB_BUSYN => FB_BUSYN, FB_PCIFFCLRN => FB_PCIFFCLRN,
FB_FBFFCLRN => FB_FBFFCLRN, FB_ADRFINN => FB_ADRFINN,

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ORCA FPSC/FPGA Express Interface
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GO TO ➢ FB_ADRFOUTN => FB_ADRFOUTN, FB_MDATAFINN =>

FB_MDATAFINN, FB_MDATAFOUTN => n127, FB_SDATAFINN =>
Table of FB_SDATAFINN, FB_SDATAFOUTN => FB_SDATAFOUTN,
Contents
FB_IRQN => FB_IRQN, FB_SYSERROR => FB_SYSERROR,
...............
Index );

FB_MCLK1_FF: FD1P3DX port map( D => FB_MCLK1_inv,

Cover
Page SP => X_Logic1_port, CK => PCICLK_port, CD => n_2,
Q => FB_MCLK1_port);
BMIDTOP: CLKCNTLB port map( CLKIN => PCIM_PCICLK,
FPSC SHUTOFF => X_Logic0_port, CLKOUT => PCICLK_port);
Home
end FPSC_Test_arch;
List of
Docs

FPSC
Tutorials

FPSC User’s Guide Version 1.2 12-14

ORCA FPSC/FPGA Express Interface
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GO TO ➢ DESIGN IMPLEMENTATION
Table of
In this step of the design process, the circuit is mapped, placed, and routed using
Contents
the following steps:

Index • Translate Synopsys FPGA Express timing constraints into an ORCA Foundry
preference file.
Cover • Compile the EDIF netlist for ORCA with the ORCA Foundry mapsh tool. (See
Page the section Mapping the Design in the ORCA Foundry Environment.) The
output of the mapping phase is an NCD database, named <design>.ncd,
FPSC
which is submitted to the placer and router (parsh) along with timing
Home preferences.
• The order of execution of the tools are: FPGA Express -> map -> trce -> par
List of -> trce -> epic.
Docs • To analyze the timing of your design, use the trcesh static timing analysis
tool.
FPSC
Tutorials • To interactively edit the physical design, use EPIC.

Figure 2 shows a typical design implementation flow using the ORCA Foundry
tools. For a complete description of how to use the ORCA Foundry design
implementation tools, see the ORCA Foundry User's Guide and the EPIC User's
Guide.

Figure 2. Design Implementation

.ngd
ORCA Foundry (Logical Generic
Description) File

Technology
Mapping

Interactive Preferences Timing

Editor Device-Specific Analysis
Design Files

Place and
Route

.ncd
(Circuit Description)
File

FPSC User’s Guide Version 1.2 12-15

ORCA FPSC/FPGA Express Interface
 Last Link Previous Next

GO TO ➢ THE ORCA FOUNDRY ENVIRONMENT

Table of
Contents This section discusses the method for reading Synopsys FPGA Express-created
EDIF designs into the ORCA Foundry design environment. It addresses only the
process of mapping a Synopsys EDIF netlist into a Circuit Description (.ncd) file.
Index Once the design is represented as an .ncd, the full complement of the ORCA
Foundry tools may operate on it. This includes providing detailed static timing
Cover analysis of the design and creating a physical implementation of the design using
Page timing driven PAR and bitgen.

FPSC Mapping the Design

Home
Each of the ORCA Foundry tools may be run from either the command line or
from within a dialog box. The following discussion identifies the operation of the
List of MAP Shell dialog box in mapping the Synopsys-created .edn into the ORCA
Docs Foundry .ncd design files.

FPSC 1. Invoke the MAP Shell dialog box by entering the command mapsh on the
Tutorials UNIX command line. For a complete description of how to use the MAP Shell
dialog box, see the chapter MAPPING A DESIGN in the ORCA Foundry
User's Guide.

2. Enter the name(s) of the design(s) to be mapped in the Input Files List. The
top level of a hierarchical design must be the first file in the list.

3. Push the Options button to select the FPSC target device: Architecture:
or3tfpsc; Device: or3txx2; Package: <select targeted package>, Speed:
<select targeted speed grade>.

4. Use the Preference File text field to specify a previously created preference
file (perhaps containing I/O specifications) for the design.

5. Press the OK button in the MAP Options dialog box to accept its configuration
and return to the MAP Shell dialog box.

6. On the MAP Shell dialog box, press the OK button to begin the mapping
operation.

FPSC User’s Guide Version 1.2 12-16

ORCA FPSC/FPGA Express Interface
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GO TO ➢ The MAP shell creates a script file (output_filename.msc) which is run (and may
be later modified and rerun). Next, the NGDBUILD operation creates the generic
Table of database (.ngd) design file, which contains the fully expanded design. Finally, the
Contents
MAP program is run to create the circuit description (.ncd) file, which represents
the mapped physical FPGA design.
Index
The timing constraints which are contained within the Preference File are written
into the .ngo files as Preference Language preferences. These constraints are
Cover
Page then written into the .prf preference file during the technology mapping operation.

The next step in the process is to run TRACE on the mapped design to get an
FPSC estimate of the logic delays, number of logic levels, and the critical paths.
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For additional information on how to run the other ORCA Foundry tools, please
List of refer to the appropriateORCA Foundry Users Guide chapters on the Preference
Docs Language, TRACE, and PAR. A list of related documents is provided at the
beginning of this chapter.
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GO TO ➢ DESIGN VERIFICATION
Table of
Design verification involves three operations:
Contents
• (Optional) Using a standard supported simulator to perform full timing
simulation of the Verilog, VHDL, or EDIF output file generated by ORCA
Index
Foundry. Currently, we support Model Technology V-System and Synopsys
VSS simulators for VITAL (VHDL) simulations, Cadence Verilog-XL for
Cover Verilog simulations, and Viewlogic Viewsim for EDIF simulations.
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• Producing a data bitstream (using BITGEN) that will be written into the device.
• Physically loading the configuration data into the device.
FPSC
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For a complete description of how to use the ORCA Foundry design verification
tools, see the ORCA Foundry User's Guide and the appropriate simulator
List of interface and reference manuals.
Docs

FPSC
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