Registo e Maquina Estados Verilog

Registers and finite state machines
DAPA E.T.S.I. Informtica Universidad de Sevilla 11/2012

Jorge Juan <jjchico@dte.us.es> 2010, 2011, 2012 You are free to copy, distribute and communicate this work publicly and make derivative work provided you cite the source and respect the conditions of the Attribution-Share alike license from Creative Commons. You can read the complete license at: http://creativecommons.org/licenses/by-sa/3.0
Departamento de Tecnologa Electrnica Universidad de Sevilla
Contents

Introduction Flip-flops Registers Counters Finite state machines
Introduction
Design a garage door control system with two push buttons (no switches) separated by a distance:

x: open the door y: close the door
open (x) door (z) close (y)
Asynchronous SR latch
R=S=0 the state is preserved

0 S
q
0 R
q 0
0 R
q 1
S=1, R=0 change to 1 (set)

1
S
S=0, R=1 change to 0 (reset)

0 S
q
q 0
0 R
q 1
1 R
SR Latch. Formal description

Symbol State table
SR q
S q
State diagram
SR=10
11 10
00
01
SR=0x
SR=x0
0 1
0 1
0 0
Q
1 1
q=0
SR=01
q=1
Verilog
S q
Excitation table qQ SR 0x 10 01 x0
module sra( input s, input r, output reg q); always @(s, r) case ({s, r}) 2'b01: q = 1'b0; 2'b10: q = 1'b1; 2'b11: q = 1'bx; endcase endmodule
00 0 1 10 11
Synchronous latches
In real circuits with thousands or million latches, it is very useful to control the state change so that it happens in all devices at the same time. State change is synchronized to a clock signal (CK) Gated latches
State change is only allowed when CK is either high (1) or low (0). State change is only allowed at the instant CK changes from 0 to 1 (positive edge) or from 1 to 0 (negative edge) State change is more precisely determined. Make more robust and easy to design circuits
Edge-triggered latches (flip-flops)

Synchronous latches
Gated latch
module srl( input ck, input s, input r, output reg q);
Flip-flop
S R q
module srff( input ck, input s, input r, output reg q);
S Rck
ck
always @(ck, s, r) if (ck == 1) case ({s, r}) 2'b01: q = 1'b0; 2'b10: q = 1'b1; 2'b11: q = 1'bx; endcase endmodule
always @(negedge ck) case ({s, r}) 2'b01: q = 1'b0; 2'b10: q = 1'b1; 2'b11: q = 1'bx; endcase endmodule
State change when ck=1
State changes when ck changes from 1 to 0
Other flip-flops

SR JK

Similar to SR: J~S, K~R Toggle (reverse) function for J=K=1 A single input equal to the next state Easy to use and implement A single input to toggle the state Very useful in some special applications: counters
D flip-flop
Synbols State table
D q
q D ck
State diagram
D=1 D=0 D=1
0 1
0 0
Q
1 1
q=0
D=0
q=1
Excitation table
q D ck
Verilog D 0 1 0 1
module dff( input ck, input d, output reg q); always @(negedge ck) q <= d; endmodule
qQ
q
00 01 10 11
Asynchronous inputs
Easy way to force a given state

CL J K q
CL (clear): set to 0 PR (preset): set to 1 Active low (0) Active high (1)
Immediate effect after activation:

ck
Higher priority than synchronous inputs
PR D ck q
J, K, D, T, ...
Solution to the problem of initiating the state in complex digital systems

Million of flip-flops Need to start from a known state
CL T
PR q
ck
Timing
Synchronous inputs should not change close to the active edge of the clock signal to avoid an unpredictable state change. Set-up time (ts)
Time before the active edge in which inputs should not change. Time after the active edge in which inputs should not change.
Hold time (th)
Timing
ts CK Q=1 Q=X D Q=X Q=0 th
D ck q
Contents

Registers
1 0 0 1 0 1 1 0
n-bit storage element (n flip-flops)
Content is expressed from the data it represents: number (in hex or decimal), character, etc. Write (load): stored data modification. Read: access to the content of the register.
Basic operations:

Registers. Classification
Parallel input

All the bits can be written (loaded) at the same time (with the same clock event). There is one load input signal for each stored bit. Only one bit can be written at each clock cycle. A single input signal for all the stored bits. All the bits can be read at the same time. One output signal for each stored bit. Only one bit can be read at each clock cycle. A single output signal for all the stored bits.
Serial input

Parallel output

Serial output

Registers. Classification
parallel-in/parallel-out parallel-in/serial-out
1 0 0 1 0 1 1 0
1 0 0 1 0 1 1 0
serial-in/parallel-out
serial-in/serial-out
1 0 0 1 0 1 1 0
1 0 0 1 0 1 1 0
Parallel-in/parallel-out register
x
x3 CL LD CK z3 z2 z1 z0 x2 x1 x0
Verilog code
module reg( input ck, input cl, input ld, input [3:0] x, output [3:0] z ); reg [3:0] q; always @(posedge ck, negedge cl) if (cl == 0) q <= 0; else if (ld == 1) q <= x; assign z = q; endmodule
REG
Operation table CL, LD 0x 11 10 Operation q0 qx qq Type async. sync. sync.
x3 CL LD CK z3 z2 z1 z0 x2 x1 x0
Asynchronous operation table

CL Operation q0 qq Typ. stage Qi = 0 Qi = qi Excit. CLi = 0 CLi = 1 0 1
REG
Synchronous operation table

LD 1 0 Operation qx qq Typ. stage Q i = xi Qi = qi
CL
Excit. Di = x i D i = qi
C.C.
qi 0 Di 1
CLi
qi zi
control data state
C.C.
flip-flop
qi
xi
LD
zi
CK
x3 CL LD CK z3 x3 x2 z2 z1 x1 z0 x0 x2 x1 x0
REG
CL
CL
0 D3 1 1 q3 0 D2
CL
q2 0 D1 1
CL
q1 0 D0 1
CL
q0
LD CK z3 z2 z1 z0
Shift register
xL CL EN CK zL
Verilog code
module reg_shl( input ck, input cl, input en, input xl, output zl ); reg [3:0] q;
REG
Operation table CL, EN 0x 11 10 Operation q0 q SHL(q) qq Type async. sync. sync.
always @(posedge ck, negedge cl) if (cl == 0) q <= 0; else if (en == 1) q <= {q[2:0], xl}; assign zl = q[3]; endmodule
Shift register
xL CL EN CK zL
Synchronous operation table

EN Operacin q SHL(q) qq Et. tpica Qi = qi-1 Qi = qi Et. 0 Q0 = xL Q0 = q0 Ex. tp. Di = qi-1 Di = qi Ex. et. 0 D0 = x L D0 = q 0 1 0
REG
CL
C.C.
qi 0 Di 1
CLi
qi
control data state
C.C.
flip-flop
qi
qi-1
EN
zi
CK
Shift register
xL CL EN CK zL xL
REG
CL
CL
0 D0 1 1 q0 0 D1
CL
q1 0 D2 1
CL
q2 0 D3 1
CL
q3
EN CK zL
Contents

Counters

Introduction Registers Counters

Binary up counter modulus 2n Count limiting Down counter Up/down counter Non-binary counters
Design with sequential subsystems
Counters

Similar to the register: adds count operation Design

Modular design principles Easier implementation with T or JK flip-flops (simplified count operation). Up counting Down counting Reset (clear) Count state loading Count state Count end: counter in the last count value.
Typical operations

Typical output

Binary modulus 2n up counter
Modulus
Number of counter states Consecutive base-2 numbers Counts from 0 to 2n-1 (n bits) First count state follows last count state (overflow)
Binary
Modulus 2n
Cyclic count
Binary modulus 2n up counter

Verilog code
CL
COUNT
CK z3 z2 z1 z0
module count_mod16( input ck, input cl, output [3:0] z ); reg [3:0] q; always @(posedge ck, posedge cl) if (cl == 1) q <= 0; else q <= q + 1;
Operation table CL 1 0 Operation q0 q q+1|mod 16 Type async. sync.
assign z = q; endmodule
Binary modulus 2n up counter Count operation
CK q0 q1 q2 q3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Binary modulus 2n up counter with clear and enable inputs

Verilog code
CL EN CK z3 z2 z1 z0
COUNT
module count_mod16( input ck, input cl, input en, output [3:0] z ); reg [3:0] q; always @(posedge ck) if (cl == 1) q <= 0; else if (en == 1) q <= q + 1;
Operation table CL, EN 1x 01 00 Operation q0 q q+1|mod 16 qq Type sync. sync. sync.
assign z = q; endmodule
End-of-count output
Verilog code
COUNT
module count_mod16( input ck, input cl, input en, output [3:0] z, output c ); reg [3:0] q; always @(posedge ck) if (cl == 1) q <= 0; else if (en == 1) q <= q + 1; assign z = q; assign c = &q; endmodule
Binary modulus 2n up counter with load and enable inputs

x3 x2 x1 x0
Verilog code
module count_mod16( input ck, input ld, input en, input [3:0] x, output [3:0] z ); reg [3:0] q; always @(posedge ck) if (ld == 1) q <= x; else if (en == 1) q <= q + 1; assign z = q; endmodule
LD EN CK
COUNT
z3
z2
z1
z0
Operation table LD, EN 1x 01 00 Operation qx q q+1|mod 16 qq Tipo sync. sync. sync.
Count limiting. BCD counter

Verilog code BCD COUNT (0-9)
z3 z2 z1 z0
EN CK
module count_mod10( input ck, input cl, input en, output [3:0] z, ); reg [3:0] q; always @(posedge ck) if (cl == 1) q <= 0; else if (en == 1) if (q == 9) q <= 0; else q <= q + 1; assign z = q; endmodule
Operation table CL, EN 1x 01 00 Operation q0 q q+1|mod 10 qq Type sync. sync. sync.
Modulus 2n down counter with clear, enable and borrow

Verilog code
COUNT
module count_mod16( input ck, input cl, input en, output [3:0] z, output b c ); reg [3:0] q; always @(posedge ck) if (cl == 1) q <= 0; else if (en == 1) q <= q + 1; assign z = q; assign b c = &~q; &q; endmodule
Operation table CL, EN 1x 01 00 Operation q0 q q-1|mod 16 qq Type sync. sync. sync.
Up/down counter
CL EN UD CK z3 z2 z1 z0
COUNT
Operation table
CL, EN, UD
Operation q0 qq q q+1|mod 16 q q-1|mod 16
Type async. sync. sync. sync.
1xx 00x 010 011
Up/down counter
Verilog code
module rev_counter1( input ck, input cl, input en, input ud, output [3:0] z, output c ); reg [3:0] q; always @(posedge ck, posedge cl) begin if (cl == 1) q <= 0; else if (en == 1) if (ud == 0) q <= q + 1; else q <= q - 1; end assign z = q; assign c = ud ? ~(|q) : &q; endmodule assign z = q; endmodule
Verilog code
module rev_counter2( input ck, input cl, input en, input ud, output [3:0] z, output c ); reg [3:0] q; reg c; always @(posedge ck, posedge cl) begin if (cl) q <= 0; else if (en) if (!ud) q <= q + 1; else q <= q - 1; end always @* if (ud) c = ~(|q); else c = &q;
Ring counter
z3 z2 z1 z0 1000
CK
0 0 1 0
0100 0010 0001 1000 ...
START
PR
q3 D3 D2
CL
q2 D1
CL
q1 D0
CL
q0
CK
z3
z2
z1
z0
Sequence generator
0011 sequence generator with shift register.
CK
1 1 0 0
z
START
PR
q3 D3 D3
PR
q3 D3
CL
q3 D3
CL
q3 z
CK
Sequence generator
With counter and C.C.

START CL
Verilog code
module seq_gen( input ck, input start, output z ); reg [1:0] q; reg z;
COUNT
CK
C.C.
always @(posedge ck) if (start == 1) q <= 0; else q <= q + 1;

0 0 1 z 1 1 2 3
1 0
START
CL
COUNT
CK q1 q0
case (q) 2'h0: z 2'h1: z 2'h2: z 2'h3: z endcase endmodule
= = = =
1'b0; 1'b0; 1'b1; 1'b1;
Example: de-bouncer and edge detector

y x de-bouncer edge detector z
x y z
Example: 7S controller
AN D0 D1 A D[3:0] D2 D3 F G B BCD/7S A B C D E F G seg[1:7]
D3D2D1D0
0000
D
0 1 2 3 4 5 6 7 8 9
seg[1:7] ABCDEFG
0000001 1001111 0010010 0000110 1001100 0100100 0100000 0001111 0000000 0001100
0001 0011 0010 0110 0111 0101 0100 1100 1101
A B C D E F G
AN should be '0' for the device to work.
Example: 7S controller
4 X0 X1 X2 X3 CK AN0 AN1 AN2 AN3 7 7S
Refresh period AN0 AN1 AN2 AN3
CK: 50MHz Refresh frequency: 100Hz - 1KHz
Contents

Finite State Machines (FSM)

x1 x2 x3 x4 x5 ... z1 z2 z3 z4 z5 ...
x ,
q state S1 S2 S3 S4 ...
Q = (q, x) z = (q, x)
Finite State Machine properties
Starting at the same state, deterministic FSM's always generate the same output sequence for the same input sequence. Two FSM's are equivalent if they generate the same output sequence for the same input sequence. FSM's can be optimized: an equivalent FSM with a reduced number of states. The state of the machine changes depending on the input sequence so the state represents the whole set of old input symbols (history of the machine) FSM's may not be completely specified: a next state may not be defined for a given current state and input value.
Synchronous Sequential Circuits (SSC)
FSM's are an excellent tool to model digital circuits with memory. Digital circuits with memory elements (latches) are an excellent technology to implement FSM's:

Inputs/outputs: digital signals of one or more bits. State: n-bit word stored in latches Next state function: combinational functions that are applied to the inputs of the latches. Output function: combinational function.
Synchronous sequential circuits are digital circuits that implement finite state machines by using combinational circuits and latches. For practical reasons, the state change is controlled by a clock signal: edge-triggered flip-flops are normally used.
Synchronous Sequential Circuits (SSC)

x , z x C.C. z
q state
q flip-flops
Mealy x Q q
flip-flops
Formal representations

State diagrams State tables
Example 1: barrier control x=1: open y=1: close z: door control (0: close, 1: open)
Example 2: single-input barrier control x=1 one cycle: open x=1 two cycles: close z: door control (0: close, 1: open)
State diagram. Mealy
Nodes
1/0 1/0
0/0
Represent states. State names are more or less intuitive. E.g. {A, B, C, ...}, {S0, S1, S2, ...}, {wait, start, receiving, ...} Represent possible state transitions from every state (S). Named as x/z, where:
Arcs
A
0/0
1/0 1/1
0/0
0/0
x: input value that triggers the transition from state S. z: output value of the machine when in state S and input is x.
State table. Mealy
Double input table (rows and columns) with information equivalent to the states diagram.

Rows: possible states. Columns: possible input values. In each cell: corresponding next state and output.
Each node in the diagram and the arcs starting at that node correspond to a row in the states table. Converting a states diagram to a states table and vice-versa is trivial.
State table. Mealy

x S 0 1
1/0 1/0
0/0
A B
A,0 C,0 D,0 A,0
B,0 A,0 B,0 B,1

Q,z
A
0/0
1/0 1/1
C D
0/0
0/0
State diagram. Moore

1 1 0
Nodes
B/0
1 1
A/0
0
C/0
E/1
0
Represent states. State names are more or less intuitive. E.g. {A, B, C, ...}, {S0, S1, S2, ...}, {wait, start, receiving, } Each node includes the output value corresponding to each state. Represent possible state transitions from every state (S). Named as x: input value that triggers the transition from state S.
D/0
Arcs

State table. Moore
Double input table (rows and columns) with information equivalent to the states diagram.

Rows: possible states. Columns: possible input values. Output associated to every state in last column. Optionally, output value in each cell like Mealy. Same output for every input value.
Each node in the diagram and the arcs starting at that node correspond to a row in the states table. Converting a states diagram to a states table and vice-versa is trivial.
State table. Moore

x S
1 1 0
z 0 0 0 0 1
B/0
1 1
A B
A C D A A
Q
B A B E B
A/0
0
C/0
C D
E/1
0
D/0
Applications of the SSC
Sequence detectors
Output activates only when a given sequence of symbols arrive to the input. The output generates a fixed sequence of symbols, or a variable one depending on the input. The inputs modify the state and the state defines an actuation over an external system: barrier control, temperature control, presence control, liquid level control, etc. The output sequence is the result of applying some operation to the input sequence: parity calculation, sequential arithmetic operations, sequential coding/decoding, etc.
Sequence generators
Control units
Sequential processing
FSM design objective
Objective

Define a FSM that solves a given problem. Implement the FSM using a synchronous sequential circuits. Various cost criteria drive the design process
Cost
Minimizing the number of memory elements Minimizing the number of devices Operation frequency Energy consumption ...
Need to compromise different criteria
Design processes
Hand process

Can be done with paper and pencil. Starts with a description of the problem using a state diagram or a state table. The states table is transformed in different steps to lead to a circuit representation. The problem is translated to a formal description using a hardware description language. Simulation tools are used to check that the operation of the described system is correct. Automatic synthesis tools are used to implement the actual circuit.
Design process using Computer Aided Design (CAD) tools

Design process using CAD tools

Word description of the problem
Translation
State diagram
LDH description
Translation
Test bench
Simulation
no
ok?
yes
Automatic synthesis
Circuit
Configuration
Verilog FSM descriptions

Mealy x Q flip-flops q // State change process (sequential) always @(posedge ck, posedge reset) if (reset) state <= A; else state <= next_state; // Next state calculation process // (combinational) always @* begin case (state) A: next_state = . . .; B: next_state = . . .; . . . endcase end // Output calculation process // (combinational) always @* begin z = . . .; end z
Three processes

State change: represents the flip-flop block. Next state calculation: excitation equations () Output calculation: output equations ().
Only the state change process is sequential (includes memory elements)
Verilog FSM. Example

x ck reset z
See Verilog course
1/0 1/0
1 0/0 1 0
B/0
1 1
A
0/0
1/0 1/1
A/0
0
C/0
E/1
0
0/0
0/0
D/0
Other FSM design styles

Mealy x Q flip-flops q

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Registers and finite state machines

DAPA E.T.S.I. Informtica Universidad de Sevilla 11/2012

Departamento de Tecnologa Electrnica Universidad de Sevilla

Introduction Flip-flops Registers Counters Finite state machines

Departamento de Tecnologa Electrnica Universidad de Sevilla

x: open the door y: close the door

open (x) door (z) close (y)

Departamento de Tecnologa Electrnica Universidad de Sevilla

R=S=0 the state is preserved

S=1, R=0 change to 1 (set)

S=0, R=1 change to 0 (reset)

Departamento de Tecnologa Electrnica Universidad de Sevilla

SR Latch. Formal description

Departamento de Tecnologa Electrnica Universidad de Sevilla

Edge-triggered latches (flip-flops)

Departamento de Tecnologa Electrnica Universidad de Sevilla

State change when ck=1

State changes when ck changes from 1 to 0

Departamento de Tecnologa Electrnica Universidad de Sevilla

Departamento de Tecnologa Electrnica Universidad de Sevilla

Departamento de Tecnologa Electrnica Universidad de Sevilla

Easy way to force a given state

Immediate effect after activation:

Higher priority than synchronous inputs

Solution to the problem of initiating the state in complex digital systems

Million of flip-flops Need to start from a known state

Departamento de Tecnologa Electrnica Universidad de Sevilla

Hold time (th)

Departamento de Tecnologa Electrnica Universidad de Sevilla

Departamento de Tecnologa Electrnica Universidad de Sevilla

Introduction Flip-flops Registers Counters Finite state machines

Departamento de Tecnologa Electrnica Universidad de Sevilla

n-bit storage element (n flip-flops)

Departamento de Tecnologa Electrnica Universidad de Sevilla

Departamento de Tecnologa Electrnica Universidad de Sevilla

Departamento de Tecnologa Electrnica Universidad de Sevilla

Operation table CL, LD 0x 11 10 Operation q0 qx qq Type async. sync. sync.

Departamento de Tecnologa Electrnica Universidad de Sevilla

Asynchronous operation table

Synchronous operation table

control data state

Departamento de Tecnologa Electrnica Universidad de Sevilla

Departamento de Tecnologa Electrnica Universidad de Sevilla

Operation table CL, EN 0x 11 10 Operation q0 q SHL(q) qq Type async. sync. sync.

Departamento de Tecnologa Electrnica Universidad de Sevilla

Synchronous operation table

control data state

Departamento de Tecnologa Electrnica Universidad de Sevilla

Departamento de Tecnologa Electrnica Universidad de Sevilla

Introduction Flip-flops Registers Counters Finite state machines

Departamento de Tecnologa Electrnica Universidad de Sevilla

Introduction Registers Counters

Design with sequential subsystems

Departamento de Tecnologa Electrnica Universidad de Sevilla

Similar to the register: adds count operation Design

Departamento de Tecnologa Electrnica Universidad de Sevilla

Binary modulus 2n up counter

Departamento de Tecnologa Electrnica Universidad de Sevilla

Binary modulus 2n up counter

Operation table CL 1 0 Operation q0 q q+1|mod 16 Type async. sync.

Departamento de Tecnologa Electrnica Universidad de Sevilla

Binary modulus 2n up counter Count operation

Departamento de Tecnologa Electrnica Universidad de Sevilla