27/12/12

Universal Asynchronous Receiver UAR

Universal Asynchronous Receiver (UAR)

Many thanks to Gerard Blair at the University of Edinburgh for allow ing us to use his UAR model for February's Model of the Month. Gerard's home page is http://w w w .ee.ed.ac.uk/~gerard/. If you have a model that you are w illing to have advertised on these pages, please drop us a line by clicking here. OK, on w ith this month's Model...

The above figure show s a simplified picture of an asynchronous serial interface of the type commonly used to transfer data in computer and communications systems. The data transfer is referred to as `asynchronous' because the spacing betw een the characters may be of any length. In contrast, the timing of the bits w ithin the character is w ell defined (and is related to the baud rate of the interface). The Tx clock and Rx clock signals are nominally of the same frequency, but are generated locally at each end of the transmission link and therefore cannot be assumed to be locked' together. The design of a suitable transmitter circuit is not difficult, but the receiver must be able to detect the start of an incoming character and then store the value of each data bit, despite the fact that the relative frequency and phase of the Tx and Rx clocks may vary.

As show n in the data diagram above, the beginning and end of each character is delimited by a start bit w hose value is alw ays 0, and a stop bit w hose value is alw ays 1. In betw een characters, the transmitter outputs a constant value of 1. In operation, the receiver continually samples the input data. Follow ing a 1 -> 0 data input transition, the eight data bits must be stored, and this is w here a problem may occur, since for maximum reliability w e w ish to sample the data bits in the centre of their bit times and not close to either edge, so that small differences betw een the Tx and Rx clocks can be accommodated. This may be accomplished by using an Rx clock frequency w hich is a multiple of the data bit rate. In this exercise w e shall assume that the Rx clock signal is eight times the bit rate.
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Universal Asynchronous Receiver UAR

Follow ing the detection of a start bit, the stop bit should be detected 76 clock cycles later. If so, the Data Available output is set high; if not, the Framing Error output is set. Both status outputs are reset low by the detection of the next start bit. There is thought to be a danger of spikes on the communication channel falsely starting the receiver. This means that a momentary LOW on the input to the receiver w ould be seen as a one-to-zero transition w here-as it is really just noise. To counter this, the specification is changed as follow s: The start bit is a one-to zero transition w here the input signal is still zero four (or three or five) samples later. Thus you w ill have to update your design for detectng a valid start bit. Note:- the flexibility of 3-4-5 clock periods is to allow you to implement w hichever is simplest - BUT there is no definition of w hat value is on the input at the sample AFTER the one-to-zero transition: this is to avoid problems associated w ith signal bounce. Well, that's the specification for a UAR model. Here is a design based on sound synchronous design principles. The follow ing Verilog code has five major sub-modules: a start detector w hich deals w ith recognizing the beginning of a new data frame. This sends a signal to set the... control module into run mode. A counter generates a pulse every 8 bits to input the data (thus sampled in the middle of the valid period) serially into a... serial-parallel shift register. On the last bit of the data frame, the shift register is not updated, but rather the.. flags are set according to the value of the stop bit. As w ith all good synchronous modules, a global_reset signal is included so that the registers can be put into a know n state at the start of testing. You are w elcome to use the source code w e provide but you must keep the copyright notice w ith the code (see the Notices page for details). / /U n i v e r s a lA s y n c h r o n o u sR e c e i v e r / / / /+ + / /| L i b r a r y:D a t a c o m m s | / /| d e s i g n e r:G e r a r dB l a i r | / /| o p e n e d :0 3F e b1 9 9 7 | / /+ + / /A r c h i t e c t u r e s : / / 0 3 . 0 2 . 9 7u a r / /S t a r td e t e c t i o n m o d u l es t a r t _ d e t e c t( v a l i d ,c l k ,r e s e t ,g l _ r e s e t ,d I n ) ; o u t p u t v a l i d ; i n p u t c l k ,r e s e t ,g l _ r e s e t ,d I n ; r e g [ 3 : 0 ]s h i f t _ r e g ; a l w a y s@( p o s e d g ec l k )b e g i n i f( r e s e t|g l _ r e s e t ) s h i f t _ r e g=0 ; e l s e s h i f t _ r e g={s h i f t _ r e g [ 2 : 0 ] ,d I n} ; e n d a s s i g nv a l i d=( s h i f t _ r e g[ 0 ]= =0 )& ( s h i f t _ r e g[ 2 ]= =0 )& ( s h i f t _ r e g[ 3 ]= =1 ) ; e n d m o d u l e / /c o n t r o l l e r m o d u l ec o u n t e r( c o u n t 7 2 ,c o u n t 8 ,c l k ,e n a b l e ) ; o u t p u t c o u n t 7 2 ,c o u n t 8 ; i n p u t c l k ,e n a b l e ; w i r e e a c h 8 ; r e g [ 8 : 0 ]c o u n t _ r e g ; a l w a y s@( p o s e d g ec l k ) i f( e n a b l e= =0 ) c o u n t _ r e g< =0 ; e l s eb e g i n c o u n t _ r e g< =c o u n t _ r e g+1 ; e n d
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Universal Asynchronous Receiver UAR

a s s i g ne a c h 8 =( ( c o u n t _ r e g%8 )= =7 ) ; a s s i g nc o u n t 7 2=( c o u n t _ r e g= =7 1 ) ; a s s i g nc o u n t 8 =e a c h 8&~ c o u n t 7 2 ; e n d m o d u l e / /s e r i a lp a r a l l e lc o n v e r t e r m o d u l es e r _ p a r _ c o n v( d O u t ,c l k ,e n a b l e ,d I n ) ; o u t p u t[ 7 : 0 ]d O u t ; i n p u t c l k ,e n a b l e ,d I n ; r e g [ 7 : 0 ]d O u t ; a l w a y s@( p o s e d g ec l k ) i f( e n a b l e= =1 ) d O u t={ d I n ,d O u t [ 7 : 1 ] } ; e n d m o d u l e / /f l a g sf o rr e a d ya n dd a t ae r r o r m o d u l ef l a g s( d R e a d y ,d E r r o r , c l k ,s e t , r e s e t ,d I n ) ; o u t p u td R e a d y ,d E r r o r ; i n p u t c l k ,s e t , r e s e t ,d I n ; r e g d R e a d y ,d E r r o r ; a l w a y s@ ( p o s e d g ec l k ) i f( r e s e t= =1 )b e g i n d R e a d y=0 ; d E r r o r=0 ; e n d e l s ei f( s e t= =1 )b e g i n d R e a d y< =d I n ; d E r r o r< =~ d I n ; e n d i n i t i a l$ m o n i t o r ( " d R e a d y% b% b " ,d R e a d y ,d E r r o r ,$ t i m e ) ; e n d m o d u l e / /g e n e r a t i n gt h er u ns i g n a l s m o d u l ec o n t r o l( r u n n i n g ,c l k ,r e s e t ,g l _ r e s e t ,s e t ) ; o u t p u tr u n n i n g ; i n p u t c l k ,r e s e t ,g l _ r e s e t ,s e t ; r e g r u n n i n g ; a l w a y s@( p o s e d g ec l k ) i f( ( r e s e t= =1 )|( g l _ r e s e t= =1 ) ) r u n n i n g = 0 ; e l s ei f( s e t= =1 ) r u n n i n g=1 ; e n d m o d u l e / /o v e r a l lr e c e i v e rd e f i n i t i o n m o d u l eu a r( d O u t ,d R e a d y ,d E r r o r ,c l k ,g l _ r e s e t ,d I n ) ; o u t p u t[ 7 : 0 ]d O u t ; o u t p u t d R e a d y ,d E r r o r ; i n p u t c l k ,g l _ r e s e t ,d I n ; w i r e r u n n i n g ,f i n i s h ,c o u n t 8 ,s t a r t ;

s t a r t _ d e t e c ts _ d( s t a r t ,c l k ,r u n n i n g ,g l _ r e s e t ,d I n ) ; c o u n t e r c o v( f i n i s h ,c o u n t 8 ,c l k ,r u n n i n g ) ; s e r _ p a r _ c o n vs _ p( d O u t ,c l k ,c o u n t 8 ,d I n ) ;
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Universal Asynchronous Receiver UAR

f l a g s c o n t r o l e n d m o d u l e

f l a( d R e a d y ,d E r r o r ,c l k ,f i n i s h ,s t a r t ,d I n ) ; c o n( r u n n i n g ,c l k ,f i n i s h ,g l _ r e s e t ,s t a r t ) ;

To dow nload the Verilog source code for this month's Model of the Month, click here. Your e-mail comments are w elcome - send email Copyright 2005-2012 Doulos. All rights reserved.

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