JOURNAL OF TELECOMMUNICATIONS, VOLUME 19, ISSUE 1, MARCH 2013 1

A High Gain, Fully Differential Single Stage Folded Cascade Op-amp with 1GHZ Bandwidth
L. Bagheriye, M. Yargholi, S. Toofan and M. Safari
Abstract This paper presents the design of a single stage, fully differential operational amplifier with high gain and large unity gain bandwidth. A folding cascode topology with two gain boosting auxiliary amplifiers is designed in 0.18m CMOS processing technology. This Op-amp is ideally suited for gain stages in A/D converters like pipeline ADCs which applied high resolution MDACs. With 6bit MDAC resolution, the op-amp shows a closed loop gain of 32 and high output swing of 1.2 Vp-p from 1.8V supply voltage. Simulations depict a unity gain bandwidth of 1.13GHz and a DC gain of 75dB, with 2 pF load capacitor. Index Terms Folded cascode, Gain boosting, Fully differential op-amp, Pipeline ADC.

1 INTRODUCTION

witched-Capacitor circuits are widely used in highly integrated, mixed signal applications. In these circuits, op-amps are configured either as the sample-and-hold (S/H), gain stage, integrator and comparator. From these elements more complex circuits can be built such as fil- ters, digital-to-analog converters (DAC), and analog-to- digital converters (ADC) [1]. In the pipeline ADC archi- tecture, the operational amplifier, forming the core of a switched capacitor multiplying D/A converter (SC- MDAC), is the most critical block. The resolution and speed of the whole ADC is usually determined by the operational amplifiers of the MDAC. In general, the am- plifiers open loop DC-gain limits the settling accuracy of the amplifier output, while the bandwidth and slew rate of the amplifier determine the maximal clock frequency of the ADC. In large resolution MDACs (4b and more) op amps must provide high gain and high bandwidth to work properly in ADC structure [2], [3]. With aggressive device scaling in modern CMOS technology, and low supply voltages, designing of high performance op-amps become more challenging. Various op-amp topologies are implemented in ADC structures, such as telescopic, folded cascode, regulated cascade (gain boosting) and two-stage op amps. Telescopic amplifiers have a simple architecture, good bandwidth characteristics and high voltage gain in one stage. The drawback of these topologies, especially with low supply voltage, is a limited signal swing. Folded cascode amplifiers can get extra voltage swing higher than a tele-

scopic one, because of no consuming of headroom in tail current source. The folded cascode exhibits more noise (more transistors incorporate in input noise, i.e. input pairs and current mirror of cascode stage in the folding node) [4] and lower phase margin due to larger parasitic capacitances at the folding nodes. In telescopic and folded cascode op-amps the out- put impedance and hence the gain can be increased by stacking more devices, but at the cost of reduced output swings [6]. To achieving both high gain and high output swing there are two alternative op amp structures, two- stage and regulated cascode op-amps. In two-stage ampli- fiers as shown in Fig. 1, the first stage provide a high gain and the second stage is designed for high output swing. But the drawbacks of these architectures are more power consumption (contribution of two stages) and the non- dominant pole formed by the output impedances of A1 and the load capacitances. Regulated cascode topologies have fewer numbers of cas- code transistors and it's suitable for low voltage designs. But this topology needs modern control systems, as dis- cusses in the next part. The op-amp introduced in this paper is a folded cascode amplifier with two gain boosting auxiliary amplifiers. Section II discusses the circuit topology, and design pro- cess is given in Section III. Section IV gives the simulation results, and finally Section V includes the conclusion. L. Bagheriye is a Msc. student with the Department of Electrical Engineering, University of Zanjan, Zanjan, Iran M.Yargholi and S. Toofan have been
working as assistant professors with the Department of Electrical Engineering, University of Zanjan, Zanjan, Iran M. Safari is a Msc. student with the Department of Electrical Engineering, University of Zanjan, Zanjan, Iran.

CC
Stage 1 : 6b MADC

Vref

Vin

Gm1

A1

Vout

Vin
6b ADC 6b DAC

32

V res

Stage 2: 7b ADC

Fig.

1. Two-stage amplifier
Vref

7 Dout,2

2 CIRCUIT DESCRIPTION
2.1 Proposed Structure In pipeline ADCs with M bit MDAC resolution, the feedback factor of op-amp, !, will be 21 M . Conventional pipeline stages solve only 1.5 bit per stage with !=1/2 (closed loop gain nearly 2), but these architectures consume more power due to a large number of stages (for 12 bit, needs 11 stages), and consequently large number of op-amps [5]. There are architectures in some publications which solve more than one bit per stage, reducing the ! and increasing the closed loop gain [2], [3]. The objective of this paper is designing of an operational amplifier that is suitable for two stage pipeline ADC with 12bit resolution and conversion rate of 20 MS/s. As demonstrated in Fig. 2, first stage has 5 bit, with one bit redundancy and second stage with 7 bit resolution. Fig. 3 depicts the proposed op-amp architecture, which is a single stage folded cascode amplifier. The gain boosting technique applied in this amplifier as shown with AN and Ap amplifiers. The op-amp closed loop small signal model is shown in Fig. 4. Cpi and Cpo indicated the input, output parasitic capacitances. Cl and RL presents the load capacitance and output resistance respectively. Cf and Cs make the feedback loop, where, = Cf / ( Cf + Cs + Cpi ) (1) In this design Cs is much greater than Cf due to required large ! (1/32) and "p2 is the non dominant pole of the opamp. This pole located in folding node, drain of M3,4 in Fig. 3. The main folded cascode amplifier uses PMOS transistors as input pairs, to greatly reduces the parasitic capacitance at folding nodes, and consequently located "p2 in upper frequencies.

6 Dout,1
Digital Error Correction Block
12

Dout,final

Fig. 2. Two stage pipeline ADC with proposed op-amp

M9
AP

M 10

V in 1

M1M

V in 2

M8
Vout

M5
AN

M3

Fig. 3. Single stage, regulated, folded cascode op-amp

Cf
OpAmp
1

2.2 Gain Boosting Isuee The main goal of applying gain boosting amplifiers AP and AN, is to increasing the output resistance. The dedi- cated output resistance is equal to:

CS

C pi

gm

1+

p2

C po

RL

Rout = AN gm6 ro6 ro 4 Ap gm8ro8ro10

(2)

This improved output resistance drastically increase the gain of main amplifier. The stability of main amplifier is an important issue during the gain boosting operation of AP and AN. So defining the unity gain frequency of the auxiliary amplifier is a bottleneck as discussed in several publications [6], [7]. A low bandwidth auxiliary amplifier leads to a pole zero doublet, causes a slow settling behav

Fig. 4. Small signal model of closed loop op-amp

VDD

M 15

M 16

VCMFB

Outm

M 11

M 13
Vref

M 14

M 12

Outp

M 17

Biasn

M 18

Fig. 5. The CMFB circuit

1
VCM

Vout +

Vout 2

1
VCM

C2
Vb

C1

C1 2

C2
Vb

1
Vctrl

Fig. 6. SC-CMFB used in main amplifier

iour in closed loop architecture and an auxiliary ampli- fier with too large bandwidth causes the amplifier may become unstable. To satisfy the stability of the whole structure, unity gain frequency of gain boosting amplifi- ers need to be less than the second pole but greater than first pole of the main amplifier.

, from this view the overdrive voltage of M3 and M4 could not be chosen so large. But to satisfy bandwidth require- ments, using a large current, M3 and M4 will require a high over drive voltages (if their capacitance in folding nodes minimized) [8]. To ensure wide swing and noise immunity, all the cir- cuits, i.e. main amplifier and two auxiliary amplifiers are chosen fully differential architectures, so using the com- mon mode feed back (CMFB) circuits are inevitable to prevent the output common mode voltages from fluctuat- ing. As illustrated in Fig. 5, the CMFB circuit, which is used in AP and AN amplifiers, are as the same used in [9]. This simple CMFB consumes only 70A from 1.8V. Its performance is explained in following for AN amplifier and it is the same for AP. As AN has similar architecture to main amplifier, the performance of CMFB explained with corresponding transistors in main amplifier in Fig. 3. In Fig. 5 the input transistors M11 and M12 sense the output voltage of AN and compare this sensed voltages with Vref in the gate of M13, M14. VCMFB is injected to gate of M9AN and M10AN After that the output common mode will not be more sensitive to the mismatches between two current sources, M9-10AN and M3-4AN, and can be stabilized in fixed 0.9V as common mode voltage is needed. As depicted in Fig. 6, SC-CMFB is chosen for main amplifier due to its low power consumption [10]. Vctrl is applied to gate terminal of M9 and M10 in Fig. 3. The other important design issue of differential folded cascode amplifier is the difference of biasing currents in input transistors (M1-2) and the transistors in cascode stage (M3-10). If the current in the cascode stage is small, a slow CMFB circuit leads to nonsymmetrical output slewing, and the output current becomes the bottleneck for the differential slew rate of the op-amp [6]. The current of cascode stage is selected near the current of input pairs to have a symmetrical output.
4

VDD -(VOD3 +VOD5 + VOD7 + VOD9 ) (3)

SIMULATION RESULTS

3 DESIGN PROCESS
The gain boosting amplifier, AP is another folded cascade amplifier with NMOS transistors as input pairs and the AP part amplifier is similar to main amplifier i.e. a folded cascode with PMOS input pairs. In design process, the width of M3 and M4 in Fig. 3, must be chosen carefully due to bring compromise between speed and output swing tradeoffs. The pick to pick output swing in each side is equal to :

The gain and phase response of the proposed amplifier in open loop configuration is shown in Fig.7. With the load capacitances of 2pF, resulting dc gain is about 75dB, the o phase margin is 68 with unity gain band width of larger than 1GHz. The closed loop frequency response with feedback factor of 1/32 is depicted in Fig. 8. The transient analysis of closed loop output in Fig. 9, illustrates that, the available output swing is high, from 0.2V-1.6V. The measured THD is less than %6. Measured settling time from Fig. 10 is about 6ns with 1% accuracy, that is sufficient for sampling frequency of the desired ADC 20MS/s (must be settle to 0.1% accuracy in less than one-half clock cycle of 50 ns) [11], and obtained slew rate is 150V/s. Table 1 compares the performance of the proposed opamp with some other previously reported topologies.

2012 JOT www.journaloftelecommunications.co.uk

gain frequency of 1.13 GHz. The phase margin is 68 and the amplifier consumes 7.5mW DC power from 1.8V sup- ply voltage and has a high output swing of 1.2 Vp-p.
O utm

TABLE 1 Summary of results

This work 180nM 75dB 1.13GHz 2pF 6ns 150V/s 1.2V Vp-p 7.5mW

Parameter Fig. 7. Gain and phase of open loop response Technology DC gain UGBW Load cap. Settling time(1%) Slew rate Output swing Fig. 8. closed loop gain with =1/32 Power cons. Supply voltage

[9] 0.25 M 79.17 1.16GHz 1pF 10ns NA 650m Vp-p 16.5mW

[12] 90 nM 50 dB 57MHz 6pF NA NA NA 80mW

[13] 180 nM 50 dB 310MHz 10pF 10ns 20V/s 280mV 2.28mW

2V

1V

1.8V

1.8V

Fig. 9. Transient analysis of closed loop output with =1/32

REFERENCES
[1] A. M. Abo, Design for Reliability of Low-voltage, Switched- capacitor Circuits, PhD. dissertation, University of California, Berkeley, spring 1999. J. li, F. Maloberti, Pipeline of Successive Approximation Con- verters with Optimum Power Merit Factor, Springer, vol. 45, pp. 211-217, 2005. C. C. Lee and M. P. Flynn, A SAR assisted 2-stage pipeline ADC, IEEE J. Solid-State Circuits, vol. 46, no. 4, pp. 859-869, Apr. 2011. B. Razavi, Principles of data conversion system design, New York: Wiley/IEEE Press, 1994. S. I. Ahmed. Pipelined ADC Design and Enhancement Tech- niques. Analog circuits and Signal Processing, Springer, 2010. K. Gulati and H. S. Lee. A High Swing CMOS Telescopic Op- erational Amplifier, IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 2010-2019, Dec. 1998. K. Bult and G. Gleen, A Fast-Settling CMOS Op Amp for SC Circuits with 90-dB DC Gain, IEEE J. Solid-State Circuits, vol. 25, no. 6, pp. 1379-1384, Dec. 1990. B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, New York, 2000.

[2]

[3]

Fig. 10 Step input and output settling

[4] [5] [6]

5 CONCLUSION
A fully differential single stage folded cascode amplifier with two gain boosting auxiliary amplifiers, is designed and simulated with TSMC 0.18 CMOS technology. In this paper, the amplifier is designed with closed loop gain of 32 to satisfy the requirements of the gain stage from a two stage pipeline ADC, with 6 bit MDAC resolution. Simula- tions show a low frequency gain of around 75 dB, a unity

[7]

[8]

[9]

[10] [11]

[12]

[13]

C. C .Lee, J. May, A. Grichener, A Low-Voltage High Gain CMOS Op Amp for SC Circuits with 1GHZ Bandwidth, Uni- versity of Michigan, EECS 413, 2004. D. Johns and K.W. Martin, Analog integrated circuit design, John Wiley & Sons, 1997. L. Sumanen, Pipeline Analog-to-Digital Converters for Wide- Band Wireless Communications, PhD. dissertation, Helsinki University of Technology, Helsinki, 2002. L. Yao, M. S. J. Steyaert, and W. Sansen, A 1-V 140-W 88 dB Audio Sigma-Delta Modulator in 90nm CMOS, IEEE J. Solid State Circuits, Vol. 39, No. 11, pp. 1809-1818, Nov. 2004. M. Memarian, S. Toofan, Design And Simulation of High per- formance Operational Transconductance Amplifier, Canadian Journal on Electrical and Electronics Engineering vol. 2, no. 7, pp. 275-281, Jul. 2011.

Leila Bagheriye received the B.Sc. degree in Control Engineering from Tabriz University, Tabriz, Iran in 2010, and the MSc degree in Electronics Engineering form the University of Zanjan, Zanjan, Iran in 2012. Her research interests are in the area of high-speed low-power A/D converters. Mostafa Yargholi received the B.Sc. degree in Communication Engineering from Iran University of Science and Technology (IUST), Iran in 2002, and the M.Sc. And Ph.D. degree in Electronics Engineering form Tarbiat Modares University (TMU), Iran in 2004 and 2009, respectively. He has been working as assistant professor with the Department of Electrical Engineering, University of Zanjan, since 2009. His current research interests include designing of RF Integrated Circuits, UWB systems, and CMOS Integrated Circuits. Siroos Toofan received the B.Sc. degree in Electronics Engineering from Amirkabir University of Technology (Tehran Polytechnic) in 1999, and the MSc. And PhD degree in Electronics Engineering form ran University of Science and Technology (IUST) in 2002 and 2008, respectively. During 2007 to 2008, on his sabbatical leave, he was with the VLSI group of Politechnico di Torino and in the Microelectronics- Integrated Circuits Lab. of the Politechnico di Milano Universities in Italy. He has been working as assistant professor with the Department of Electrical Engineering, University of Zanjan, since 2009. His current research activities include the design of CMOS Analog Integrated Circuits, RF Integrated Circuits and Capacitive Sensors Readout Circuits. Maryam Safari received the B.Sc. degree in Electrical Engineering from the University of Babol, Babol, Iran in 2009 and the MSc degree in Electrical Engineering from University of Zanjan, Zanjan, Iran in 2012. Her research interests include the design and analysis of highspeed analog, RF, and mixed-signal integrated circuits.