International Journal of Electrical and Electronics Engineering Research (IJEEER) ISSN 2250-155X Vol.

3, Issue 2, Jun 2013, 19-28 TJPRC Pvt. Ltd.

TJPRC Pvt. Ltd.,

HIGH GAIN AND PHASE MARGIN CMOS OPERATIONAL AMPLIFIER DESIGNS

NEHA ARORA1, SHALU MALIK2, PRASHANT SINGH3 & NARENDRA BAHADUR SINGH4

TJPRC Pvt. Ltd.,

Chief Scientist, MEMS, MS & RF ICS Design, Central Electronics Engineering Research Institute (CSIR-CEERI), Pilani, India
3

Senior Project Fellow at CSIR-CEERI, Pilani, India

1,2

M.Tech (VLSI Design) Trainees at CSIR-CEERI Pilani from Banasthali University, India

ABSTRACT
The paper presents the designs of high gain and phase margin low power cmos operational amplifiers near 200nm Technology, since it is a fundamental building block in all analogue integrated circuits. Up to the third order operational amplifiers designs are presented in this paper, including the design of a fully differential folded cascode configuration with all the transistors are operating in saturation region in all configurations. The designs are carried out in parallel based on higher order model of operational amplifier and its circuit simulation in spice using Hspice model parameters. The mos transistors parameters optimizations were carried out to achieve the best performance of the operational amplifier near to 200nm Technology. The simulation results of the spice agree with the results of calculated parameters of the amplifiers mathematical models.

KEYWORDS: CMOS, OTA, Operational Amplifier, Analog Integrated Circuits INTRODUCTION

The challenge in the design of op amps is the scaling down of the supply voltage and transistor channel length with each generation of CMOS technologies. As CMOS technology continues to evolve, the supply voltages are decreasing while at the same time, the transistor threshold voltages are remaining relatively constant. The decrease in the inherent gain of the nano-CMOS transistors is also of great concern. Traditional techniques for achieving high gain by vertically stacking (i.e. cascoding) transistors becomes less useful in sub-100nm processes. Horizontal cascading (multi-stage) must be used in order to realize op-amps in low supply voltage processes [3]. Obtaining high gain from an op-amp is of great importance. The first challenge in providing high gain is the small supply voltage which limits the cascade topology to have enough output voltage swing. Therefore the use of this topology in output stage is not suitable [4]. The second problem in the deep submicron process is small transistors output resistance. In order to increase this resistance one should decrease the bias current of transistor which in turn reduces the speed. Another solution to overcome to the problem is implementing gain boosting [5] to enhance gain in a high speed circuit. To achieve high gain, at least, two cascaded stages are required. Modern high performance analog integrated circuits make use of fully differential signal paths. Op-amps having differential input as well as differential output are referred to as fully differential op-amp. Common Feedback circuit is added with fully differential op-amp to provide the common mode output voltage [6].

THEORY
Equivalent Circuit of a two stage operational amplifier is shown in figure 1.

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Neha Arora, Shalu Malik, Prashant Singh & Narendra Bahadur Singh

Figure 1: Schematic for Two Stage OP-Amp [1] Design of a two stage op amplifier, its transistors sizes and simulation results are presented here, Table 1: Aspect Ratio of Transistors Transistor M1/M2 M3/M4 M5/M8 M6 M7 W/L (m) 3/1 15/1 4.5/1 94/1 14/1

L=1m VDD=1.8V CC=3pf; CL=10pf Unity Gain BW=3.2MHz 3dB Frequency=690 Hz Gain=76dB Phase= 52 Theoretical calculation of gain Method 1: gm based gain and phase calculation,

where,

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n = 259.530 * 10-4 m2/V s (Mobility for NMOS ) p = 109.976 * 10-4 m2/V s (Mobility for NMOS ) tox=4.1 *10-9 m

Cox= ox / tox= 8.57*10-3 F/m2 ox = 3.97 *8.854 *10-12 F/m

(1) can be calculated by using Eqn. (1). The calculated values of are shown in table 1.

(2) g m can be calculated using Equation (2) , by using the calculated values of and gm, gain can be calculated using following formula:

calculated value of gain using eqn. (1) and eqn. (2) is, Av = 68.61dB Method 2 gds based gain and phase calculations,

(4)

(5) can be calculated using Eqn.(4) and gm can be calculated using Eqn.(2)[1]. The calculated values of and gm are shown in table 2.

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Neha Arora, Shalu Malik, Prashant Singh & Narendra Bahadur Singh

Table 2: Parameter Values for Two Stage OP-Amp Transistors gm() gm() gm() Calculated Calculated Calculated Spice from gDS from ID from gDS O/p M1/M2 1-Mar 0.29 0.14 91 81 76 M3/M4 15/1 0.41 0.08 104 127 78 M5 4.5/1 0.04 0.14 141 146 135 M6 94/1 0.18 0.08 678 765 503 M7 14/1 0.03 0.11 450 400 135 * all rounded figures for gm calculations calculated value on the basis of (from gDS) Eqn. (2), of 79.60dB Transistor W/L Calculated from ID AC Analysis: AC- Analysis determines Phase margin, Gain and GBW of the OP-Amp.

Figure 2: Ac Analysis of Two Stage OP Amp (L=1m) Start frequency = 1Hz Stop frequency = 10MHz

ICMR (Input Common Mode Range) Estimation

Figure 3: Circuit and its Response for the Input Common Mode Voltage Range of Two Stage OP-Amp[1]

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The unity gain configuration is useful for measuring or simulating ICMR. For this, a dc transfer sweep is plotted and the linear part of the transfer curve where the slope is unity corresponds to the input common mode voltage range. Calculated value of ICMR is 0.75-1.46V[1]. Common Mode Rejection Ratio (CMRR) Estimation

Figure 4: Circuit and its Response for the Common Mode Rejection Ratio of two Stage OP-Amp[7] The common mode rejection ratio of an op amp is defined as [8] =80.66dB Transient Analysis Slew Rate The slew rate is defined as the maximum rate of change of output voltage. For slew rate calculation, non inverting terminal is connected to a pulse with delay of 0.5s and a pulse width of 1s. The value of pulse period is 3s. SR+=2.1V/s SR-=1.83V/s

Figure 5: Circuit and its Response for the Slew Rate of two Stage OP-Amp[1] Table 3: Aspect Ratio of Transistors Transistor M1/M2 M3/M4 M5,M8 M6 M7 W/L(m) 0.6/0.2 3/0.2 0.9/0.2 18.8/2 2.8/0.2

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Neha Arora, Shalu Malik, Prashant Singh & Narendra Bahadur Singh

The Two Stage OP Amp for L=0.2m Unity Gain BW=3.27MHz 3dB Frequency= 6 kHz Gain(simulation)=53.20dB Phase= 59.42 Gain (calculated) =52.52dB Three Stage OP Amp (L=1m) Table 4: Aspect Ratio of Transistors Transistor M1/M2 M3/M4 M5 M6 M7 M8 M9 M10 Gain Phase W/L(m) 1-Apr 15/1 4.5/1 99/1 14/1 4.5/1 1-Dec 1-Oct 109dB 59 W/L(m) 2/0.2 3/0.2 0.9/0.2 22/0.2 2.8/0.2 0.9/0.2 15/0.2 5/0.2 81dB 74

Figure 6: Schematic for Three Stage OP-Amp Values of gm and are calculated using eqn. (2) and eqn. (4) respectively. Gain is calculated for the highlighted columns. For L=1m,

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AV=49643.3AV (dB) =20 log (49643.3) =20*4.69=93.91dB Calculated value of gain=93.91dB Simulated Gain =108.51dB

Figure 7: Ac Analysis of three Stage OP-Amp (L=1m) For L=0.2m Calculated value of gain=67.28dB Simulated Gain =80dB Table 5: Comparison of Different OP-Amp Parameters Results Gain(dB) Phase Margin(PM) -3dB(KHz) UGB(MHz) CMRR(dB) ICMR(dB) Slew Rate (V/s) SR+ /SRFor L=1m Two Stage 76dB 52 0.7 3.2 81dB 0.75-1.46V 2/1.8 (V/s) For L=0.2m Two Stage 53dB 60 6 3.27 60dB 0.75-1.46V 2/1.8(V/s) For L=1m Three Stage 109dB 59 5 12 92dB 0.7-1.77V 4.5/14(V/s) For L=0.2m Three Stage 80dB 70 30 31 61dB 0.65-1.77V 4.7/13.5(V/s)

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Neha Arora, Shalu Malik, Prashant Singh & Narendra Bahadur Singh

Fully Differential Folded Cascode Operational Transconductance Amplifier (OTA)

Figure 8: Schematic for Fully Differential Folded Cascode OTA [7] The name, folded cascade, comes from folding down p-channel cascode active load of a differential pair and changing the MOSFETS to n-channel.The fully differential folded cascode OTA is shown in figure 9, it uses a common mode feedback circuit (CMFB). The inputs to the CMFB circuit are vo+ and vo- of OTA and output is VCMFB. The unique aspect of this circuit is its rejection to a difference mode signal on its inputs and amplification of the common mode signal. This is exactly the opposite of what a single diff-amp does. To be exact, the CMFB circuit amplifies the difference b/w the average of the outputs, ( vo+ + vo-)/2 and VCM [7].

Figure 9: Schematic for Fully Differential Folded Cascode OTA with CMFB Circuit [8]

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Table 6: Performance Parameter of the OTA Performance Parameter DC Gain Phase Margin Bandwidth UGB CMRR Values 70dB 88 1kHz 3.2MHz 74dB

Table 7: Aspect Ratio of Transistors Transistor M1,M2 M3,M4 M5,M6 M7,M8 M9,M11 M10 W/L(m) 30 20 10.22 2 5 4.72 Transistor M12 M13,M14 M15,M16 M17,M18 M19,M20 M21,M22 W/L(m) 4.72 5.79 4.69 45.76 20.55 30.37

Figure 10: Gain Plot of Folded Cascode OTA

Figure 11: Phase Plot of Folded Cascode OTA

CONCLUSIONS
In this paper the mos transistors parameters optimization are carried out to achieve the best performance of the operational amplifier near to 200nm Technology for second and third order amplifier including the design of a fully differential folded cascode configuration with all the transistors are operating in saturation region. Gm and Gds based

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Neha Arora, Shalu Malik, Prashant Singh & Narendra Bahadur Singh

calculations were carried out in the physical model to calculate gain and phase of the second and third orders amplifiers and its results are also compared with the spice simulat ion results, as presented in various tables. The open loop gain is 76dB for two stage, 109dB for three stage and 70dB for cascode configuration, based on simulated output frequency response for 1.8V dc supply voltage. In this paper trade off curves are computed for the characteristics such as Gain, PM, UGB, ICMR, CMRR, Slew Rate etc.

REFERENCES
1. P. Allen and D. Holberg CMOS Analog Circuit Design, International 2nd Edition. Oxford University Press, 2009. 2. 3. 4. B. Razavi, Design of Analog CMOS Integrated Circuits, New York: Mc Graw-Hill, 2001. http://cmosedu.com/jbaker/papers/talks/Multistage_Opamp_Presentation.pdf Mohammad Mojtaba Sheikholeslami, Abbas Golmakani, Khalil Mafinezhad, Design of a Low-Voltage, LowPower, Two-Stage Amplifier in 0.18m CMOS Process, International Journal of Academic Research in Applied Science1(4): 9-15, 2012. 5. Bult K., Geelen G. J. G. M., "A fast-settling CMOS op amp for SC circuits with 90-dB DC gain", IEEE Journal of Solid-State Circuits, Vol.25, pp. 1379-1384, Dec. 1990. 6. 7. 8. Keneth R. Laker, Willey M.C.Sansen,Design of Analog Integrated Circuits and Systems, McGraw - Hill. R.J. Baker,CMOS Circuit Design, Layout and Simulation, Wiley-Interscience, 2004. A.S. Sedra and K.C.Smith, Microelectronics Circuits Theory and Applications, Fifth Edition. Oxford University Press, 2009.