N-channel 500 V, 0.40 , 11 A TO-220, TO-220FP, TO-247 Zener-protected SuperMESHTM Power MOSFET
Features
Type STF13NK50Z STP13NK50Z STW13NK50Z
RDS(on) max
ID
3 1 2
TO-220FP
Extremely high dv/dt capability 100% avalanche tested Gate charge minimized Very low intrinsic capacitances Very good manufacturing repeatability Figure 1. Internal schematic diagram
TO-247
2 1 3
Applications
Switching application
Description
The SuperMESH series is obtained through an extreme optimization of STs well established strip-based PowerMESH layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications. Such series complements ST full range of high voltage MOSFETs.
Table 1.
Device summary
Order code Marking F13NK50Z P13NK50Z W13NK50Z Package TO-220FP TO-220 TO-247 Packaging Tube Tube Tube
March 2009
Rev 2
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Contents
STx13NK50Z
Contents
1 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) ............................ 6
3 4 5
Test circuit
................................................ 9
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Electrical ratings
Electrical ratings
Table 2.
Symbol VDS VGS ID ID IDM(2) PTOT dv/dt(3) VISO TJ Tstg
1. Limited only by maximum temperature allowed 2. Pulse width limited by safe operating area 3. ISD 11 A, di/dt 200 A/s, VDD 80% V(BR)DSS
Table 3.
Symbol Rthj-case Rthj-a Tl
Thermal data
Value Parameter TO-220 Thermal resistance junction-case max Thermal resistance junction-ambient max Maximum lead temperature for soldering purpose 62.5 0.89 50 300 TO-247 TO-220FP 4.17 62.5 C/W C/W C Unit
Table 4.
Symbol IAR EAS
Avalanche characteristics
Parameter Avalanche current, repetitive or not-repetitive (pulse width limited by Tj Max) Single pulse avalanche energy (starting TJ = 25 C, ID = IAR, VDD= 50 V) Value 11 240 Unit A mJ
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Electrical characteristics
STx13NK50Z
Electrical characteristics
(TCASE = 25 C unless otherwise specified) Table 5.
Symbol V(BR)DSS
On/off states
Parameter Drain-source breakdown voltage Zero gate voltage drain current (VGS = 0) Gate body leakage current (VDS = 0) Gate threshold voltage Static drain-source on resistance Test conditions ID = 1 mA, VGS= 0 VDS = Max rating, VDS = Max rating, TC =125 C VGS = 20 V VDS= VGS, ID = 100 A VGS= 10 V, ID= 6.5 A 3 3.75 0.4 Min. 500 1 50
10
Typ.
Max.
Unit V A A A V
IDSS
4.5 0.48
Table 6.
Symbol gfs
(1)
Dynamic
Parameter Forward transconductance Input capacitance Output capacitance Reverse transfer capacitance Test conditions VDS =15 V, ID = 6.5 A VDS =25 V, f=1 MHz, VGS=0 Min. Typ. 8.5 1600 200 45 50 47 9 28 2.3 Max. Unit S pF pF pF pF nC nC nC
Equivalent output Coss eq(2). capacitance Qg Qgs Qgd Rg Total gate charge Gate-source charge Gate-drain charge Intrinsic gate resistance
VGS=0, VDS =0 V to 400 V VDD=400 V, ID = 13 A VGS =10 V Figure 20 f= 1 MHz open drain
1. Pulsed: pulse duration=300s, duty cycle 1.5% 2. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS
Table 7.
Symbol td(on) tr td(off) tf
Switching times
Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions VDD=400 V, ID=6.5 A, RG=4.7 , VGS=10 V Figure 19 Min. Typ. 18 23 61 24 Max. Unit ns ns ns ns
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Electrical characteristics
Table 8.
Symbol ISD ISDM VSD
(1) (2)
1. Pulse width limited by safe operating area 2. Pulsed: pulse duration=300s, duty cycle 1.5%
Table 9.
Symbol
1. The built-in back-to-back Zener diodes have specifically been designed to enhance not only the devices ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the devices integrity. These integrated Zener diodes thus avoid the usage of external components.
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Electrical characteristics
STx13NK50Z
2.1
Figure 2.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
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Figure 12. Gate charge vs gate-source voltage Figure 13. Capacitance variations
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STx13NK50Z
Test circuit
Test circuit
Figure 20. Gate charge test circuit
Figure 21. Test circuit for inductive load Figure 22. Unclamped inductive load test switching and diode recovery times circuit
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STx13NK50Z
mm Dim Min A b b1 c D D1 E e e1 F H1 J1 L L1 L20 L30 P Q 4.40 0.61 1.14 0.48 15.25 1.27 10 2.40 4.95 1.23 6.20 2.40 13 3.50 16.40 28.90 3.75 2.65 3.85 2.95 0.147 0.104 10.40 2.70 5.15 1.32 6.60 2.72 14 3.93 0.393 0.094 0.194 0.048 0.244 0.094 0.511 0.137 Typ Max 4.60 0.88 1.70 0.70 15.75 Min 0.173 0.024 0.044 0.019 0.6
inch Typ Max 0.181 0.034 0.066 0.027 0.62 0.050 0.409 0.106 0.202 0.051 0.256 0.107 0.551 0.154 0.645 1.137 0.151 0.116
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STx13NK50Z
Typ.
Max.
4.6 2.7 2.75 0.7 1 1.70 1.5 5.2 2.7 10.4
L7 E A
B Dia L6 L5 F1 F2 F D
H G1
L2 L 3
L4 7012510_Rev_J
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Dim. A A1 b b1 b2 c D E e L L1 L2 P R S
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Revision history
STx13NK50Z
Revision history
Table 10.
Date 07-Aug-2007 19-Mar-2009
Revision history
Revision 1 2 First version Update ID value test condition in Table 6. Changes
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STx13NK50Z
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