Laborator 3 Introduction to simulation using Xilinx ISim in Verilog

Necessary Software ISE 12.2 or newer software

Laboratory work
1. Simulate a subcomponent of a project a. Create a new project on C:\Temp targeting the FPGA device present on the development board you have. Name the project Fuladder_4bit_group_name, b. Add the HA.v, fuladd.v and fulladd_4bit.v files from the .\Lab3 folder to your project. The top level module should be fuladd_4bit. c. In ISE create a new Verilog Test Fixture (Testbench) like the figure below shows. Name the testbench test_Halfadder

Figure 1. Creating a testbench d. Associate the testbench to the HA module as the picture below shows:

Figure 3. Associating the testbech to a specific module

e. Look to the code of the newly created testbench:

f. In order to test the functionality of the halfadder we have to apply all the four possible values for a and b. Keep in mind that a = 0 and b = 0 is already applied as initial value.Lets change the values with a delay of 25nS. Therefore the statements area will look like: #25; a = 1b1; b = 1b0; //it is not necessary to write this statement since b is already 0; #25; a = 1b0;

b = 1b1; #25; a = 1b1; g. Save the testbench and switch in ISE to simulation mode and expand the Test_Halfadder module to check if HA is present in the hierarchy, as shown in the figure below:

Figure 4. Switching to simulation mode h. Very Important: Select the Test_Halfadder module, not the HA module, neither the fulladd_4bit module! ISE will simulate always the module selected i. In the Processes window expand ISim Simulator and double-click on the Simulate Behavioral Model, as the figure below shows:

Figure 5. Starting simulation

j.

Zoom to Full view in ISim and check the functionality of the Halfadder.

2. One-bit Full Adder a. Create a testbench and simulate the one-bit fulladder module in a similar manner as above Note: There will be three inputs: a, b and cin. A better way to set all the possible values is to use either a for() loop or repeat () statement: Using for () loop, the code of the testbench should look like below: //define a local parameter for time delay in the signal definition area localparam TM_DEL = 25; //define a 3-bit counter in the signal definition area reg [2:0] cnt; initial begin #100; //in the Statements area: for (cnt = 0; cnt<=7; cnt = cnt +1) begin a = cnt[0]; b = cnt[1]; cin = cnt[2]; #TM_DEL; end //for end //initial begin Insert the code above into the testbench and run the simulation. Note that the testbench will run in an infinite loop. This is because the cnt <=7 condition is always true. Same happens if the condition changes to cnt <= 8. It means that any statement after the for () loop will never be executed. One solution to this problem is to increase the number of bits for cnt, for example to 4, or define cnt as integer (that will make cnt 32-bit wide). In this case the cnt <= 7 condition will not be satisfied when cnt becomes 8.

Another solution is to use the repeat () statement. The general form of the repeat () statement is: repeat (NR_TIMES) begin //Statements end where NR_TIMES has to be a constant number. All of the statements between begin and end will be repeated (in the order in which are written) NR_TIMES times. The code snippet for the testbench should look like below: //define a local parameter for time delay in the signal definition area localparam TM_DEL = 25; //define a 3-bit counter in the signal definition area reg [2:0] cnt; initial begin cnt = 0; //now we have to also initialize cnt #100; //in the Statements area: repeat (8) begin a = cnt[0]; b = cnt[1]; cin = cnt[2]; #TM_DEL; cnt = cnt +1; end //repeat end //initial begin Change the code in the testbench with the one described above and run the simulation. Note that the testbench will now run only once.

3. Four-bit Full Adder a. Create a testbench for the top-level module and simulate the fourbit fulladder in behavioral mode. Use the repetitive instructions described at point 2.a. Note that a and b are 4-bit wide now. 3.a.1. Define cnt on 9 bits and connect a to cnt[3:0], b to cnt [7:4] and cin to cnt[8]. Use repeat statements in the testbench. The code snippet should look like below: initial begin cnt = 0; //now we have to also initialize cnt #100; //in the Statements area: repeat (512) begin a = cnt[3:0]; b = cnt[7:4]; cin = cnt[8]; #TM_DEL; cnt = cnt +1; end //repeat end //initial begin Insert the code above into the testbench and run the simulation. Note that the simulation will run, by default, only up to 1us. Estimate the time needed to run the simulation for all of the values (in the case above it will be 512 * TM_DEL + 100 ns) Use in Isim the restart and run time (for example: run 25 us) commands to run the simulation up to the desired time. 3.a.2. Because a, b and cin are defined as reg, the cnt signal is not needed in fact. All the values for a, b and cin can be set in the testbench by using nested repeat () statements. The code snippet should look like below: initial begin #100; //in the Statements area: repeat (2) begin

repeat (16) begin repeat (16) begin #TM_DEL; b = b + 1; end a = a+1; end cin = cin +1; //or cin = ~cin, because cin is 1-bit wide end //outer repeat end //initial begin Insert the code above into the testbench and run the simulation. Estimate the time needed to run the simulation in order to display all of the values and use the restart and run time commands in Isim to run the simulation up to the desired time. b. In Isim go to the Instances and processes tab, as the figure below shows:

Figure 6. Instances and processes tab. Expand the arrow beside the testbench name and the sub-arrows. Note that the hierarchy of the design is present in behavioral simulation. You can wiew any internal signal by adding it to the wave window (by simply dragging the signal to

the wave window), as the figure below shows. The signal added to the wave window, according to the hierarchy is Test_Fulladd_4bit/uut/FA0/HA0/a, that in fact is connected to the lsb of the a input, i.e. a[0]

Figure 7. Adding an internal signal to the wave window. Note that the values of the internal signal are not displayed in the wave window, only after a restart and a run time command is issued c. Post-Translate and Post-Place and Route simulations can be run only for the top-level module in the design, in our case the 4-bit fulladder Switch to PostTranslate simulation in ISE and run the post-translate simulation for the 4-bit fulladder. In Isim go to the Instances and Processes tab and expand the uut unit. Note that the hierarchy is not preserved after the circuit was synthesized, therefore is difficult to find the internal signals d. Modify the testbench such as before the repeat () statements a and b changes from 4h0 to 4hf, and cin changes from 0 to 1, then all signals change from 1 to 0 The code snippet should look like below: .. #TM_DEL; a = 4hf; b = 4hf; cin = 1b1; #TM_DEL; a = 4h0; b = 4h0;

cin = 1b0; #TM_DEL; repeat (2) begin In this case all the input bits change, therefore the maximum timing delay is expected in Post-Route simulation. Run the Post- Route simulation. Note that the outputs will change after a timing delay. In Isim, using the cursors measure the timing delay (from input change until S becomes stable) when all the input bit change at the same time! e. Apply the ucf constraints for the Nexys2 board as indicated in Lab2 and rerun the Post- Route simulation! What is the timing delay comparing to point d?

4. Comparison between 8-bit fast adder and cascaded carry-adder The XST synthesizer is able to infer an optimized adder if the adder is described in behavioral. The code of the module is the one below: module Fast_8bit_adder ( input [7:0] a, input [7:0] b, output [7:0] s, output c ); //we define an internal wire to make the sum wire [8:0] s_int; //force 9-bit signals in the assigmnent at both left and right hand to avoid warnings assign s_int = {1b0, a} + {1b0, b}; assign s = s_int [7:0]; assign c = s_int [8];
endmodule

a. Using the HA.v, fuladd.v and fulladd_4bit.v files, create an 8-bit adder using generate statements. Name the module Cascaded_8bit_adder. b. Create a top-level module and name it Adders_Comparison, with the following schematic:

Figure 8. Top-level module for comparing 8-bit fast and cascaded adders c. Run the Post-Route simulation for the module below and compare the timing delays of the two adders in the same conditions as at point 3.d. Note the timing delay differences between the two adders!