Laborator 6 One-shot and synchronization circuits

Necessary Hardware and Software Nexys2 Development Boards + USB-Mini Cable ISE 12.2 or newer software

Laboratory exercises
1. Counter clocked from a pushbutton. The button bouncing problem. a. Create a new project on C:\Temp targeting the FPGA device present on the development board you have. Name the project Cnt_8_btn. b. From the ./ Cnt_8_Sources subfolder add the copies of the Verilog files and the .ucf file corresponding to the development board you have c. Draw the block schematic of the design! What are the clock signals in the design?

d. Implement the design for the target board and download the .bit file to the board Btn0 is connected to BTNCLK Btn1 is connected to Reset The counter output is displayed on the seven-segment decoder. Note that when pressing Btn0, the counter may advance more than one increment. This is due to the fact that the pushbuttons mechanical contacts present various surface inequalities; therefore the signal provided by the pushbutton when pressed might have several variations. This phenomenon is called bouncing.

2. One-shot circuit. a. Create a new module in the project created above. Name it one_shot. The schematic of module is presented below. Write the code for the module!

Figure 1. Schematic of the one-shot circuit NOTE: A short method to write the one-shot circuit is to create a two-bit register. b. Insert the module in the Cnt_8_Top_Level module between the BTNCLK input (to BTN) and the clock input of the 8-bit counter (BTN_OS connected to the clock input of the counter). Note that you have to define one more internal signal. Obviously, connect CLK to the system clock. c. Implement the design and try now its functionality on the board. The bouncing is significantly reduced, but not eliminated. This is due to: - The bouncing time for mechanical switches and buttons can be about milliseconds to tenths of milliseconds. However, the system clock has a frequency of 50MHz, it means that the button signal is sampled at a period of 20nS - Every register needs to have the input stable for a specific time before the clock edge. This time is called SETUP TIME. Also, the output will be stable at a specific time after the clock edge. This time is called HOLD TIME. However, the signal coming from the pushbutton is asynchronous (the user can press the pushbutton at any time). This can lead to setup time requirement violations. Setup time requirement violations can make a flip-flop (register) to enter into METASTABLILITY. It means, that the output of the flip-flop is unknown for a specific period of time - The BTN_OS signal is used as a clock signal for the counter; however, it is not a specialized clock signal for the FPGA device. Look at the implementation warning message: PhysDesignRules:372 - Gated clock. Clock net BTNCLK_int is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.

It means that BTNCLK comes from a combinational circuit; combinational circuits due to different signal propagation can generate glitches i.e. impulses whose length is shorter than the clock period. This leads to incorrect circuit behavior In order to study the behavior of the one-shot circuit, proceed to point 3. 3. Studying the one-shot circuit a. Add as a copy the testbench named test_one_shot, found in the ./Cnt_8_Testbench subfolder. Associate the file to simulation only! The input stimulus is shown in the figure below. The clock period is 20 nS.

Figure 2. Testbench stimulus for studying the one-shot circuit b. Analyze the circuit versus the testbench stimulus in Figure 2 and describe its behavior by answering to the questions in the table below! Simulate then the design using behavioral simulation! Represent the internal Q_reg signal! Check your answers versus the simulation results! Table 1. One-shot circuit analysis questions Answer after Answer after Question analyzing the simulating the circuit circuit 1. BTN_OS is activated at (or after) the first impulse of BTN (Clock period 0 to 1) (Y/N)? 2. BTN_OS is activated at (or after) the second impulse of BTN (Clock periods 6 to 8) (Y/N)? 3. What will be the length of the BTN_OS impulse (measured in clock periods) at (or after) the third impulse of BTN (i.e. Clock period 14-15) 4. What will be the length of the BTN_OS impulse (measured in clock periods) at (or after) the fourth impulse of BTN (after Clock Edge 21)?

5. The BTN_OS signal is synchronous to BTN or to the CLK signal? Notes: - The signal for BTN represented in Figure 2 includes impulses similar to the situation when a mechanical pushbutton is pressed - The length of the first and the second impulse of BTN is the same. The only difference in the output effect is that the first one is not sampled by the positive clock edge, and the second one is sampled. Due to the fact that the user can press a button anytime, it is unknown which impulse will be sampled by the positive clock edge. Both impulses are shorter than the clock period, therefore both are considered as being a GLITCH. A digital circuit that handles external asynchronous signals should remove the effect of glitches. In order to avoid glitches, proceed to point 4.

4. One-shot circuit removing glitches. a. Insert another register into the one_shot module as shown in the figure below:

Figure 3. Schematic of the one-shot circuit with debouncer capability b. Analyze the circuit versus the testbench stimulus in Figure 2 and describe its behavior by answering to the questions in the table below! Simulate then the design using behavioral simulation! Represent the internal Q_reg signal! Check your answers versus the simulation results! Table 1. One-shot circuit analysis questions Answer after Answer after Question analyzing the simulating the circuit circuit

1. BTN_OS is activated at (or after) the first impulse of BTN (Clock period 0 to 1) (Y/N)? 2. BTN_OS is activated at (or after) the second impulse of BTN (Clock periods 6 to 8) (Y/N)? 3. What will be the length of the BTN_OS impulse (measured in clock periods) at (or after) the third impulse of BTN (i.e. Clock period 14-15) 4. What will be the length of the BTN_OS impulse (measured in clock periods) at (or after) the fourth impulse of BTN (after Clock Edge 21)? 5. The BTN_OS signal is synchronous to BTN or to the CLK signal? Notes: - This time the output signal is not activated if the input BTN signal length is shorter than the clock period. Therefore this circuit is able to avoid glitches. This type of circuit is also called DEBOUNCER c. Change the code of the one_shot module such as BTN_OS becomes active for two clock periods, when BTN is active for at least one clock period!

5. Sampling at lower frequencies a. Create a new project on C:\Temp and name it DB_CE_Group_Name. Add as a copy to the project the Verilog files from the .\ Cnt_8_DB_CE subfolder. Associate the Test_DB_CE module to simulation only! b. Draw the schematic diagram of the CE_DB module below!

c. Draw the testbench signal diagram and answer to the following questions: - What is the period of the CE signal? - What is the shortest impulse width for which BTN_OS becomes active?

d. Change the code of the CE_DB module such as the BTN_OS signal becomes active for three clock periods, when BTN becomes active (for at least one CE period) e. Add the CE_DB module to the Cnt_8_btn project. Also create or add the Freq_Div module to the project. Modify the project top-level connections according to the figure below: The Freq_Div module can be found in the ./Lab5 subfolder. Note: Use the Freq_Div, not the Freq_Div_gated module!

Figure 4. Schematic of the modified Cnt_8_Top_Level module including a debouncer circuit with lower frequency sampling f. Create a testbench for the top-level module. Set the OUT_FREQUENCY_HZ parameter to be no less than CLK_FREQUENCY_HZ/20. Create a clock signal for BTNCLK too, with the frequency smaller than OUT_FREQUENCY_HZ. Also set the REFRESH_RATE parameter in the Ssg_Decoder to be no less than the frequency of BTNCLK *4. Dont forget to activate at the beginning of the testbench the Reset signal! Simulate the design using behavioral simulation. Represent the Data signal in order to follow the evolution of the counter! Prove the functionality of the whole circuit using simulation!

Simulate then the design using post-translate simulation, for at least four increments of the counter! Prove the functionality of the circuit using simulation! g. Download the design to the board and try its functionality. 6. Using clock enable a. Modify the top-level module according to the schematic below:

Figure 5. Schematic of the modified Cnt_8_Top_Level module including a debouncer circuit with lower frequency sampling and using count enable b. Simulate the design again using behavioral, then post-translate simulation. Prove the design functionality! c. Also download the design and check its functionality on the board. What is the difference in the design from point 5? What warning message disappeared? d. Change the code of the DB_CE module such as: - BTN_OS becomes active when the pushbutton is released instead of pressed - BTN_OS becomes active both when the pushbutton is pressed or released - BTN_OS becomes active for four clock periods when the pushbutton is pressed e. Change the OUT_FREQUENCY_HZ parameter to 2 and download the design to the board! What will change in the design functionality? What happens if the pushbutton is pressed shortly?