IEEE REVIEWS IN BIOMEDICAL ENGINEERING, VOL.

3, 2010

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Analog Integrated Circuits Design for Processing Physiological Signals

Yan Li, Carmen C. Y. Poon, Member, IEEE, and Yuan-Ting Zhang, Fellow, IEEE
Methodological Review

AbstractAnalog integrated circuits (ICs) designed for processing physiological signals are important building blocks of wearable and implantable medical devices used for health monitoring or restoring lost body functions. Due to the nature of physiological signals and the corresponding application scenarios, the ICs designed for these applications should have low power consumption, low cutoff frequency, and low input-referred noise. In this paper, techniques for designing the analog front-end circuits with these three characteristics will be reviewed, including subthreshold circuits, bulk-driven MOSFETs, oating gate MOSFETs, and log-domain circuits to reduce power consumption; methods for designing fully integrated low cutoff frequency circuits; as well as chopper stabilization (CHS) and other techniques that can be used to achieve a high signal-to-noise performance. Novel applications using these techniques will also be discussed. Index TermsAnalog integrated circuits, low frequency, low noise, low power, medical devices.
Fig. 1. Frequency ranges of some physiological signals, where PCG, PPG, EGG, ECG, ERG, EOG, EEG, and EMG refer to the phonocardiographic, photoplethysmographic, electrogastrographic, electrocardiographic, electroretinographic, el ectrooculographic, electroencephalographic and electromyographic signals respectively.

I. INTRODUCTION

LOBAL population ageing and prevalence of chronic diseases have placed substantial pressure on our current healthcare systems [1][3]. Meanwhile, there is a pressing call for a more proactive healthcare approach, where individuals health conditions will be monitored closely from birth for the prevention, prediction, early detection, and timely treatment of diseases [4][7]. Long-term and continuous monitoring of health conditions are made possible by wearable and implantable devices, which must be small and unobtrusive enough so that users of these devices can maintain their normal lifestyle without interruption. These devices require enabling technologies in six areas: miniaturization, integration, networking, digitalization, smart and standardization (MINDSS) [8], [9].

Manuscript received February 24, 2010; revised August 11, 2010; accepted September 14, 2010. Date of publication September 30, 2010; date of current version December 08, 2010. This work was supported in part by the Hong Kong Innovation and Technology Fund (ITF), the National Basic Research Program of China (973 Program) under Grant 2010CB732606, and the Guangdong Innovation Team Fund in China. Y. Li and Y.-T. Zhang are with the Joint Research Centre for Biomedical Engineering, The Chinese University of Hong Kong, Hong Kong, China. They are also with Key Laboratory for Biomedical Informatics and Health Engineering, Chinese Academy of Science and also with SIAT-Institute of Biomedical and Health Engineering, Chinese Academy of Science (e-mail: ytzhang@ee.cuhk. edu.hk). C. C. Y. Poon is with the Joint Research Centre for Biomedical Engineering, The Chinese University of Hong Kong, Hong Kong, China. Digital Object Identier 10.1109/RBME.2010.2082521

The integration in the above description refers to the design and implementation of integrated circuits (ICs) for these wearable and implantable devices to perform various functions, including processing physiological signals. Physiological signals, for example bio-potentials such as electrocardiogram (ECG), electroencephalogram (EEG), and electromyogram (EMG), chemical quantities such as ion concentrations and physical quantities such as body temperature, blood pressure, are often small signals of low frequency [10], as shown in Fig. 1. Therefore, after converting a physiological signal into an electrical signal by the corresponding type of sensor or transducer, an analog front-end circuit is often needed to lter and amplify the signal before digitizing it for further processing. The design of analog ICs for wearable and implantable devices faces three challenges. Firstly, the design must incorporate low power techniques to reduce the amount of heat dissipation such that the surrounding human tissues will not be damaged. A heat ux of 80 mW/cm can already cause necrosis in muscle tissue [11], [12]. Low power IC design is also important to be used along with new battery technologies to avoid the use of bulky batteries or frequent replacement of batteries during long-term operations. At present, zinc-air batteries are commonly used for button cells to power wearable devices such as hearing-aids because they have high energy densities and are

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Fig. 2.

0V

curves of NMOSFET under different aspect ratios.

relatively inexpensive to produce [13]. Nevertheless, zinc-air batteries have a low current capability and are unsuitable for some long-term monitoring applications. Rechargeable lithium ion batteries are widely used in mobile phones and laptop computers due to their high energy density and light weight compared to other rechargeable batteries [13], [14]. New battery or power technologies, e.g., lithium-air battery technologies or converting electrical power from ambient sources, are under development to yield more powerful and lightweight batteries [15]. Secondly, physiological signals are often low frequency signals that span from dc to a few kilohertz [10]. Sometimes, there is also a large dc component caused by electrode and skin interface residing in the signal. Hence, the analog front-end ICs are often implemented with low cutoff frequencies to read out the signals from the electrodes or sensors. Such designs require large resistances and/or large capacitances, which can be easily achieved with discrete components but are difcult to be fabricated on chip directly due to the large areas they occupy. For example, an integrated 100 pF capacitance already occupies about 0.1 mm . Thirdly, the amplitude of most physiological signals can be relatively small and in the range of a few microvolts to tens of millivolts. The quality of the signals is also largely affected by the noises from the electrodes or sensors, the power supplies, as well as the users motion. Therefore, the circuits must exhibit low input-referred noises to process the weak physiological signals precisely. The paper is organized as follows: In Sections II, III, and IV we will briey review respectively the low power, low frequency, and low noise integrated circuit design techniques for processing physiological signals. Section V gives some examples of the related applications. II. LOW POWER DESIGN METHODS Low power consumption can be achieved by reducing the operation current, lowering the supply voltage, or compressing the signal from current domain to voltage domain using the exponential current versus voltage relation of transistors. A. Subthreshold Circuits Ideally, a MOSFET, for example an N type, should turn on as the gate to source voltage exceeds the threshold voltage

, and turn off as drops below ; however, in reality, there exists a small current owing from drain to source is below . This operation region is called subwhen threshold or weak inversion region [16], [17], which was rst proposed in the 1970s [18][20] and further studied by many groups subsequently [21][25]. In recent years, some designers make use of this characteristic to develop low power circuits. The idea is to bias MOSFET in the subthreshold region, restraining the current to a much smaller value than in regions above the threshold voltage and thereby largely reducing the power consumption. In this paper, we will use weak inversion (i.e., subthreshold), moderate inversion, and strong inversion regions to describe a MOSFETs three operation states, which are differentiated by the inversion coefcient, . These three operation regions are differently dened in different models. For example, in the EKV model [26], the weak inversion/subthreshold, moderate inversion, and strong in, , version region usually corresponds to , respectively. While in Cunhas model, the weak and inversion/subthreshold, moderate inversion, and strong inver, , and sion region corresponds to , respectively [27]. Fig. 2 shows the curves of with different aspect ratios a NMOSFET when in the UMC 0.13- m CMOS process. As shown in the right panel of Fig. 2, the weak inversion current, which is the cur(in the UMC 0.13 m CMOS process, rent when ), can be as low as 1 nA with a small aspect ratio. In addition, since the transconductance is greatest in the weak inversion region compared to that in the moderate and strong inversion regions for a given drain current, biasing a MOSFET in the weak inversion region also helps to decrease the input-referred noise and increase the gain, which are desirable features for processing the small amplitude physiological signals. On the other hand, a MOSFET in the weak inversion region is known to have a poor frequency response. The transitional frequency of a MOSFET in Cunhas model is given by [27]

(1)

where is the mobility of electrons or holes , is the thermal voltage, and is the inversion coefcient of the

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Fig. 3. (a) Bulk driven MOSFET and its equivalent deviceJFET [38]. (b) Schematic symbol and equivalent circuit of multiple-input oating gate MOSFET [28].

MOSFET. According to (1), a small will result in a low transitional frequency. Usually, should be at least three to ten times higher than the operating frequency of the circuit [28]. As a result, small limits the bandwidths of the circuits. For example, and using the UMC 0.13- m CMOS process assuming with cm Vs and m, the transitional freHz according to (1). Suppose quency is calculated to be the transitional frequency is three times higher than the operating frequency, the operating frequency has to be limited within 4 10 Hz. This may be a problem when designing ICs for other applications but not for processing physiological signals, which are normally within 10 Hz, as shown in Fig. 1. Moreover, the source and drain substrate current associated with the reversed moat-substrate junction should not be ignored when the weak inversion current is reduced to a certain level [28]. However, a tradeoff can be made between the bias current and the acceptable leakage current. For the above reasons, subthreshold circuits are the most commonly used in low power designs for processing physiological signals, e.g., a nanopower band-pass lter for detecting acoustic signal [29], a 220 nW neural amplier for a multi-channel neural recording system [30], and a 140 nW modulator for processing EEG [31], all of which operated at nanowatt by using the subthreshold method. B. Low Threshold Voltage Methods Lowering supply voltage is another way to reduce power consumption. Nevertheless, as supply voltage is scaled down cannot be scaled with feature size, threshold voltage down at the same rate since this will increase the off-state or static leakage of digital circuits [32], [33]. Analog IC designers will face big challenges due to the limited voltage headroom under low supply voltages if the threshold voltages cannot be scaled down with supply voltages at the same rate. Some techniques have been used to achieve low equivalent threshold voltages corresponding to low supply voltages. 1) Bulk-Driven MOSFETs: Guzinski et al. were the rst to use a bulk-driven MOS transistor as an active component in an operational transconductance amplier (OTA) differential input stage to yield a small transconductance and to improve the linearity of the circuit [34]. In recent years, their idea has been developed into a technique for lowering threshold voltage in low power circuit designs [35][37]. is controlled In a conventional MOSFET, drain current and the inuence of bulk to by gate to source voltage is only considered as a parasitic effect. source voltage

Different from the conventional setting, as shown in Fig. 3(a), in with a constant a bulk-driven MOSFET, is controlled by . A bulk-driven MOSFET which functions as a JFET like transistor can work with negative, zero, or slightly positive bias voltages. Designing low power circuits with bulk-driven MOSFETs should consider the following [38]: 1) bulk-driven MOSFETs are process dependent and therefore only PMOSFET is available in N-well process, and only NMOSFET is available in should be less than the turn-on voltage P-well process; 2) of the bulk-channel PN junction, otherwise the parasitic bipolar junction transistor (BJT) latch-up may be incurred when is increasing; 3) bulk-driven MOSFETs have poor frequency characteristic and small transconductance compared with the gate driven transistors; and 4) bulk-driven MOSFETs have a smaller transconductance and therefore a larger equivalent input inferred noise than a normal gate driven MOSFET. Bulk-driven MOSFETs are useful for designing low-voltage and low power circuits with a biomedical application. Lasanen et al. [39] implemented a 1 V, 0.5 W operational amplier for biomedical instrumentations using P-type bulk-driven input differential pair in a 0.35- m N-well CMOS process with threshold voltages being 0.5 V and 0.65 V for NMOSFETs and PMOSFETs, respectively. The design signicantly reduced the threshold voltage and increased the input common mode range of the amplier. To avoid the source to bulk and source to substrate leakage currents and the parasitic BJT latch-up, the aspect ratio of the bulk-driven MOSFET was de. Pan signed to be sufciently large to limit the maximum et al. [40] also proposed a novel OTA with dual bulk-driven input stage in a 0.35- m CMOS process with a 0.9 V supply and 9.9 W power consumption. The new scheme achieved a rail-to-rail input range and avoided the leakage current of conventional bulk-driven circuits. The bulk-driven MOSFET is a potential structure in low power and low voltage biomedical applications. 2) Floating Gate MOSFETs: Since oating gate MOS (FGMOS) structure was proposed as a nonvolatile memory device by Kahng and Sze in 1967 [41], it has been widely used in digital EPROM and EEPROM. The oating gate is surrounded by SiO without any electrical connection, which is capacitively coupled to the controlling gate. The input signal is applied to the controlling gate. The effective threshold voltage can be reduced to a small value by setting the input voltage properly. Thus, it has been found in low voltage and low power realm recently for the tunable and reduced threshold voltage.

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The most commonly used structure is multiple-input oating gate (MIFG) MOS transistor, as shown in Fig. 3(b). The voltage is given by [42] of the oating gate

Fig. 4. Main principle of log companding method [50].

(2) where is the number of the inputs, and are the th input capacitance and voltage, is the total capacitance seen , , are the parasitic capaciby the oating gate, tances between oating gate and drain, source and bulk, respecis the residential charge trapped in the oating tively, and gate. When (bulk and source terminals are , and , would be detergrounded), as the mined only by the controlling gate [42]. Assume threshold voltage according to the oating gate, which is equal to the threshold voltage of a normal MOSFET, the MOSFET . Considering , will be turned on as we have [42]

(3) where is the voltage of the input terminal, are the voltages of the controlling terminals. The transistor will if appropriate , are turn on even with a small chosen, that is the threshold according to controlling gate is largely reduced. Using MIFG MOSFETs, Villegas et al. [42] presented a transimpedance amplier that can be used to diagnose diseases by monitoring a certain type of chemicals. The amplier consumed 82.5, 9.825, and 47.325 W for currents varying from (1 pA, 0.25 nA), (0.25 nA, 62.5 nA), and (62.5 nA, 1 A), respectively. Mourabit et al. [43] proposed a sub-1.5 V, 2 W OTA-C lter based on subthreshold MIFG MOSFETs. The cutoff frequency was tunable from 0.5 to 200 Hz, which is the desirable range for most physiological signals. There are also some other low power designs using MIFG MOSFETs with a relatively low cutoff frequency that can be used for medical applications [44], [45]. It should be emphasized that the trapped charges in oating gates during fabrication will produce large dc offset, which can be solved by methods such as UV cleaning [46], tunneling, and hot electron injection [47] and layout design techniques [48]. Ramirez-Angulo et al. also proposed an approach based on quasi-oating gate transistors to remove the trapped charges at a low supply voltage [49]. C. Log Companding Technique Different from the techniques mentioned above, log companding aims to reduce power at the circuit level based on the current-voltage characteristics of semiconductor devices. The

principle of the technique is shown in Fig. 4, where stands for the companding function that usually follows an exponential law. The processing chain includes a y-x (usually I-V) compression and an x-y (usually V-I) expansion, which is therefore named companding [50]. The basic concept of the theory is to choose the I-domain input and output signals within given dynamic ranges, but to process the signals internally using an equivalent V-domain within compressed dynamic ranges. The reduction of the internal voltage dynamic range makes it very suitable for low voltage and low power applications. Log-domain circuits were originally realized with bipolar transistors for their exponential current versus voltage characteristics. However, with the development of CMOS process, realizing log-domain circuits with MOS transistors biased in the subthreshold region became popular, especially for low power design including biomedical applications. For instance, Gerosa et al. [51] presented a log-domain preamplier and lter for a pacemaker that dissipated at most 2.8 W. Bartolozzi et al. [52] proposed a current mode lter for neuromorphic system with less than 1 nW. Lim et al. [53] designed an amplier for recording ECG that consumed less than 20 W. III. LOW FREQUENCY DESIGN METHODS Most physiological signals are low frequency signals as illustrated in Fig. 1. Therefore, the circuits often need to be designed or ), which imply with large time constants ( that large capacitances, large resistances, and/or small transconductances (mostly referring to the transconductances of OTAs) have to be implemented. For example, using the UMC 0.13- m resistor ocCMOS process where a 1-pF capacitor and a 1cupy 10 mm and 10 mm , respectively, the minimum area to achieve a cutoff frequency of 1 Hz based on the equation is 0.8 mm , where a 400 pF capacitor and a 0.4 resistor are used. The total area of the resistor and capacitor is considerably large. Alternatively, a cutoff frequency of 1 Hz can also be implemented by a 100 pF capacitor and a 0.628 nA/V , assuming that 100 pF is transconductance based on the largest acceptable capacitor. However, designing OTAs with transconductances below 1 nA/V is also a challenge especially if noise performance, dynamic range and chip area are all considered. Some special techniques have been explored to solve the above problems. A. MOS Pseudo-Resistor A resistance of hundreds of mega ohms can be achieved when a MOSFET is biased in the subthreshold region. This kind of MOS resistor is commonly used together with a capacitor in neural recording circuits for clamping large dc drift at the recording site. The neural recording amplier proposed

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TABLE I OTA-C FILTERS USED FOR PROCESSING PHYSIOLOGICAL SIGNALS

Fig. 5. MOS pseudo-resistors: (a) common tunable MOS pseudo resistor [57], (b) balanced tunable MOS pseudo resistor [57], and (c) MOS-bipolar pseudo resistor [60].

by Chandran et al. [54] used an NMOSFET biased in subthreshold region and an electrode capacitance to achieve a cutoff frequency below 20 Hz. The amplier can tolerate a dc input voltage ranging from 0 to 0.4 V without sacricing the ac performance. Nevertheless, the design cannot reject negative dc inputs. Mohseni et al. [55] proposed an optimized neural recording amplier using the dc baseline stabilization scheme, where a PMOSFET biased in subthreshold region is used together with the recording probe capacitance of about 22 pF to bring the cutoff frequency below 50 Hz. The tolerable range of dc inputs was measured to be at least 0.25 V. In these two designs [54], [55], resistors were employed to bias the MOS resistors. These biasing resistors were laser trimmed to make the cutoff frequencies tunable. Olsson et al. [56] designed their neural recording amplier by using diode connected subthreshold NMOSFETs that had an equivalent resistance greater without using biasing circuit. The lower-band than 15.9 cutoff frequency was measured to be less than 10 Hz and the tolerable range of dc input voltages was 0.5 V. Since tuning a resistor by trimming is inconvenient and costly, a tunable MOS pseudo resistor was proposed [57], as shown in Fig. 5(a). By changing the gate voltage of the MOSFETs, the circuit can be used as a band-tunable extracellular neural chip for recording both eld potentials and action potentials. The tolerable dc input voltage range was measured to be 0.5 V. Considering this MOS resistor exhibits asymmetric and nonlinear resistance when the voltage across it varies, Zou et al. [58] proposed

a balanced tunable MOS pseudo resistor in their programmable biomedical sensor interface chip, as illustrated in Fig. 5(b). The two transistors can be turned on alternatively to achieve a symmetric incremental resistance curve. The resistance was claimed almost constant when the voltage across it changed. In addition, the MOS-bipolar device, which is a drain-gate shorted MOSFET, has also been proposed for implementing large resistance [59]. Take a PMOSFET as an example, with , it functions as a diode connected PMOSFET; negative , the parasitic BJT is turned on and works with positive as a diode connected BJT. Harrison et al. [60] employed this technique to design circuit with a low cutoff frequency. Two MOS-bipolar devices connected in series were used to reduce the distortion of large output signals, as shown in Fig. 5(c). The cutoff frequency of the amplier was 0.025 Hz, in which . the equivalent resistance of the device was larger than 10 This structure has been adopted in the neural recording amplier presented by Wattanapanitch et al. [61] and the bioamplier proposed by Gosselin et al. [62]. In addition, Lim et al. [53] proposed a high-pass lter using two oppositely connected MOS-bipolar devices and a 2-pF capacitor to achieve a cutoff frequency of 0.45 Hz, which was claimed to have better linearity than Harrisons conguration. B. Low Cutoff Frequency Filter Design 1) OTA-C Filter: OTA-C lters have been commonly used in processing physiological signals as shown in Table I, which lists some representative designs published recently. Table II summarizes several techniques that have been proposed to implement small transconductances for designing these lters with low cutoff frequency. Details of these techniques are presented as follows. a) Small transconductance OTA design: Current division technique has been proposed to reduce the small signal transconductances in voltage to current converters and Fig. 6(a)

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Fig. 6. OTAs based on (a) current division [69], (b) current cancellation [69], and (c) current division and current cancellation [63] techniques.

Fig. 7. (a) Generic series-parallel current mirror. Unit transistors are identical (b) OTA based on series-parallel current division technique [71].

M =M =M

to achieve effective copy factor

M = (SP)=(QR) [71] and

TABLE II TECHNIQUES FOR DESIGNING OTAS WITH SMALL TRANSCONDUCTANCE

partially cancelled at the output. The small signal transconductance of the OTA can be expressed as [69] (5) , and , are transconductances of where , is usually MN and M1 respectively. In order to reduce set to approach to 1. In fact, it is limited between 0.5 and 0.9 can be reduced to 10 A/V for in the order of [69]. 10 A/V. The above methods are insufcient to implement transconductances at the nV/A level. In order to get an even smaller transconductance, the above methods can be combined together as illustrated in Fig. 6(c). The current of MR, operating in triode region, is divided by MM, M1, and MN, most of which ows to , . The small signal transconducground when tance of the OTA can be written as [63] (6) This method has been used frequently when designing lters, e.g., the low-pass lter for medical applications [63], the lowpass notch lter for EEG system [65] and the lter for portable ECG detection [68], all of which achieved transconductances of a few nA/V. Another technique is Series-Parallel (SP) current division structure, which reduces the transconductance based on SP current mirror. The generic structure is shown in Fig. 7(a), where . Assume the copy factor is and for the amplier shown in Fig. 7(b), we obtain . In order to get a transconductance of pico level, a high division factor must be chosen [71]. This technique requires choosing a bias current to tradeoff between the transconductance and input linear range. On

shows an OTA using this method. The drain current of MR is divided by MM and M1, most of which ows to the ground . The small signal through MM when transconductance of the OTA is given by [69]

(4) where is the small signal drain-source conductance of , and are the MR, transconductances of MM and M1, respectively. When increases, the dc current of M1 and M2 decreases at the same rate, which will induce an increasing leakage current. As a result, the offset voltage caused by the leakage current cannot be omitted. Thus, there will be a tradeoff between transconductance and offset voltage when choosing . Current cancellation was rst presented by Garde [70] in bipolar OTAs design. Jose et al. [69] applied it into MOS ampliers. As shown in Fig. 6(b), the currents of M1 and MN are

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Fig. 8. Schematic of capacitor scaler [74]. Fig. 9. Current steering lter [75].

one hand, reducing the biased current is needed for a small transconductance. On the other hand, increasing the biased current widens the input linear range, which is approximated as [72], where is the subthreshold slope factor, is the inversion coefcient of MOSFET proporis the thermal voltage, and is tional to the bias current, the maximum acceptable relative error of the input differential current within the linear range, i.e., [72] for (7)

Fig. 10. Simple MOSFET switch modulator.

, is the transconductance of M1, as where shown in Fig. 7(b). By using this method, OTAs with transconductances varying from 33 pA/V to a few nA/V can be obtained [67], [71]. In addition to the above techniques, the OTA based on subthreshold MIFG MOS transistors in [43] achieved 15 p150 pA/V transconductances when the bias current ranged from 1 to 100 nA. The corresponding cutoff frequency of the OTA-C lter spanned from 0.2 to 15 Hz with an ultra power consumption of no more than 2 W. This work provides us a promising way in low frequency and low power designs. b) Large capacitor on chip: According to the Miller effect, the effective impedance can be reduced by increasing the input current while keeping the same input voltage. Specically, if the input current is sampled, amplied, and fed back into the input, the equivalent impedance will be scaled down with the current amplication factor [73], [74]. Impedance scaler, as shown in Fig. 8, is developed based on this concept. The small signal admittance is given by [63]

[63], [67]. A disadvantage of such capacitance multiplication techniques is the limited linear range it possessed, which is inversely proportional to the multiplication ratio. 2) Current Steering Filter: An R-MOSFET-C lter using current steering method is shown in Fig. 9, which was designed aiming to achieve a low cutoff frequency [75]

(10) The cutoff frequency can be tuned by changing the gate voltage , which in turn steered the current that ow from the of M1 capacitor to virtual ground. The gain of the lter was determined . The lter not only achieved a cutoff frequency of as by low as 1.8 Hz without off-chip components but also exhibited low distortion [75]. IV. LOW NOISE DESIGN METHODS Physiological signals are prone to be interfered by the noises caused by sensors, electrodes, environment, power supplies and power frequency, etc. Therefore, techniques must be employed to optimize the noise performance of the circuits. Chopper stabilization (CHS) is commonly used for processing bioelectrical signals, like EEG, ECG, and EMG. In CHS method, the signal is rstly modulated to a higher frenoise and then demodulated back quency where there is no to the baseband after amplication [76]. A simple MOSFET switch modulator is shown in Fig. 10. The differential difference chopper stabilization amplier (CHSDDA) is popular as an alternative instrumentation amplier. Chan et al. [77] proposed this topology for EEG recording to reduce the mismatches, noises, and offsets. The measured common mode rejection ratio (CMRR) with practical mismatch was relatively higher than three operational ampliers instrumentation amplier (3OPIA) and current mode instrumentation amplier (CMIA), which were simulated with 0.2% resistor mismatch and 0.2% transistor mismatch, respectively. In addition, some other ampliers designed for recording multichannel cortical signals [78], ENG [79], neural eld potentials [80],

(8) and are the small signal drain source conwhere ductances of MSN and MSPN respectively, is the ratio of the small signal transconductances of MSN and MS1 respectively, , and , are parasitic capacitors of the much corresponding node. By putting the pole and , higher than the pass-band frequency, reducing and omitting , (8) can be simplied as (9) A large equivalent capacitance can be achieved in a small chip area by adopting a large and small basic capacitor . For example, basic capacitors of 5 and 25 pF were used to achieve equivalent capacitances of 18200 and 125 pF, respectively

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EEG [81] achieved noise efciency factors (NEFs) of 3.35, 5.3, 4.6, 4.9 respectively when using the CHS method. Attention must be paid to the charge injection and clock feedthrough effects in simple MOS switches [17]. Charge injection usually introduces three types of errors in the output voltage of a MOS switch, the gain error, nonlinearity and dc offset [17]

A. Bioelectrical Signal Processing Cardiovascular diseases are considered to be the leading cause of death globally. ECG monitoring can be used to forecast possible heart diseases. ECG is a small amplitude, low frequency signal in the range of 0.54 mV and 0.01250 Hz [10]. It is usually affected by the noises from the skin-electrode interface, muscular activity, etc. High CMRR and low cutoff frequency ampliers are needed to detect the small differential signal. Several groups have developed ICs for ECG measurement. Lasanen et al. [84] implemented an ECG measurement chip in a 0.18- m CMOS process with 1 V1.8 V supply, 3 A averaged current and 82 dB CMRR for miniature devices like heart rate detector. There were only two electrodes in this circuit, and the analog ground was internally generated by the bias circuit. Wong et al. [85] implemented an ECG measurement chip with a driven-right-leg circuit in a 0.35- m CMOS process. The technique of using an electrode connected to the right leg as a reference has been widely used in discrete component circuits, but it was the rst time that the driven-right-leg circuit was implemented on chip. In addition, Fay et al. [86] proposed an ECG processing amplier in a 0.5 um process with 2.8 W power consumption and 90 dB CMRR, which used an active grounding electrode to attenuate the 60 Hz noise, weak inversion transistors to improve the noise efciency, and capacitor-based amplication to improve matching. Features of ECG, including P, Q, R, S, and T waves, can be attained in this design. EEG is another small amplitude (5300 V), low frequency (dc-150 Hz for scalp EEG) bioelectrical signal that plays an important role in diagnosing disorders like epilepsy, coma, stroke, and investigating cognitive state. Ng et al. [87] presented a 16-channel analog front-end chip for EEG/ECG monitoring. CHSDDIA previously mentioned was used in this work to achieve a high CMRR (115 dB) and a low input-referred noise (0.86 Vrms, 0.3150 Hz). Another example is the 8-channel EEG acquisition ASIC proposed by Refet et al. [88]. In this design, each channel utilized a new ac coupled chopper stabilized IA (ACCIA) with coarse-ne servoloop to improve the noise performance and reduce the power consumption. The design achieved 120 dB CMRR, 0.59 Vrms input-referred noise (0.5100 Hz) and consumed 200 W. Compared with the former work [87] (485 A from 1.5 V supply), the power consumption was largely reduced in this design (66 A from 3 V supply). Implantable neural recording systems with microelectrode arrays for observing the activity of the neurons in the brain are useful for understanding how the brain works. Many excellent designs have been published in this area, including a wireless 100-electrode neural recording system proposed by Harrison et al. [89] and a wireless 64-channel neural recording system published by Sodagar et al. [90]. The two systems are telemetry-powered systems that consumed 13.5 and 14.4 mW, respectively. In addition, there are some designs focusing on the front-end ampliers like the neural recording amplier designed for recording neural spikes and local eld potentials [61]. As mentioned previously, the amplier nearly achieved

(11) where is the Fermi potential in the semiconductor, is the body effect coefcient, is the gate oxide capaciis the hold capacitor. Efforts tance per unit area, and have been made to cancel the charge injection and improve the performance of the MOS switch modulator, such as adopting large shunting capacitor and slow transition time, using symmetrical capacitances at drain and source of the MOS switch with half-sized dummy switches, etc. [76]. Clock feedthrough usually introduces a constant offset voltage, which [16], where is the equals gate-source or gate-drain overlap capacitance per unit width, is the voltage during the high state of the clock signal. and In addition to CHS, Chan et al. employed auto-zeroing (AZ) in the amplier for cortical neural prostheses. The basic idea of AZ is sampling the noise and offset (in the sampling phase) and then subtracting it from the instantaneous value of signal (in the processing phase) either at the input or the output of the circuits [76]. AZ was claimed to perform better than CHS in reducing power consumption because the modulation frequency in CHS must be twice the input signal in order to meet the Nyquist criteria, resulting in a higher bandwidth and bias current [82]. An amplier using the AZ technique has to be disconnected from the input terminal in order to sample and hold its own offset and noise in the sampling phase. Therefore, the amplied signal is only available during the signal processing phase when using a single auto-zeroed amplier [76]. In addition, designers tend to use more specic ways to reduce noises, such as elaborate layout topology considerations and design special circuits. For example, for the high-PSRR microphone preamplier [83], several methods were employed to reduce the noise caused by power supply. The output of the buffer of the microphone was taken from the drain of the MOSFET instead of the source to avoid injecting noise from the power supply to the output due to the MOSFET parasitic coupling effect. In addition, wide-band power supply rejection was achieved by using a novel power supply lter. Another example is an OTA for neural recording [61], which was designed with a maximized transconductance under a given total current to achieve a low input-referred noise. The NEF of the amplier was 2.47. It nearly achieved the theoretical limit of the NEF (2.02) of an OTA that used a differential pair as an input stage. V. INTEGRATED CIRCUITS FOR PROCESSING DIFFERENT PHYSIOLOGICAL SIGNALS Different IC designs for processing different physiological signals have been published in recent years.

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Fig. 11. (a) Pacemaker [92]. (b) Bionic cochlea system [95], which usually includes microphone, transmitter, receiver/stimulator, electrodes and speech processor.

the theoretical limit of the NEF of an OTA that uses a differential pair as an input stage. Another important application is a pacemaker that is commonly used for treating bradycardia. The device monitors the hearts rate and rhythm by sensing cardiac signals and provides electrical stimulation when the heart does not beat or beats too slowly [91]. Fig. 11(a) shows a typical pacemaker. Gerosa et al. [51] proposed a fully integrated preamplier and lter for an implantable cardiac pacemaker to detect the spontaneous heart activity. This circuit was fabricated in a 0.35- m CMOS process with a 1.8 V supply voltage and 1.8 A current. Almost all the transistors were biased in the subthreshold region to meet the exponential I-V relationship required by log-domain approach to result in ultra low power consumption. Wong et al. [92] proposed a very low power IC for implantable pacemaker, which was fabricated in a 0.5- m CMOS process. Most of the transistors in the analog part worked in the deep subthreshold region. The device dissipated an average power of 8 W at approximately 2.8 V supply voltage and had an estimated longevity of 510 years with a primary battery. B. Acoustic Signal Processing The disturbance of the normal breathing process may cause severe metabolic, organic, and central nervous disorders or even death [93]. Small wearable devices with low power consumption are needed to monitor the respiration process and warn of the cessation of breathing. Corbishley et al. [29] proposed a nanopower OTA-C band-pass lter to be used in a wearable breathing detector for capturing the acoustic signal caused by breathing. The lter, which was designed with transconductance ampliers biased in the subthreshold and fabricated in a 0.35m CMOS process with a 1 V supply voltage, consumed only 70 nW. The acoustic signal received by the microphone can be rst processed by the band-pass lter before sending to the rectier, low-pass lter and comparator. By comparing with the processed signal with a predetermined threshold, the system will decide whether respiration is detected. An alarm signal can be sent if respiration ceases or the device is dislodged [29].

The incurable damage of some important organs, like ear, eye, and some nerves is suffering for people. Generating neural action potentials by electrical stimulations to control the dysfunctional organs is proved a promising way to relieve peoples pain. The rst example is bionic ear. The inner ear includes the cochlea and the vestibule, which is responsible for transmitting sound and inertia to the vestibulocochlear nerve, respectively. The bionic cochlea usually consists of an implanted module, including a receiver-stimulator and electrodes, and an external speech processor [94], as shown in Fig. 11(b). The sound is received and processed by the speech processor. The processed signal will then be transmitted to the internal module to stimulate the auditory nerve. In order to be more comfortable and convenient, the next generation bionic cochlea will be fully implantable. Sarpeshkar et al. [96] reported an ultra-low power programmable analog bionic ear processor, which aimed to be used in fully implantable bionic cochleas. Many techniques were used in this design to reduce power and improve noise performance, as mentioned in Section IV. The implant can be operated on a 100 mAh battery with a 1000 charge-anddischarge-cycle lifetime for 30 years. Another example is the 126 W cochlear chip for a totally implantable system designed by Georgiou et al. [97]. The speech processor and the stimulator were implemented on one mixed-signal chip with size and power consumption sufciently small for a fully implantable application. As another part of the inner ear, the vestibule is responsible for transmitting inertia to the vestibulocochlear nerve. A vestibular prosthesis, commonly includes an inertia sensor, interfacing, processing, and stimulating modules, brings another important function to bionic ears [98][100]. Heart sounds, noises generated by the closing of the heart valves, and the resultant ow of blood through them, are useful for diagnosing diseases such as stenosis that restricts the opening of a heart valve. A battery-free tag, which included a low power IC, an antenna and microphones, to wirelessly monitor heart sounds has been developed [101]. The IC consumed only 1 W. The tag was battery-less and powered by harvesting radiated RF energy. It was demonstrated that the tag can reliably measure heart rate through heart sounds at a distance up to 7 m from an FCC-compliant RF power source.

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It is worth mentioning that heart activity was monitored by acoustic and not electrical signals in this work such that no electrical contact is needed. C. Physical Quantity Processing Photoplethysmograhy is a noninvasive method to measure the volume changes in vessels and has been used in SpO evaluation [102], cufess blood pressure estimation [103], and heart rate measurements. Photoplethysmogram (PPG) is a very low frequency signal (0.517 Hz) and its ratio between the ac and dc components is as small as about 0.0010.015 [104], [105]. It is easily disturbed by motion artifact and environment noises. Wong et al. [75] presented a near-infrared heart rate measurement chip by processing PPG. A low-pass current steering lter mentioned in Section III was employed in this circuit to get a cutoff frequency as low as 0.25 Hz without off chip components. This is the rst chip for processing PPG. Bladder diseases may lead to various complications or even death. Many bladder diseases can be observed or predicted by long-term invasive monitoring of the bladder urine pressure for syndromes of urinary anomalisms. Wang et al. [106] proposed an invasive long term bladder urine pressure measuring system that included a controlling ASIC, a pressure sensor and a RF module. The ASIC was implemented in the TSMC 0.35- m CMOS process, and the whole system consumed 1.25 mV. The output voltage of the sensor that was proportional to the absolute pressure was processed by the ASIC, and then the data was wirelessly delivered to an external data analyzer for diagnosis. D. Chemical Quantity Processing Chemical sensors based on ion-sensitive eld effect transistors (ISFETs) have been widely used in ion concentration measurement. An ISFET is a MOS transistor with the gate connection separated from the device in the form of a reference electrode inserted into an aqueous solution which is in contact with the gate oxide [107]. The drain current of the ISFET can be expressed as a function of the hydrogen ion concentration both in strong inversion region and weak inversion region [108]. As an example, Pantelis et al. [109] proposed a silicon pancreatic beta cell, which was used for real-time glucose sensing and insulin release for diabetes. The silicon beta cell has been fabricated in the UMC 0.25- m CMOS process with a measured power consumption of 4.5 W. In this paper, the ISFET biased in the subthreshold region was employed to model the metabolic functions. The one-to-one relationship between hydrogen ions and glucose ions can be constructed according the reaction of glucose with the enzyme. By using the relation between hydrogen ion concentration and drain current of an ISFET, the connection between the glucose ion concentration and the drain current of the ISFET can be founded. VI. CONCLUSION In this paper, low power, low frequency, and low noise analog IC design techniques for processing physiological signals are reviewed and some excellent related designs are listed. It is envisaged that there will be a strong demand for medical ICs in an increasing number of novel medical applications, in addition to applications such as monitoring physiological parameters or

developing bionic organs. Moreover, the analog, digital, and RF modules as well as sensors or electrodes will be integrated or packaged into a system to perform multiple and more complex functions. New techniques for designing ICs of medical applications are therefore needed in order to improve the performance, lower the power consumption, and reduce the physical size of the wearable and implantable medical instrumentations. ACKNOWLEDGMENT The authors are grateful to the reviewers for their constructive comments and valuable inputs, which were useful in improving the quality of this paper. The authors are grateful to Standard Telecommunication Ltd., Jety Technology Ltd., Golden Meditech Company Ltd., Bird International Ltd., Bright Steps Corporation and PCCW for their support to the ITF projects. REFERENCES
[1] P. Bonato, Wearable sensors/systems and their impact on biomedical engineering, IEEE Eng. Med. Biol. Mag., vol. 22, no. 3, pp. 1820, May/Jun. 2003. [2] D. W. Ryoo, Y. S. Kim, and J. W. Lee, Wearable systems for service based on physiological signals, in Proc. 27th Conf. IEEE EMBS, Shanghai, China, 2005, pp. 24372440. [3] X. F. Teng and Y. T. Zhang, M-health: Trends in wearable medical devices, Chinese J. Med. Instrum., vol. 30, no. 5, pp. 330340, Sep. 2006. [4] A. Lymberis, Smart wearable systems for personalised health management: Current R&D and future challenges, in Proc. 25th Ann. Int. Conf. IEEE EMBS, Cancun, Mexico, 2003, pp. 37163719. [5] G. Trster, The agenda of wearable healthcare, in IMIA Yearbook of Medical Informatics 2005: Ubiquitous Health Care Systems. Stuttgart, Germany: Schattauer, 2004, pp. 125138. [6] J. E. Mezzich, Psychiatry for the person: Articulating medicines science and humanism, World Psychiatry, vol. 6, no. 2, pp. 6567, Jun. 2007. [7] X. F. Teng, Y. T. Zhang, C. C. Y. Poon, and P. Bonato, Wearable medical systems for p-health, IEEE Rev. Biomed. Eng., vol. 1, pp. 6274, 2008. [8] C. C. Y. Poon and Y. T. Zhang, Perspectives on high technologies for low-cost healthcare, IEEE Eng. Med. Biol., vol. 27, no. 5, pp. 4247, Oct. 2008. [9] Y. T. Zhang, C. C. Y. Poon, and E. Macpherson, Editorial note on health informatics, IEEE Trans. Inform. Technol. Biomed., vol. 13, no. 3, pp. 281283, May 2009. [10] J. G. Webster, Medical Instrumentation Application and Design. New York: Wiley, 1998, pp. 1011. [11] T. M. Seese, H. Harasaki, G. M. Saidel, and C. R. Davies, Characterization of tissue morphology, angiogenesis, and temperature in the adaptive response of muscle tissue to chronic heating, Lab. Invest., vol. 78, no. 12, pp. 15531562, 1998. [12] E. H. Liu, G. M. Saidel, and H. Harasaki, Model analysis of tissue responses to transient and chronic heating, Ann. Biomed. Eng., vol. 31, no. 8, pp. 10071014, Sep. 2003. [13] Radio electronics: Battery technology overview [Online]. Available: http://www.radio-electronics.com/info/data/battery-technology/tutorial-basics-overview.php [14] M. H. Miles, Recent advances in lithium battery technology, in Proc. Gallium Arsenide Integrated Circuit (GaAs IC) Symp., 23rd Annu. Technical Dig., Baltimore, MD, 2001, pp. 219222. [15] Alternative energy news: Battery technology [Online]. Available: http://www.alternative-energy-news.info/technology/battery-power/ [16] P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design. New York: Oxford Univ. Press, 2002, p. 99. [17] B. Razavi, Design of analog CMOS Integrated Circuits. Singapore: McGraw-Hill, 2002, pp. 2728. [18] R. R. Troutman and S. N. Chakravarti, Subthreshold characteristics of insulated-gate eld-effect transistors, IEEE Trans. Circuit Theory, vol. CT-20, pp. 659665, Nov. 1973. [19] R. R. Troutman, Subthreshold design considerations for insulatedgate eld-effect transistors, IEEE J. Solid-State Circuits, vol. SC-9, pp. 5560, Apr. 1974.

LI et al.: ANALOG INTEGRATED CIRCUITS DESIGN FOR PROCESSING PHYSIOLOGICAL SIGNALS

103

[20] E. Vittoz and J. Fellrath, CMOS analog integrated circuits based on weak inversion operation, IEEE J. Solid-State Circuits, vol. 12, no. 3, pp. 224231, Jun. 1977. [21] C. Jakobson, I. Bloom, and Y. Nemirovsky, 1/f noise in CMOS transistors for analog applications from subthreshold to saturation, SolidState Electron, vol. 42, no. 10, pp. 18071817, 1998. [22] D. J. Comer and D. T. Comer, Operation of analog MOS circuits in the weak or moderate inversion region, IEEE Trans. Education, vol. 47, no. 4, pp. 430435, Nov. 2004. [23] D. J. Comer and D. T. Comer, Using the weak inversion region to optimize input stage design of CMOS op amps, IEEE Trans. Circuits Syst. II: Expr. Briefs, vol. 51, no. 1, pp. 814, Jan. 2004. [24] T. M. Hollis, D. J. Comer, and D. T. Comer, Optimization of MOS amplier performance through channel length and inversion level selection, IEEE Trans. Circuits Syst. II: Expr. Briefs, vol. 52, no. 9, pp. 545549, Sep. 2005. [25] D. Bol, R. Ambroise, D. Flandre, and J. D. Legat, Interests and limitations of technology scaling for subthreshold logic, IEEE Trans. Very Large Scale Integration (VLSI) Syst., vol. 17, no. 10, pp. 15081519, Oct. 2009. [26] C. C. Enz, F. Krummenacher, and E. A. Vittoz, An analytical MOS transistor model valid in all regions of operation and dedicated to lowvoltage and low-current applications, Analog Integrat. Circuits Signal Process., vol. 8, no. 1, pp. 83114, Jul. 1995. [27] A. I. A. Cunha, M. C. Schneider, and C. Galup-Montoro, An MOS transistor model for analog circuit design, IEEE J. Solid-State Circuits, vol. 33, pp. 15101519, Oct. 1998. [28] S. S. Rajput and S. S. Jamuar, Low voltage analog circuit design techniques, IEEE Mag. Circuits Syst., vol. 2, no. 1, pp. 2442, 2002. [29] P. Corbishley and E. Rodriguez-Villegas, A nanopower bandpass lter for detection of an acoustic signal in a wearable breathing detector, IEEE Trans. Biomed. Circuits Syst., vol. 1, no. 3, pp. 163171, Sep. 2007. [30] J. Kim, M. S. Chae, and W. Liu, A 220 nW neural amplier for multichannel neural recording systems, in IEEE Int. Symp. Circuits Syst., Taipei, Taiwan, 2009, pp. 12571260. [31] E. Lopez-Morillo, R. G. Carvajal, F. Munoz, H. E. Gmili, A. LopezMartin, J. Ramirez-Angulo, and E. Rodriguez-Villegas, A 1.2 V 140 nW 10 bit sigma-delta modulator for electroencephalogram applications, IEEE Trans. Biomed. Circuits Syst., vol. 2, no. 3, pp. 223230, Sep. 2008. [32] R. H. Dennard, F. H. Gaensslen, H. N. Yu, V. L. Rideout, E. Bassous, and A. R. LeBlanc, Design of ion-implanted MOSFETs with very small physical dimensions, IEEE J. Solid-State Circuits, vol. SC-9, pp. 256268, 1974. [33] T. H. Ning, A perspective on the theory of MOSFET scaling and its impact, IEEE J. Solid-State Circuits Newslett., vol. 12, no. 1, pp. 2730, Jan. 2007. [34] A. Guzinski, M. Bialko, and J. C. Matheau, Body driven differential amplier for application in continuous time active-C ler, in Eur. Conf. Circuit Theory Design, Paris, France, 1987, pp. 315320. [35] Y. Haga, H. Zare-Hoseini, L. Berkovi, and I. Kale, Design of a 0.8 volt fully differential CMOS OTA using the bulk-driven technique, in IEEE Int. Symp. Circuits Syst., May 2326, 2005, pp. 220223. [36] Y. Haga, R. C. S. Morling, and I. Kale, A new bulk-driven input stage design for sub 1 volt CMOS opamps, in Int. Sym. IEEE Circuits Syst., Kos, Greece, 2006, pp. 15471550. [37] J. M. Carrillo, P.-A. Raquel, J. M. Valverde, J. F. Duque-Carrillo, and G. Torelli, Compact low-voltage rail-to-rail bulk-driven CMOS opamp for scaled technologies, in Eur. Conf. Circuit Theory Design, Antalya, 2009, pp. 263266. [38] E. Sanchez-Sinencio, Bulk Driven Transistors [Online]. Available: http://amsc.tamu.edu/ [39] K. Lasanen, E. Raisanen-Ruotsalainen, and J. Kostamovaara, A 1 V 5 uW CMOS opamp with bulk-driven input transistors, in Proc. 43rd IEEE Midwest Symp. Circuits System, Lansing, Michigan, pp. 10381041. [40] S. W. Pan, C. C. Chuang, C. H. Yang, and Y. S. Lai, A novel OTA with dual bulk-driven input stage, in Proc. Int. Sym. IEEE Circuits Syst., Taipei, Taiwan, 2009, pp. 27212724. [41] D. Kahng and S. M. Sze, A oating-gate and its application to memory devices, Bell Syst. Tech. J., vol. 46, no. 4, pp. 12881295, 1967. [42] E. R. Villegas, A low-power wide range transimpedance amplier for biochemical sensing, in Proc. 29th Annu. Int. Conf. IEEE Eng. Medicine Biol. Soc., Lyon, France, Aug. 2007, pp. 26732676.

[43] A. E. Mourabit, G. N. Lu, and P. Pittet, Rail-to-rail differential linear range OTA with pico-A/V transconductance for sub-Hertz OTA-C lter, in Proc. 16th Int. Conf. Microelectronics, Tunis, 2004, pp. 647650. [44] E. Rodriguez-Villegas, A. Yufera, and A. Rueda, A 1.25 V micropower Gm-C lter based on FGMOS transistors operating in weak inversion, IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 100111, Jan. 2004. [45] E. Rodriguez-Villegas, A. Yufera, and A. Rueda, A 1 V micropower log-domain integrator based on FGMOS transistors operating in weak inversion, IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 256259, Jan. 2004. [46] J. Ramirez-Angulo, R. G. Carvajal, J. Tombs, and A. Torralba, Low voltage CMOS opamp with rail-to-rail input and output signal swing for continuous-time signal processing using multiple-input oating-gate transistors, IEEE Trans. Circuits Syst. II, vol. 48, no. 1, pp. 111116, Jan. 2001. [47] P. Hasler, Foundations of learning in analog VLSI, Ph.D. dissertation, California Inst. Technology, Pasadena, CA, 1997. [48] E. Rodriguez-Villegas and H. Barnes, Solution to trapped charge in FGMOS transistors, IEE Electron. Lett., vol. 39, no. 19, pp. 14161417, Sep. 2003. [49] J. Ramirez-Angulo, C. A. Urquidi, R. Gonzalez-Carvajal, A. Torralba, and A. Lopez-Martin, A new family of very low-voltage analog circuits based on quasi-oating-gate transistors, IEEE Trans. Circuits Systems II: Analog Digital Signal Processing, vol. 50, no. 5, pp. 214220, May 2003. [50] F. Serra-Graells, A. Rueda, and J. L. Huertas, Low-Voltage CMOS Log Companding Analog Design. Hingham, MA: Kluwer, 2003, pp. 510. [51] A. Gerosa, A. Maniero, and A. Neviani, A fully integrated dual-channel log-domain programmable preamplier and lter for an implantable cardiac pacemaker, IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 51, no. 10, pp. 19161925, Oct. 2004. [52] C. Bartolozzi, S. Mitra, and G. Indiveri, An ultra low power current-mode lter for neuromorphic systems and biomedical signal processing, in Proc. IEEE Biomedical Circuits Syst. Conf., London, U.K., 2006, pp. 130133. [53] E. C. M. Lim, X. D. Zou, Y. J Zheng, and J. Tan, Design of lowpower low-voltage biomedical amplier for electrocardiogram signal recording, in Proc. IEEE Biomedical Circuits Syst. Conf., Montral, Canada, 2007, pp. 191194. [54] A. P. Chandran, K. Naja, and K. D. Wise, A new dc baseline stabilization scheme for neural recording microprobes, in Proc. 21th Conf. IEEE EMBS, Atlanta, GA, 1999, p. 386. [55] P. Mohseni and K. Naja, A fully integrated neural recording amplier with DC input stabilization, IEEE Trans. Biomed. Eng., vol. 51, no. 5, pp. 832837, May 2004. [56] R. H. Olsson, III, M. N. Gulari, and K. D. Wise, Silicon neural recording arrays with on-chip electronics for in vivo data acquisition, in Proc. 2nd Annu. Int. Conf. Microtechnologies Medicine Biology, Madison, WI, 2002, pp. 237240. [57] R. H. Olsson, III, D. L. Buhl, A. M. Sirota, G. Buzsaki, and K. D. Wise, Band-tunable and multiplexed integrated circuits for simultaneous recording and stimulation with microelectrode arrays, IEEE Trans. Biomed. Eng., vol. 52, no. 7, pp. 13031311, Jul. 2005. [58] X. D. Zou, X. Y. Xu, L. B. Yao, and Y. Lian, A 1 V 450 nW fully integrated programmable biomedical sensor interface chip, IEEE J. Solid-State Circuit, vol. 44, no. 4, pp. 10671077, Apr. 2009. [59] T. Delbrck and C. A. Mead, Analog VLSI adaptive, logarithmic wide dynamic range photoreceptor, in Proc. Int. Sym. IEEE Circuits Syst., London, U.K., 1994, pp. 339342. [60] R. R. Harrison and C. Charles, A low-power low-noise CMOS amplier for neural recording applications, IEEE J. Solid-State Circuits, vol. 38, no. 6, pp. 958965, Jun. 2003. [61] W. Wattanapanitch, M. Fee, and R. Sarpeshkar, An energy-efcient micropower neural recording amplier, IEEE Trans. Biomed. Circuits Syst., vol. 1, no. 2, pp. 136147, Jun. 2007. [62] B. Gosselin, M. Sawan, and C. A. Chapman, A low-power integrated bioamplier with active low-frequency suppression, IEEE Trans. Biomed. Circuits Syst., vol. 1, no. 3, pp. 184192, Sep. 2007. [63] S. Solis-Bustos, J. Silva-Martinez, F. Maloberti, and E. SanchezSinencio, A 60 dB dynamic-range CMOS sixth-order 2.4 Hz low-pass lter for medical applications, IEEE Trans. Circuits Syst. II, vol. 47, no. 12, pp. 13911398, Dec. 2000.

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[64] C. D. Salthouse and R. Sarpeshkar, A practical micropower programmable bandpass lter for use in bionic ears, IEEE J. Solid-State Circuits, vol. 38, no. 1, pp. 6370, Jan. 2003. [65] X. B. Qian, Y. P. Xu, and X. P. Li, A CMOS continuous-time lowpass notch lter for EEG systems, Analog Integrated Circuits Signal Processing, vol. 44, no. 3, pp. 231238, Sep. 2005. [66] O. Omeni, E. Rodriguez-Villegas, and C. Toumazou, A micropower CMOS continuous-time lter with on-chip automatic tuning, IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 52, no. 4, pp. 695705, Apr. 2005. [67] C. L. Hsu, M. H. Ho, Y. K. Wu, and T. H. Chen, Design of lowfrequency low-pass lters for biomedical applications, in Proc. Asia Pacic Conf. IEEE Circuits Systems, Singapore, 2006, pp. 690695. [68] S. Y. Lee, C. J. Cheng, C. P. Wang, and W. C. Kao, Low-power signal processing devices for portable ECG detection, in Proc. 25th Ann. Int. Conf. IEEE EMBS, British Columbia, Canada, 2008, pp. 16831686. [69] J. Silva-Martnez and J. Salcedo-Suer, IC voltage-to-current transducers with very-small transconductance, Analog Inte. Circ. Signal Processing, vol. 13, no. 3, pp. 285293, 1997. [70] P. Garde, Transconductance cancellation for operational ampliers, IEEE J. Solid-State Circuits, vol. 12, no. 3, pp. 310311, Jun. 1977. [71] A. Arnaud, R. Fiorell, and C. Galup-Montoro, Nanowatt, sub-ns OTAs, with sub-10-mV input offset, using series-parallel current mirrors, IEEE J. Solid-State Circuits, vol. 41, no. 9, pp. 20092018, Set. 2006. [72] A. Arnaud and C. Galup-Montoro, Pico-A/V range CMOS transconductors using series-parallel current division, Electron. Lett., vol. 39, no. 18, pp. 12951296, Sep. 2003. [73] J. Silva-Martinez and A. Vazquez-Gonzalez, Impedance scalers for IC active lters, in Proc. Int. Sym. IEEE Circuits Systems, Monterey, CA, 1998, pp. 151154. [74] J. Silva-Martinez and S. Solis-Bustos, Design considerations for high performance very low frequency lters, in Proc. Int. Sym. IEEE Circuits Systems, Orlando, FL, 1999, pp. 648651. [75] A. K. Y. Wong, K. P. Pun, Y. T. Zhang, and K. Hung, A near-infrared heart rate measurement IC with very low cutoff frequency using current steering technique, IEEE Trans. Circuits Syst. I, vol. 52, no. 12, pp. 26422647, Dec. 2005. [76] C. C. Enz and G. C. Temes, Circuit techniques for reducing the effects of op-amp imperfections: Autozeroing, correlated double sampling, and chopper stabilization, Proc. IEEE, no. 8, pp. 15841614, Aug. 1996. [77] P. K. Chan, K. A. Ng, and X. L. Zhang, CMOS chopper-stabilized differential difference amplier for biomedical integrated circuits, in Proc. 47th Midwest Symp. Circuits Syst., Hiroshima, Japan, 2004, pp. 2528. [78] B. Gosselin, V. Simard, and M. Sawan, An ultra low-power chopper stabilized front-end for multichannel cortical signals recording, in Proc. Conf. Canadian Electrical Computer Engineering, 2004, pp. 22592262. [79] A. Uranga, X. Navarro, and N. Barniol, Integrated CMOS amplier for ENG signal recording, IEEE Trans. Biomed. Eng., vol. 51, no. 12, pp. 21882194, Dec. 2004. [80] T. Denison, K. Consoer, W. Santa, A. T. Avestruz, J. Cooley, and A. Kelly, A 2 uW 100 nV/rtHz chopper-stabilized instrumentation amplier for chronic measurement of neural eld potentials, IEEE J. Solid-State Circuits, vol. 42, no. 12, pp. 29342945, Dec. 2007. [81] T. Denison, K. Consoer, A. Kelly, A. Hachenburg, and W. Santa, A 2.2 uW 94 nV= Hz, chopper-stabilized instrumentation amplier for EEG detection in chronic implants, in Proc. Int. Conf. IEEE SolidState Circuits, San Francisco, CA, 2007, pp. 162594. [82] C. H. Chan, J. Wills, J. LaCoss, J. J. Granacki, and J. Choma, A micropower low-noise auto-zeroing CMOS amplier for cortical neural prostheses, in Proc. Conf. IEEE Biomedical Circuits Systems, London, U.K., 2006, pp. 214217. [83] M. W. Baker and R. Sarpeshkar, A low-power high-PSRR currentmode microphone preamplier, IEEE J. Solid-State Circuits, vol. 38, no. 10, pp. 16711678, Oct. 2003. [84] K. Lasanen and J. Kostamovaara, A 1 V analog CMOS front-end for detecting QRS complexes in a cardiac signal, IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 52, no. 12, pp. 25842594, Dec. 2005. [85] A. K. Y. Wong, P. Pun, Y. T. Zhang, and C. S. Choy, An ECG measurement IC using driven-right-leg circuit, in IEEE Int. Symp. Circuits Syst., Island of Kos, Greece, 2006, pp. 345348. [86] L. Fay, V. Misra, and R. Sarpeshkar, A micropower electrocardiogram amplier, IEEE Trans. Biomed. Circuits Syst., vol. 3, no. 5, pp. 312320, Oct. 2009.

[87] K. A. Ng and P. K. Chan, A CMOS analog front-end IC for portable EEG/ECG monitoring applications, IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 52, no. 11, pp. 23352347, Nov. 2005. [88] R. F. Yazicioglu, P. Merken, R. Puers, and C. V. Hoof, A 200 uW eight-channel EEG acquisition ASIC for ambulatory EEG systems, IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 30253038, Dec. 2008. [89] R. R. Harrison, P. T. Watkins, R. J. Kier, R. O. Lovejoy, D. J. Black, B. Greger, and F. Solzbacher, A low-power integrated circuit for a wireless 100-electrode neural recording system, IEEE J. Solid-State Circuits, vol. 42, no. 1, pp. 123133, Jan. 2007. [90] A. M. Sodagar, G. E. Perlin, Y. Yao, K. Naja, and K. D. Wise, An implantable 64-channel wireless microsystem for single-unit neural recording, IEEE J. Solid-State Circuits, vol. 44, no. 9, pp. 25912604, Sep. 2009. [91] M. A. Wood and K. A. Ellenbogen, Cardiac pacemakers from the patients perspective, Circulation, vol. 105, pp. 21362138, May 2002. [92] L. S. Y. Wong, S. Hossain, A. Ta, J. Edvinsson, D. H. Rivas, and H. Naas, A very low-power CMOS mixed-signal IC for implantable pacemaker applications, IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 24462456, Dec. 2004. [93] P. Varady, T. Micsik, S. Benedek, and Z. Benyo, A novel method for the detection of apnea and hypopnea events in respiration signals, IEEE Trans. Biomed. Eng., vol. 49, no. 9, pp. 936942, Sep. 2002. [94] W. Germanovix and C. Toumazou, Design of a micropower currentmode log-domain analog cochlear implant, IEEE Trans. Circuits Syst. II: Analog Digital Signal Processing, vol. 47, no. 10, pp. 10231046, Oct. 2000. [95] Kidshealth [Online]. Available: http://kidshealth.org/parent/general/eyes/cochlear.html [96] R. Sarpeshkar, C. Salthouse, J. J. Sit, M. W. Baker, S. M. Zhak, T. K. T. Lu, L. Turicchia, and S. Balster, An ultra-low-power programmable analog bionic ear processor, IEEE Trans. Biomed. Eng., vol. 52, no. 4, pp. 711727, Apr. 2005. [97] J. Georgiou and C. Toumazou, A 126-uW cochlear chip for a totally implantable system, IEEE J. Solid-State Circuits, vol. 40, no. 2, pp. 430443, Feb. 2005. [98] T. G. Constandinou, J. Georgiou, and C. Toumazou, A fully-integrated semicircular canal processor for an implantable vestibular prosthesis, in Proc. 15th Int. Conf. IEEE Electronics, Circuits Syst., St. Juliens, 2008, pp. 8184. [99] T. G. Constandinou, J. Georgiou, and C. Toumazou, A micropower front-end interface for differential-capacitive sensor systems, in Proc. IEEE ISCAS, Seattle, WA, 2008, pp. 24742477. [100] T. G. Constandinou, J. Georgiou, and C. Toumazou, A partial-current-steering biphasic stimulation driver for neural prostheses, in Proc. IEEE ISCAS, Seattle, WA, 2008, pp. 25062509. [101] S. Mandal, L. Turicchia, and R. Sarpeshkar, A battery-free tag for wireless monitoring of heart sounds, in Proc. BSN 2009, Berkeley, CA, 2009, pp. 201206. [102] Y. S. Yan and Y. T. Zhang, A model-based artifact reduction method for the non-invasive estimation of blood oxygen saturation, in Proc. Int. Workshop IEEE Computer Architectures for Machine Perception, 2003, pp. 9092. [103] C. C. Y. Poon, Y. T. Zhang, G. Wong, and W. S. Poon, The beat-to-beat relationship between pulse transit time and systolic blood pressure, in Proc. Int. Conf. Technology Applications in Biomedicine, Shenzhen, China, 2008, pp. 342343. [104] A. K. Y. Wong, K. P. Pun, Y. T. Zhang, and K. N. Leung, A low-power CMOS front-end for photoplethysmographic signal acquisition with robust dc photocurrent rejection, IEEE Trans. Biomed. Circuits Syst., vol. 2, no. 4, pp. 280288, Dec. 2008. [105] P. D. Mannheimer, J. R. Cascini, M. E. Fein, and S. L. Nierlich, Wavelength selection for low-saturation pulse oximetry, IEEE Trans. Biomed. Eng., vol. 44, no. 3, pp. 148158, Mar. 1997. [106] C. C. Wang, C. C. Huang, J. S. Liou, Y. J. Ciou, I. Y. Huang, C. P. Li, Y. C. Lee, and W. J. Wu, A mini-invasive long-term bladder urine pressure measurement ASIC and system, IEEE Trans. Biomed. Circuits Syst., vol. 2, no. 1, pp. 4449, Mar. 2008. [107] P. Bergveld, Thirty years of isfetologyWhat happened in the past 30 years and what may happen in the next 30 years, Sens. Actuators B-Chem., vol. 88, no. 1, Jan. 2003. [108] L. Shepherd and C. Toumazou, Weak inversion ISFETs for ultra-low power biochemical sensing and real-time analysis, Sensors Actuators B: Chemical, vol. 107, no. 1, pp. 468473, May 2005. [109] P. Georgiou and C. Toumazou, A silicon pancreatic beta cell for diabetes, IEEE Trans. Biomed. Circuits Syst., vol. 1, no. 1, pp. 3949, Mar. 2007.

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Yan Li received the B.E. and M.E. degrees from Liaoning University, Shenyang, China, in 2004 and 2007, respectively. She is currently working toward the Ph.D. degree at the Key Laboratory for Biomedical Informatics and Health Engineering, Chinese Academy of Sciences, Shenzhen, China, and SIATInstitute of Biomedical and Health Engineering of Chinese Academy of Sciences, Shenzhen, China. She is also a Research Assistant of the Division of Biomedical Engineering and the Joint Research Center for Biomedical Engineering at the Chinese University of Hong Kong, Hong Kong. Her current research interests include low power analog integrated circuit design of medical applications.

Carmen C. Y. Poon (M08) received the B.A.Sc. degree in engineering science (biomedical option) and the M.A.Sc. degree in biomedical engineering from the University of Toronto, ON, Canada, and the Ph.D. degree from The Chinese University of Hong Kong, Hong Kong. She is currently a Research Assistant Professor at The Chinese University of Hong Kong. Her research interests include biosignal processing, biosystem modeling, and development of wearable medical devices and body sensor network for telemedicine, m-Health, and p-Health. Dr. Poon is as an Associate Editor of the IEEE TRANSACTIONS ON INFORMATION TECHNOLOGY IN BIOMEDICINE.

Yuan-Ting Zhang (M90SM93F06) received the M.S. degree from Shandong University, Jinan, China, and the Ph.D. degree from the University of New Brunswick, Fredericton, NB, Canada, in 1990. He is currently Head of the Division of Biomedical Engineering and Director of the Joint Research Center for Biomedical Engineering at the Chinese University of Hong Kong, Hong Kong. He also serves currently as the Director of Key Laboratory for Biomedical Informatics and Health Engineering of Chinese Academy of Sciences and Director of the SIATInstitute of Biomedical and Health Engineering of Chinese Academy of Science. He was a Research Associate and Adjunct Assistant Professor at the University of Calgary, Calgary, AB, Canada, from 1989 to 1994. He chaired the Biomedical Division of Hong Kong Institution of Engineers in 1996/1997 and 2000/2001. His current research interests include neural engineering, health informatics, THz imaging, and wearable medical devices and body sensor networks particularly for mobile health. He has published more than 300 scientic articles in the area of biomedical engineering. Dr. Zhang was the Technical Program Chair of the 20th Annual International Conference in 1998 and the General Conference Chair of the 27th Annual International Conference in 2005. He served the TPC Chair of IEEE-EMBS Summer School and Symposium on Medical Devices and Biosensors (ISSS-MDBS) in 2006 and 2007. He was elected as an IEEE-EMBS AdCom member in 1999 and served as Vice-President (Conferences) in 2000. He was an honorary advisor of Hong Kong Medical and Healthcare Device Manufacture Association. He served as Associate Editor for IEEE TRANSACTIONS ON BIOMEDICAL ENGINEERING and IEEE TRANSACTIONS ON MOBILE COMPUTING. He was also the Guest Editor of IEEE Communications Magazine and IEEE TRANSACTIONS ON INFORMATION TECHNOLOGY IN BIOMEDICINE. He currently serves as the Editor-in-Chief of IEEE TRANSACTIONS ON INFORMATION TECHNOLOGY IN BIOMEDICINE and Associate Editor of the Journal of NeuroEngineering and Rehabilitation. He is also on a number of editorial boards, the Book Series of Biomedical Engineering published by the IEEE Press, and the IEEE-EMBS Technical Committee of Wearable Systems and Sensors. He is a Fellow of the International Academy of Medicinal and Biological Engineering and the American Institute for Medical and Biological Engineering.