NATIONAL INSTITUTE OF SCIENCE & TECHNOLOGY

MCA 2nd Semester, 2012 Batch Exam: 1st Internal Test Subject Code & Name: MCC202 COMPUTER ARCHITECTURE & ORGANIZATION Time: 2 Hrs Max. Marks: 80 Examination Superintendent: Santosh Kr Kar Name of the Paper Setter: Tapas Kr Bayen Date of Examination: 09/04/2013

1. Answer the following in brief a. b. c. d. e. f. g. h. i. j.

2x10 = 20

State the bottleneck of von-Newman architecture. How can you differentiate data and instruction? Why data bus is bidirectional and address bus is unidirectional? How set associative memory mapping is overcome the disadvantages of full associative mapping? What is the main function of control bus? How can you store the data in the little-endian format? Give an example. Temporary register is invisible to the user Explain. What do you mean by op-code and operand? What is the difference between instruction cycle and machine cycle? What are differences between memory and register?

2. a) Write down the differences between system software and application software. b) Harvard architecture overcomes the bottleneck of von-Newman architecture justify your answer. c) Draw a functional diagram for a computer. d) Write down the steps to execute an instruction. 2+3+4+3=12 3. a) Write down the functions of MDR and MAR. b) How can you store a three byte instruction in your computer, explain with an example.

*** Let, the content of R1=100(memory address). c) MOV R3, (R1) Values of memory addresses are given the following way: MOV R4, R1 MOV R2, 15(R1) 100=36, 110=25, 115=30, 120=56 ADD R2, R3 Find the corresponding value of the registers after the execution of the instructions (consider it as a little-endian format). d) How can you calculate an effective address for an auto increment addressing mode? 3+3+4+2=12 4. a) Suppose, a virtual computer has 32 main memory block and cache memory has 8 block frame. Draw the direct mapping technique to map the blocks. b) Cache memory overcomes the speed gap between processor and primary memory explain. c) What do you mean by hit ratio and how it would be affected if the block size is increased? Show it graphically. d) write back policy is better than the write through policy justify 4+3+3+2=12 5. a) Write down the difference between RISC and SISC. b) What is the function of PC an SP at time of execution of an instruction? c) How split caches enhance the speed of a computer? d)Differentiate SDRAM and DRAM 4*3=12
6. Write short notes: a) b) c) d) Memory pyramid Cache performance DDRRAM Big-endian and little-endian 4*3=12