Test Paper-1 Digital Electronics

Source Book: GATE Multiple Choice Questions ECE Author: RK Kanodia ISBN: 9788192276205 Publisher : Nodia and Company Visit us at: www.nodia.co.in Edition: 6th

Q. No. 1 - 10 Carry One Mark Each

MCQ 1.1

11001, 1001 and 11001 correspond to the 2s complement representation of the following set of numbers (A) 25, 9 and 57 respectively (B) 6, 6 and 6 respectively (C) 7, 7 and 7 respectively (D) 25, 9 and 57 respectively All are 2s complement of 7 00110 & 11001 + 1 00111 = 7 10 1001 & 0110 + 1 0111

SOL 1.1

= 7 10

111001

&

000110 + 1 000111 = 7 10

Hence (C) is correct option.

MCQ 1.2

To implement Y = ABCD using only two-input NAND gates, minimum number of requirement of (A) 3 (B) 4 (C) 5 (D) 6

SOL 1.2

The circuit is as follows

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Hence (D) is correct option.

MCQ 1.3

A four-variable switching function has minterms m6 and m 9 . If the literals in these minterms are complemented, the corresponding minterm numbers are (A) m 3 and m 0 (B) m 9 and m6 (C) m2 and m 0 (D) m6 and m 9

SOL 1.3

Hence (B) is correct option. m6 = ABCD , m 9 = ABC D After complementing literal ml 6 = ABC D = m 9 , ml 9 = ABCD = m 6 The network shown below implements

MCQ 1.4

(A) NOR gate (C) XOR gate

SOL 1.4

(B) NAND gate (D) XNOR gate

Hence (B) is correct option. f1 = C D + CB + CB , S = F1 f = f1 + f1 A = CB + CBA = CB + A = C + B + A = ABC Consider a circuit shown in figure. The circuit functions as

MCQ 1.5

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(A) D-flip-flop (C) Output remains stable at '1'

SOL 1.5

(B) T-flip-flop (D) Output remains stable at '0'

From the combinational logic Let D is input, Qn is present state, Qn + 1 is next state, then R = D 5 Q, S = D 5 Q Characteristic equation of R-S flip-flop is given by Qn + 1 = S + RQn So,Qn + 1 = (D + Qn) + (D 5 Qn) Qn = (D 5 Qn) + (D 5 Qn) Qn = (D 5 Qn) (1 5 Qn) = (D 5 Qn) = DQ n + DQn For D = 0 , Qn + 1 = Qn D = 1, Qn + 1 = Qn So, the circuit function as a T-flip flop. Hence (B) is correct option. To count from 0 to 1024 the number of required flip-flop is (A) 10 (B) 11 (C) 12 (D) 13

MCQ 1.6

SOL 1.6

10 flip-flop will count from 0 to 1023. Hence 11 flip-flop are required to count from 0 to 1024. Hence (B) is correct option. The circuit shown below is a

MCQ 1.7

(A) NAND (C) AND

(B) NOR (D) OR

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If either one or both the inputs are V (0) = 0 V the corresponding FET will be OFF, the voltage across the load FET will be 0 V, hence the output is VDD . If both inputs are V (1) = VDD , both M 1 and M 2 are ON and the output is V (0) = 0 V. It satisfy NAND gate. Hence (A) is correct option. For the given logic families, correct order of their increasing noise margin is (A) RTL, ECL, MOS, DTL (B) RTL, ECL, DTL, MOS (C) ECL, RTL, MOS, DTL (D) ECL, RTL, DTL, MOS

MCQ 1.8

SOL 1.8

The correct order of increasing noise is RTL, ECL, DTL, MOS. Hence (B) is correct option. The full scale output of a DAC is 10 mA. If resolution is to be less than 40 A , then required bits are (A) 11 (B) 10 (C) 8 (D) 9

MCQ 1.9

SOL 1.9

Hence (C) is correct option. Resolution = 40 A The step required = 10m = 250 40 Therefore is requires 8 bits. Which one of the following is NOT a vectored interrupted ? (A) TRAP (B) INTR (C) RST 3 (D) RST 7.5

MCQ 1.10

SOL 1.10

Vectored interrupts are those interrupts in which program control transfer to a fixed location. In non vectored interrupts the location is not fixed. Here INTR is a non-vectored interrupt. Hence (B) is correct option.

Q. No. 11- 21 Carry Two Marks Each

MCQ 1.11

Consider the following loop LXI H, 000AH LOOP : DCX B MOV A, B ORA C JNZ LOOP This loop will be executed (A) 1 time

(B) 10 times

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(C) 11 times
SOL 1.11

(D) infinite times ; ; ; ; ; 00 " C, 0AH " B CB - 1 " B, flag not affected B"A A OR C " A, set flag

Hence (B) is correct option. LXI B, 000 AH LOOP : DCX B

MOV A, B ORA C JNZ LOOP Hence this loop will be executed 0AH or ten times. Hence (B) is correct option.
MCQ 1.12

A 555 IC is connected as shown below. The range of oscillation frequency is

(A) 607 kHz < f < 1.41 kHz (C) 627 Hz # f # 4.81 kHz
SOL 1.12

(B) 208 kHz # f # 496 kHz (D) 5 kHz # f # 9.4 kHz

Hence (C) is correct option. 1 f = 0.693 (RA + 2RB) C RA = R1 = 10 k RB = R2 + xR 3 & 10k < RB # 110k f min = f max 1 = 627 Hz 0.693 {10k + 2 (110k)} 0.01 1 = = 4.81 kHz 0.693 {10k + 2 (10k)} 0.01

MCQ 1.13

In the circuit shown in figure below the output G is

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(A) G = AC + BD (C) G = A 5 D
SOL 1.13

(B) G = AB + CD (D) G = B 5 C

If either A or B is low, then diode D1 or D2 will conduct, and point E will be at low. If both A and B are high, diode D1 and D2 both are off, and point E is at high. Thus D1 and D2 form the AND function E = AB and similarly F = CD D5 and D6 form a OR gate, so G = E+F, G = AB + CD Hence (B) is correct option. A 4-bit right shift register is initialized to value 1000 for (Q3, Q2, Q1, Q0). The D input is derived from Q 0, Q2 and Q 3 through two XOR gates as shown in fig. below. The pattern 1000 will appear at

MCQ 1.14

(A) 3rd pulse (C) 6th pulse

SOL 1.14

(B) 7th pulse (D) 4 th pulse

After t = t1 , at the first rising edge of clock, the output of shift register is 0110, which is input to address line of ROM. At 0110 (6) data 1010 is stored which will be on bus. At next rising edge of clock 1010 is applied to register. So at this time data stored in ROM at 1010 (10), 1000 will be on bus. Hence (C) is correct option.

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For the logic circuit shown below the output Y is

(A) A 5 B (C) A 5 B 5 C
SOL 1.15

(B) A 5 B (D) A 5 B 5 C

Output is 1 when even parity Therefore Y = A 5 B 5 C Hence (D) is correct option. Consider the signed binary number A = 01000110 and B = 11010011, where B is in 2s complement and MSB is the sign bit. In list-I operation is given and is List-II resultant binary number is given List - I P. A + B Q. A B R. B A S. A B The correct P (A) 5 (B) 6 (C) 6 (D) 5 match Q 7 3 7 3 is R 4 1 1 4 List - II 1. 1 0 0 0 1 1 0 1 2. 1 1 1 0 0 1 1 1 3. 0 1 1 1 0 0 1 1 4. 1 0 0 0 1 1 1 0 5. 0 0 0 1 1 0 1 0 6. 0 0 0 1 1 0 0 1 7. 0 0 0 1 1 0 0 1 8. 0 1 0 1 1 0 1 1 S 2 2 3 2

MCQ 1.16

SOL 1.16

Here A, B are 2s complement A + B, A B 01000110 + 11010011 1 00011001

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Discard the carry 1 A AB = A+B, B

01000110 + 00101101 01110011 11010011 + 10111010 1 11000110 10111010 + 00101101 11100111

B A,

B A

Discard the carry 1 A B = A + B , A B

Hence (B) is correct option.

MCQ 1.17

The CMOS circuit shown below implements the logic function

(A) AB + CD + E (C) AB + CD + E
SOL 1.17

(B) (A + B) (C + D) E (D) (A + B) (C + D) E

If input E is LOW, output will not be LOW. It must be HIGH. Option (B) satisfy this condition. Hence (B) is correct option.

MCQ 1.18

Consider a binary weighted n -bit D/A converter shown in the following circuit of figure. What is the tolerance of resistance to limit the output error to the equivalent of ! 1 LSB ? 2

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(A) (C)

1 2n 1

(B) 1n 2

SOL 1.18

1 (D) n 1 2 +1 2n 1 Required error in MSB # 1/2 LSB Let ! x % is the tolerance in resistance V V # 1 nV 2 2 1R R R 1+ x a k 100 x a1 + 100 k 1 # 1n x 2 a1 + 100 k x 2n # 1 + x , x (2n 1) # 1 100 # 100 100 x# 1 # 100 2n 1

Hence (A) is correct option.

MCQ 1.19

Consider the following program MVI A, DATA MVI B, 64H MVI C, C8H CMP B JC RJCT CMP C JNC RJCT OUT PORT1 HLT RJCT : SUB A OUT PORT1 HLT If the following sequence of byte is loaded in accumulator,

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DATA (H)

58

64

73

B4

C8

FA

then sequence of output will be (A) 00, 00, 73, B4, 00, FA (C) 58, 00, 00, 00, C8, FA
SOL 1.19

(B) 58, 64, 00, 00, C8, FA (D) 00, 64, 73, B4, 00, FA

This program will display the number between 64H to C8H including 64H. C8H will not be displayed. Hence (D) is correct option. The ideal inverter in figure below has a reference voltage of 2.5 V. The forward voltage of the diode is 0.75 V. The maximum number of diode logic circuit, that may be cascaded ahead of the inverter without producing logic error, is

MCQ 1.20

(A) 3 (C) 5
SOL 1.20

(B) 4 (D) 9

Each diode causes a voltage level loss of 0.75 V. Therefore 0.75n < 2.5 V & n = 3 Hence (A) is correct option. The following serial data are applied to the flip-flop through the AND gates as shown in figure. There is one clock pulse for each bit time. Q is initially 0 and PRE and CLR are high. If leftmost bits are applied first then output Q is

MCQ 1.21

J1 : 1010011, J2 : 0111010, J 3 : 1111000 K1 : 0001110, K2 : 1101100, K 3 : 1010101

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(A) 0000111 (C) 0101000

SOL 1.21

(B) 0011000 (D) 1010101

By applying the serial bits for J and K inputs of the flip-flop CLK J1 J2 J3 K1 K2 K3 J K Q 1 1 0 1 0 1 1 0 0 0 2 0 1 1 0 1 0 0 0 0 3 1 1 1 0 0 1 1 0 1 4 0 1 1 1 1 0 0 0 1 5 0 0 0 1 1 1 0 1 0 6 1 1 0 1 0 0 0 0 0 7 1 0 0 0 0 1 0 0 0

Hence (B) is correct option.

Common Data for Q. 22-23 :

The input-output voltage specification for the standard TTL family are as follows : VOH (min) = 2.4 V, VOL (max) = 0.4 V, VIH (min) = 2.0 V, and VIL (max) = 0.8 V
MCQ 1.22

The maximum-amplitude nose spike, that can be tolerated when a HIGH input is driving an input, is (A) 0.4 V (B) 0.8 V (C) 0.2 V (D) 0.6 V When an output is HIGH, it may be as low as VOH (min) = 2.4 V. The minimum voltage that an input will respond to as a HIGH is VIH (min) = 2.0 V. A negative noise spike that can drive the actual voltage below 2.0 V if its amplitude is greater than VNH = VOH (min) VIH (min) = 2.4 2.0 = 0.4 V Hence (A) is correct option. The maximum-amplitude noise spike, that can be tolerated when a LOW output is driving an input, is (A) 0.4 V (B) 0.8 V (C) 0.2 V (D) 0.6 V When an output is LOW, it may be as high as VOL (max) = 0.4 V. The maximum voltage that an input will respond to as a LOW is VIL (max) = 0.8 V. A positive noise spike can drive the actual voltage above the 0.8 V level if its amplitude is greater

SOL 1.22

MCQ 1.23

SOL 1.23

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than VNL = VIL (max) VOL (max) = 0.8 0.4 = 0.4 V Hence (A) is correct option.

Statement for Linked Question 24-25 :

For the Schmitt trigger oscillator shown below saturation output voltage are + 10 V and 5 V.

MCQ 1.24

The frequency of oscillation is (A) 2183 Hz (C) 1369 Hz

(B) 869 Hz (D) 1443 Hz

SOL 1.24

The switching voltage are V+ = 10 = 5 V, 2 V+ = 5 = 2.5 V 2 The charging and discharging of capacitor is shown in fig. S4.5.23 Hence & & 5 = 10 + ( 2.5 10) e RC i e RC = 2 5
1

i1

t1 = RC ln 2.5

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2.5 = 5 + (5 ( 5)) e RC
t e RC = 1 & t2 = RC ln 4 , 4
2

t2

&

T = t1 + t2 = RC ln 2.5 + RC ln 4 = RC ln 10 R = 50 k , C = 0.01 F T = 50k # 0.01 # ln10 = 1.15 ms f = 1 = 869 Hz T

Hence (B) is correct option.

MCQ 1.25

The duty cycle is (A) 60.2% (C) 48.4%

(B) 39.8% (D) 51.6%

SOL 1.25

Hence (B) is correct option. Duty cycle = t1 # 100 t1 + t 2 RC ln 2.5 = 100 RC ln 2.5 + RC ln 4 # = ln 2.5 # 100 = 39.8% ln 10

Answer Sheet

1. 2. 3. 4. 5.

(C) (D) (B) (B) (B)

6. 7. 8. 9. 10.

(B) (A) (B) (C) (B)

11. 12. 13. 14. 15.

(B) (C) (B) (C) (D)

16. 17. 18. 19. 20.

(B) (B) (A) (D) (A)

21. 22. 23. 24. 25.

(B) (A) (A) (B) (B)

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