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UC2842A/3A/4A/5A UC3842A/3A/4A/5A

HIGH PERFORMANCE CURRENT MODE PWM CONTROLLER

. . . . . . . . .

TRIMMED OSCILLATOR DISCHARGE CURRENT CURRENT MODE OPERATION TO 500kHz AUTOMATIC FEED FORWARD COMPENSATION LATCHING PWM FOR CYCLE-BY-CYCLE CURRENT LIMITING INTERNALLY TRIMMED REFERENCE WITH UNDERVOLTAGE LOCKOUT HIGH CURRENT TOTEM POLE OUTPUT UNDERVOLTAGE LOCKOUT WITH HYSTERESIS LOW START-UP CURRENT (< 0.5mA) DOUBLE PULSE SUPPRESSION

Minidip

SO8

DESCRIPTION The UC384xA family of control ICs provides the necessary features to implement off-line or DC to DC fixed frequency current mode control schemes with a minimal external parts count. Internally implemented circuits include a trimmed oscillator for precise DUTY CYCLE CONTROL under voltage lockout featuring start-up current less than 0.5mA, a precision reference trimmed for accuracy at the error amp input, logic to insure latched operation, a PWM

comparator which also provides current limit control, and a totem pole output stage designed to source or sink high peak current. The output stage, suitable for driving N-Channel MOSFETs, is low in the offstate. Differences between members of this family are the under-voltage lockout thresholds and maximum duty cycle ranges. The UC3842A and UC3844A have UVLO thresholds of 16V (on) and 10V (off), ideally suited off-line applications The corresponding thresholds for the UC3843A and UC3845A are 8.5 V and 7.9V. The UC3842A and UC3843A can operate to duty cycles approaching 100%. A range of the zero to < 50 % is obtained by the UC3844A and UC3845A by the addition of an internal toggle flip flop which blanks the output off every other clock cycle.

BLOCK DIAGRAM (toggle flip flop used only in UC3844A and UC3845A)
Vi 7 34V GROUND 5 UVLO S/R 5V REF INTERNAL BIAS VREF GOOD LOGIC RT/CT 4 OSC ERROR AMP. 2R R 1V T

VREF 5V 50mA

2.50V

OUTPUT

VFB COMP CURRENT SENSE

2 1 3

+ -

S R CURRENT SENSE COMPARATOR PWM LATCH

UC3842A
D95IN331

March 1999

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UC2842A/3A/4A/5A - UC3842A/3A/4A/5A
ABSOLUTE MAXIMUM RATINGS
Symbol Vi Vi IO EO Parameter Supply Voltage (low impedance source) Supply Voltage (Ii < 30mA) Output Current Output Energy (capacitive load) Analog Inputs (pins 2, 3) Error Amplifier Output Sink Current Ptot Ptot Tstg TJ TL Power Dissipation at Tamb 25 C (Minidip) Power Dissipation at Tamb 25 C (SO8) Storage Temperature Range Junction Operating Temperature Lead Temperature (soldering 10s) Value 30 Self Limiting 1 5 0.3 to 5.5 10 1.25 800 65 to 150 40 to 150 300 A J V mA W mW C C C Unit V

* All voltages are with respect to pin 5, all currents are positive into the specified terminal.

PIN CONNECTION (top view) Minidip/SO8

COMP VFB ISENSE RT/CT

1 2 3 4
D95IN332

8 7 6 5

VREF Vi OUTPUT GROUND

PIN FUNCTIONS
No 1 2 3 4 5 6 7 8 Function COMP VFB ISENSE RT/CT GROUND OUTPUT VCC Vref Description This pin is the Error Amplifier output and is made available for loop compensation. This is the inverting input of the Error Amplifier. It is normally connected to the switching power supply output through a resistor divider. A voltage proportional to inductor current is connected to this input. The PWM uses this information to terminate the output switch conduction. The oscillator frequency and maximum Output duty cycle are programmed by connecting resistor RT to Vref and cpacitor CT to ground. Operation to 500kHz is possible. This pin is the combined control circuitry and power ground. This output directly drives the gate of a power MOSFET. Peak currents up to 1A are sourced and sunk by this pin. This pin is the positive supply of the control IC. This is the reference output. It provides charging current for capacitor C T through resistor RT.

ORDERING NUMBERS
SO8 UC2842AD1; UC2843AD1; UC2844AD1; UC2845AD1; UC3842AD1 UC3843AD1 UC3844AD1 UC3845AD1 Minidip UC2842AN; UC2843AN; UC2844AN; UC2845AN; UC3842AN UC3843AN UC3844AN UC3845AN

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THERMAL DATA
Symbol Rth j-amb Description Thermal Resistance Junction-ambient. max. Minidip 100 SO8 150 Unit C/W

ELECTRICAL CHARACTERISTICS ( [note 1] Unless otherwise stated, these specifications apply for -25 < Tamb < 85C for UC284XA; 0 < Tamb < 70C for UC384XA; Vi = 15V (note 5); RT = 10K; CT = 3.3nF)
Symbol Parameter Test Conditions UC284XA UC384XA Unit Min. Typ. Max. Min. Typ. Max. 4.95 5.00 5.05 4.90 5.00 5.10 2 3 0.2 4.9 50 5 -30 Tj = 25C TA = Tlow to Thigh (peak to peak) 47 7.8 25 -30 47 7.8 5.1 4.82 50 5 25 20 25 2 3 0.2 5.18 20 25 V mV mV mV/C V V mV mA KHz % % V mA V A dB MHz dB mA mA V 1.1 V

REFERENCE SECTION VREF Output Voltage VREF VREF Line Regulation Load Regulation

Tj = 25C Io = 1mA 12V Vi 25V 1 Io 20mA (Note 2) Line, Load, Temperature 10Hz f 10KHz Tj = 25C (note 2) Tamb = (note 2) 125C, 1000Hrs

VREF/T Temperature Stability Total Output Variation eN Output Noise Voltage Long Term Stability ISC Output Short Circuit

-100 -180 52 0.2 5 1.6 8.3 57 1 8.8

-100 -180 52 0.2 5 1.6 8.3 57 1 8.8

OSCILLATOR SECTION fOSC Frequency fOSC/V fOSC/T VOSC Idischg Frequency Change with Temp. Oscillator Voltage Swing

Frequency Change with Volt. VCC = 12V to 25V

Discharge Current (VOSC =2V) TJ = 25C VPIN1 = 2.5V VFB = 5V 2V Vo 4V TJ = 25C 12V Vi 25V VPIN2 = 2.7V VPIN1 = 1.1V VPIN2 = 2.3V VPIN1 = 5V VPIN2 = 2.3V; RL = 15K to Ground VPIN2 = 2.7V; RL = 15K to Pin 8 (note 3 & 4) VPIN1 = 5V (note 3) 12 Vi 25V (note 3)

ERROR AMP SECTION Input Voltage V2 Ib BW PSRR Io Io Input Bias Current AVOL Unity Gain Bandwidth Power Supply Rejec. Ratio Output Sink Current Output Source Current VOUT High VOUT Low CURRENT SENSE SECTION GV Gain V3 SVR Ib Maximum Input Signal Supply Voltage Rejection Input Bias Current Delay to Output

2.45 2.50 2.55 2.42 2.50 2.58 -0.1 65 0.7 60 2 -0.5 5 90 1 70 12 -1 6.2 0.8 1.1 -1 65 0.7 60 2 -0.5 5 -0.1 90 1 70 12 -1 6.2 0.8 -2

2.85 0.9

3 1 70 -2 150

3.15 2.85 1.1 -10 300 0.9

3 1 70 -2 150

3.15 1.1 -10 300

V/V V dB A ns

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UC2842A/3A/4A/5A - UC3842A/3A/4A/5A
ELECTRICAL CHARACTERISTICS (continued)
Symbol OUTPUT SECTION VOL VOH VOLS tr tf Output Low Level ISINK = 20mA ISINK = 200mA Output High Level ISOURCE = 20mA ISOURCE = 200mA UVLO Saturation Rise Time Fall Time Start Threshold VCC = 6V; ISINK = 1mA Tj = 25C CL = 1nF (2) Tj = 25C CL = 1nF (2) X842A/4A X843A/5A Min Operating Voltage After Turn-on PWM SECTION Maximum Duty Cycle X842A/3A X844A/5A Minimum Duty Cycle TOTAL STANDBY CURRENT Ist Ii Viz Start-up Current Vi = 6.5V for UCX843A/45A Vi = 14V for UCX842A/44A Operating Supply Current Zener Voltage VPIN2 = VPIN3 = 0V Ii = 25mA 30 0.3 0.3 12 36 0.5 0.5 17 30 0.3 0.3 12 36 0.5 0.5 17 mA mA mA V 94 47 96 48 100 50 0 94 47 96 48 100 50 0 % % % X842A/4A X843A/5A 15 7.8 9 7.0 13 12 0.1 1.6 13.5 13.5 0.7 50 50 16 8.4 10 7.6 1.2 150 150 17 9.0 11 8.2 14.5 7.8 8.5 7.0 0.4 2.2 13 12 0.1 1.6 13.5 13.5 0.7 50 50 16 8.4 10 7.6 1.2 150 150 17.5 9.0 11.5 8.2 0.4 2.2 V V V V V ns ns V V V V Parameter Test Conditions UC284XA UC384XA Unit Min. Typ. Max. Min. Typ. Max.

UNDER-VOLTAGE LOCKOUT SECTION

Notes : 1. Max package power dissipation limits must be respected; low duty cycle pulse techniques are used during test maintain Tj as close to Tamb as possible. 2. These parameters, although guaranteed, are not 100% tested in production. 3. Parameter measured at trip point of latch with VPIN2 = 0. 4. Gain defined as : VPIN1 A= ; 0 VPIN3 0.8 V VPIN3 5. Adjust Vi above the start threshold before setting at 15 V.

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UC2842A/3A/4A/5A - UC3842A/3A/4A/5A
Figure 1: Open Loop Test Circuit.

VREF 4.7K 2N2222 100K ERROR AMP. ADJUST 4.7K 1K ISENSE ADJUST 5K COMP VFB ISENSE RT/CT RT VREF 1 2 8 7 Vi 0.1F OUTPUT GROUND 1W 1K OUTPUT A 0.1F Vi

UC3842A
3 4 6 5

CT
D95IN343

GROUND

High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should be connected close

to pin 5 in a single point ground. The transistor and 5 K potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to pin 3.

Figure 2: Oscillator Frequency vs Timing Resistance


fo (Hz)
D96IN362

Figure 3: Maximum Duty Cycle vs Timing Resistor


fo (Hz)
D96IN363

80

1M
CT =4 70

1nF

pF

60

100K

2.2

nF

4.7

nF

40

10K
20

1K 300 1K 3K 10K 30K

RT()

0 300 1K 3K 10K 30K

RT()

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UC2842A/3A/4A/5A - UC3842A/3A/4A/5A
Figure 4: Oscillator Discharge Current vs. Temperature.
Idischg (mA)
D95IN335

Figure 5: Error Amp Open-Loop Gain and Phase vs. Frequency.


(dB) 80
D95IN337

30 60 90 120 150

Vi=15V VOSC=2V
8.5

Gain
60 40 20

Vi=15V VO=2V to 4V RL=100K TA=25C

8.0

Phase

7.5
0

7.0 -55 -25 0 25 50 75 100 TA(C)

-20 10

100

1K

10K

100K

1M

180 f(Hz)

Figure 6: Current Sense Input Threshold vs. Error Amp Output Voltage.
Vth (V) 1.0
D95IN338

Figure 7: Reference Voltage Change vs. Source Current.


60
D95IN339

Vi=15V
50

Vi=15V

TA=25C
0.8

40

TA=-40C TA=125C

TA=125C
0.6 0.4

30 20

TA=-40C
0.2 0.0

10 0

VO(V)

20

40

60

TA=25C
80

100 Iref(mA)

Figure 8: Reference Short Circuit Current vs. Temperature.


ISC (mA) 100 90 80 70 60 50 -55 -25 0 25 50 75 100 TA(C) Vi=15V RL0.1
D95IN340

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Figure 9: Output Saturation Voltage vs. Load Current.
Vsat (V)
D95IN341

Figure 10: Supply Current vs. Supply Voltage.


Ii (mA) 20
D95IN342

Vi
-1 -2

Source Saturation (Load to Ground) TA=25C TA=-40C

Vi=15V 80s Pulsed Load 120Hz Rate

15
RT=10K CT=3.3nF VFB=0V ISense=0V TA=25C

UCX843/45

10
2 1 0 0

TA=-40C TA=25C
5

Sink Saturation (Load to Vi)


200 400 600

GND
0
IO(mA)

10

UCX842/44

20

30

Vi(V)

Figure 11: Output Waveform.

Figure 12: Output Cross Conduction


Vi =30V CL = 15pF TA = 25C VO 20V/DIV

90%

Vi =15V CL = 1.0nF TA = 25C

ICC 10% 50ns/DIV 100ns/DIV 100mA/DIV

Figure 13: Oscillator and Output Waveforms.

Vi 7 8 5V REG PWM RT CLOCK 4 OSCILLATOR ID CT 5 GND


D95IN344

CT

OUTPUT 6 OUTPUT LARGE RT/SMALL CT

CT

OUTPUT SMALL RT/LARGE CT

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UC2842A/3A/4A/5A - UC3842A/3A/4A/5A
Figure 14 : Error Amp Configuration.
2.5V

1mA + VFB COMP Zf


D95IN345

Zi

2 1

Figure 15 : Under Voltage Lockout.

Vi

ON/OFF COMMAND TO REST OF IC

ICC

UC3842A UC3843A UC3844A UC3845A VON VOFF 16V 10V 8.4V 7.6V

<17mA

<0.5mA VOFF VON

VCC

Fig.15-UC3842A

Figure 16 : Current Sense Circuit .


ERROR AMPL. IS COMP R RS C CURRENT SENSE 5 GND 1

2R R 1V

CURRENT SENSE COMPARATOR

D95IN347

Peak current (is) is determined by the formula 1.0 V IS max RS A small RC filter may be required to suppress switch transients.
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Figure 17 : Slope Compensation Techniques.

VREG RT IS RSLOPE R1 RS RT/CT CT ISENSE

VREG RT

UC3842A

IS RSLOPE

RT/CT CT ISENSE

UC3842A

3 5 GND RS

R1

3 5 GND
D95IN348

Figure 18 : Isolated MOSFET Drive and Current Transformer Sensing.


VCC Vin

5.0Vref

+ -

ISOLATION BOUNDARY VGS Waveforms

+ S R + COMP/LATCH

Q1

+ 0 -

50% DC

+ 0 -

25% DC

Ipk =

V(pin 1) -1.4 3RS

( )
NP

NS

3 C
D95IN349

R RS NS NP

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Figure 19 : Latched Shutdown.
4

OSC

8 R BIAS R + 1mA + 2 EA 2R

1 5

2N 3905 2N 3903

D95IN350

SCR must be selected for a holding current of less than 0.5mA at TA(min). The simple two transistor circuit can be used in place of the SCR as shown. All resistors are 10K.

Figure 20: Error Amplifier Compensation

From VO Ri 2 Rd Cf Rf 1

2.5V

+ 1mA + EA 2R

Error Amp compensation circuit for stabilizing any current-mode topology except for boost and flyback converters operating with continuous inductor current.
+ 1mA RP Ri 2 CP Rd Cf Rf 1 5
D95IN351

From VO

2.5V

+ EA

2R

Error Amp compensation circuit for stabilizing current-mode boost and flyback topologies operating with continuous inductor current.

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Figure 21: External Clock Synchronization.

VREF 8 R BIAS RT 4 CT EXTERNAL SYNC INPUT 0.01F 47 2 1 + EA + R

OSC

2R

The diode clamp is required if the Sync amplitude is large enough to cause the bottom side of CT to go more than 300mV below ground

D95IN352

Figure 22: External Duty Cycle Clamp and Multi Unit Synchronization.

VREF RA 8 4

8 R BIAS R 3 4 + Q + 5K 1 7 + EA 2R

RB 6 5

5K

+ 5K

OSC

2 C

NE555

1 5 TO ADDITIONAL UCX84XAs UCX84XAs


D95IN353

f=

1.44 (RA + 2RB)C

Dmax =

RB RA + 2RB

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Figure 23: Soft-Start Circuit

8 R BIAS R 4 + 1mA 2 1M 1 C 5 + EA 2R

5Vref + -

OSC

S + R 1V Q R

D95IN354

Figure 24: Soft-Start and Error Amplifier Output Duty Cycle Clamp.

VCC

Vin

7 + -

8 R BIAS R 4 + 1mA 2 R2 + EA 2R R 1V

5Vref + -

OSC

Q1

VClamp +

S Q R Comp/Latch 5

1 5

R1

BC109 VCLAMP = R1 R1 + R 2 where 0 <VCLAMP <1V Ipk(max) = VCLAMP RS


D95IN355

RS

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mm MIN. A a1 a2 a3 b b1 C c1 D (1) E e e3 F (1) L M S 3.8 0.4 4.8 5.8 1.27 3.81 4.0 1.27 0.6 8 (max.) 0.15 0.016 0.65 0.35 0.19 0.25 0.1 TYP. MAX. 1.75 0.25 1.65 0.85 0.48 0.25 0.5 0.026 0.014 0.007 0.010 0.004 MIN. inch TYP. MAX. 0.069 0.010 0.065 0.033 0.019 0.010 0.020

DIM.

OUTLINE AND MECHANICAL DATA

45 (typ.) 5.0 6.2 0.189 0.228 0.050 0.150 0.157 0.050 0.024 0.197 0.244

SO8

(1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch).

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DIM. MIN. A a1 B b b1 D E e e3 e4 F I L Z 3.18 7.95 0.51 1.15 0.356 0.204

mm TYP. 3.32 0.020 1.65 0.55 0.304 10.92 9.75 2.54 7.62 7.62 6.6 5.08 3.81 1.52 0.125 0.313 0.045 0.014 0.008 MAX. MIN.

inch TYP. 0.131 MAX.

OUTLINE AND MECHANICAL DATA

0.065 0.022 0.012 0.430 0.384 0.100 0.300 0.300 0.260 0.200 0.150 0.060

Minidip

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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 1999 STMicroelectronics Printed in Italy All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com

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