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2012-1634 (Reexamination No. 95/001,134)

IN THE

UNITED STATES COURT OF APPEALS

FOR THE FEDERAL CIRCUIT

___________ RAMBUS, INC., Appellant, v. Teresa Stanek Rea, ACTING DIRECTOR, UNITED STATES PATENT AND TRADEMARK OFFICE, Appellee. ___________ Appeal from the United States Patent and Trademark Office, Board of Patent Appeals and Interferences. ___________ REPLY BRIEF FOR RAMBUS INC. ___________ J. Michael Jakes James R. Barney Molly R. Silfen FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER, LLP 901 New York Avenue, NW Washington, DC 20001 (202) 408-4000 April 19, 2013
Attorneys for Appellant Rambus Inc.

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TABLE OF CONTENTS I. II. Introduction......................................................................................................1 Argument .........................................................................................................3 A. The PTOs Arguments Incorrectly and Implicitly Construe External Clock Signal to Include Intermittent Pulses that Are Incapable of Governing the Timing of Responses to Transaction Requests and, Therefore, Are Incapable of Serving as a Synchronous Memory Device External Clock Signal .....................................................................................................3 1. The Undisputed Construction of Synchronous Memory Device Mandates that the Claimed External Clock Signal Be Continuously Periodic ...................3 The Specification and Prosecution History Demand the Same Construction ................................................................8 Even the Boards Extrinsic Evidence Leads to the Same Construction ....................................................................10 Under the Correct Construction, Inagaki Does Not Disclose an External Clock Signal that Governs the Timing of the Response to a Transaction Request ...................12

2. 3. 4.

B. C.

The PTOs Arguments Ignore This Courts Prior Construction of Write Request ........................................................14 The PTOs Arguments Fail to Justify the Boards Erroneous Affirmance of the Examiners Obviousness Rejection on Alternative Grounds ............................................................................19 1. The PTO Fails to Rebut that the Board Erroneously Relied on Its Own Conjecture and Presumed Expertise Rather Than Record Evidence ..................................19 The PTOs Arguments Improperly Discount Rambuss Objective Evidence of Nonobviousness ..................27

2. III.

Conclusion .....................................................................................................30 i

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TABLE OF AUTHORITIES

Page(s) FEDERAL CASES Becton, Dickinson & Co. v. Tyco Healthcare Group, 616 F.3d 1249 (Fed. Cir. 2010) .......................................................................... 10 Brand v. Miller, 487 F.3d 862 (Fed. Cir. 2007) ................................................................24, 26, 27 In re Bond, 910 F.2d 831 (Fed. Cir. 1990) ............................................................................ 18 In re Glatt Air Techniques, Inc., 630 F.3d 1026 (Fed. Cir. 2011) .......................................................................... 29 In re Kao, 639 F.3d 1057 (Fed. Cir. 2011) .......................................................................... 24 Intel Corp. v. Broadcom Corp., 172 F.Supp.2d 478 (D. Del. 2001)................................................................ 17-18 Karlin Technology Inc. v. Surgical Dynamics, Inc., 177 F.3d 968 (Fed. Cir. 1999) ............................................................................ 17 KSR International Co. v. Teleflex, Inc., 550 U.S. 398 (2007) ............................................................................................ 21 Miken Composites, L.L.C. v. Wilson Sporting Goods Co., 515 F.3d 1331 (Fed. Cir. 2008) .......................................................................... 16 Phillips v. AWH Corp., 415 F.3d 1303 (Fed. Cir. 2005) (en banc) .......................................................... 11 Powell v. Home Depot U.S.A., Inc., 663 F.3d 1221 (Fed. Cir. 2011) .......................................................................... 23 Rambus Inc. v. Infineon Technologies AG, 318 F.3d 1081 (Fed. Cir. 2003) ...................................................................passim Rambus, Inc. v. LSI Corp., 2012 WL 4466578 (N.D. Cal. Sept. 26, 2012) .............................................11, 12 ii

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Resonate Inc. v. Alteon Websystems, Inc., 338 F.3d 1360 (Fed. Cir. 2003) ............................................................................ 8 Technology Patents LLC v. T-Mobile (UK) Ltd., 700 F.3d 482 (Fed. Cir. 2012) ............................................................................ 10 Trading Technologies International, Inc. v. eSpeed, Inc., 595 F.3d 1340 (Fed. Cir. 2010) ....................................................................10, 13 Transocean Offshore Deepwater Drilling, Inc. v. Maersk Drilling USA, Inc., 699 F.3d 1340 (Fed. Cir. 2012) .......................................................................... 29 Yee v. City of Escondido, California, 503 U.S. 519 (1992) ............................................................................................ 23 OTHER AUTHORITIES WEBSTERS NINTH NEW COLLEGIATE DICTIONARY 1160 (1986) ......................................................................................................... 17

iii

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I.

INTRODUCTION As explained in Rambuss opening brief, the Boards decision rejecting

claims 1, 2, and 7 of U.S. Patent No. 6,260,097 (the 097 patent) as anticipated by Inagaki relied on erroneous constructions of the terms external clock signal and write request. The Board further erred by substituting its own conjecture in place of the record evidence showing that the intermittent data-transfer signal of Inagaki could not be combined with the iAPX clocked system to render claims 1-5, 7, 26, 28-32, 34, and 35 obvious, e.g., because iAPX already uses both edges of its clock signals for other purposes, and the Board improperly discounted the objective evidence of nonobviousness. The PTOs responsive brief fails to address several of Rambuss key arguments. For instance, Rambus explained in its opening brief that all of the claims-at-issue require a synchronous memory device, which the examiner construed to mean a memory device that receives an external clock signal which governs the timing of the response to [a] transaction request. A1067-68

(emphasis added). The Board tacitly adopted this construction, and the PTO has never challenged it, including in this appeal. Thus, it remains undisputed that the claimed external clock signal must be capable of governing the timing of a response to a transaction request. As Rambus explained at length in its brief (see, e.g., Rambus-Br. 9, 13, 17-20, 46-47), in order to govern the timing of a 1

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response to a transaction request, the clock signal must be continuously periodic, not only while a particular memory device is active but also while it is inactive (e.g., when it is waiting to deliver requested data) (id. at 46). Yet the PTOs responsive brief completely ignores this point. Indeed, nowhere in its brief does the PTO even acknowledge that a synchronous memory device requires an external clock that governs the timing of the response to [a] transaction request. Only by ignoring this undisputed construction of synchronous memory device can the PTO argue that the claimed external clock signal can be intermittent, i.e., operating merely during periods of data transfer, which would preclude the ability to govern the timing of responses to transaction requests. The PTO similarly glosses over this Courts earlier construction of the term write request, which specifically requires a series of bits, and instead conflates Inagakis conventional write operation with the claimed write request. Finally, the PTO asserts that it would have been obvious to use both edges of iAPXs clocks for data transfer, notwithstanding that iAPX already uses the other edges of its clocks for non-data functions and has no circuitry capable of performing double-clock-edge data transfer, and notwithstanding that Inagaki uses intermittent pulses to transfer data instead of a system clock. The PTO fails to explain how the iAPX device would have actually operated under the PTOsuggested modifications. And, like the Board, the PTO dismisses Rambuss 2

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objective evidence of nonobviousness, claiming that it lacks a nexus with the claimed invention, even though Rambus pointed to specific evidence touting the combination of a double data rate with a synchronous DRAM. The PTOs rote assertion of lack of nexus does not withstand scrutiny in this case. II. ARGUMENT A. The PTOs Arguments Incorrectly and Implicitly Construe External Clock Signal to Include Intermittent Pulses that Are Incapable of Governing the Timing of Responses to Transaction Requests and, Therefore, Are Incapable of Serving as a Synchronous Memory Device External Clock Signal

As explained below and in Rambuss opening brief, the correct construction of external clock signal does not encompass intermittent pulses like those in Inagaki because such pulses are not capable of governing the timing of responses to transaction requests, a feature that is undisputedly required by the claim language at issue and is consistent with both the intrinsic and extrinsic evidence. Under the proper construction of external clock signal, Inagaki does not anticipate the claims-at-issue as a matter of law. 1. The Undisputed Construction of Synchronous Memory Device Mandates that the Claimed External Clock Signal Be Continuously Periodic

All the claims-at-issue recite a synchronous memory device that includes an external clock signal. A69-70. As Rambus explained in its opening brief, and as the PTO does not dispute, the examiner construed synchronous memory 3

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device to mean a memory device that receives an external clock signal which governs the timing of the response to [a] transaction request. A1067-68

(emphasis added). The Board did not alter this construction, and the PTO does not challenge it on appeal. Thus, the examiners construction of synchronous

memory device is undisputed in this case. It is therefore also undisputed that the external clock signal recited in all of the claims-at-issue must be capable of governing the timing of the response to [a] transaction request. Id. The PTO, however, steadfastly refuses to acknowledge this fact in its brief. Instead, the PTO offers several factually incorrect statements as to what synchronous means in the claims-at-issue. The PTO characterizes the claimed method as only including synchronizing (timing) the writing of information to a memory device in response to an external clock signal. PTO-Br. 6; see also id. at 8, 29-30. This characterization ignores that the claims also recite a synchronous memory device, which further requires timing of the response to [a] transaction request (A1067-68 (emphasis added)), not merely timing of the writing of information to a memory device. The difference between these two concepts is not trivial. The PTO is referring to the concept of synchronizing data delivery, i.e., using a clock to synchronize the transfer of data bits during a read/write operation. Under that narrow view, it does not matter what the clock is doing before or after data delivery because the clock is 4

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dedicated only to the transfer of data, nothing more. The claims-at-issue, however, recite a synchronous memory device, which undisputedly requires an external clock signal that governs the timing of the response to [a] transaction request. A1067-68 (emphasis added). In the context of a synchronous memory device, it does matter what the clock is doing before and after data delivery because the clock is what governs the timing of responses to read/write requests on the bus (among other things). As the 097 patent explains, all conventional asynchronous memory devices transferred data with the transition of the RAS and CAS signals, but those devices were unquestionably asynchronous, not operating on any clock. A58[2:45-48]; see A1767-69[20-27]. As Rambuss expert and even the examiner himself

explained, a synchronous memory device has a very specific meaning in the art, and it means that the device is keyed to a clock that governs the timing of responses to transaction requests. A1067-68; A1767-69[20-27]. The synchronous system described in the 097 patent reflects an entirely different paradigm than prior-art asynchronous systems like Inagaki. Conventional asynchronous systems performed one read/write operation at a time, i.e., a particular memory device was activated, and the read/write operation was performed and fully completed before another read/write transaction on the bus could be commenced. See Rambus-Br. 7, 10-11; A2954-55; A2961[Fig.4]; 5

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A1809[14]. Such asynchronous systems did not need a continuously periodic timing reference on the bus because read/write transactions were performed sequentially, i.e., a particular memory transaction could not start until the previous transaction(s) on the bus had been completed. See A2961[Fig.4]; A1793[118]. In contrast, the synchronous system of the 097 patent preschedules and interleaves transaction requests to different memory devices on the bus, e.g., telling one device to return data in a specific number of clock cycles and using the intervening time to issue other transaction requests and/or pick up data from earlier requests. See Rambus-Br. 12-14. Such a system relies on an external clock signal that runs continuously in the background during system operations, regardless of whether a particular memory device is actively transferring data at a particular time. Id. This is because, as the examiner found and the PTO does not dispute, a synchronous memory device must receive[ ] an external clock signal which governs the timing of the response to [a] transaction request. (emphasis added). As explained in Rambuss opening brief, for a clock to govern the timing of a response to a transaction request, it must cycle predictably and continuously in the background during system operations, regardless of whether any particular memory device happens to be actively transferring data at any given time. The following simplified demonstrative illustrates this point: 6 A1067-68

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clock runs in background for 4 cycles

4-bit data transfer takes 2 clock cycles

Controller: requests read of 4 bits of data to be returned after 4 clock cycles

Memory device: outputs requested data

In the hypothetical illustration above, the memory controller requests a read of four bits of data to be returned after four clock cycles. During the next four clock cycles, even though the designated memory device is not actively transferring data, the external clock signal continues running in the background, allowing the memory device to know how long its been since it received the read request. After four clock cycles have elapsed, the memory device returns the requested data, which takes two clock cycles in this example (i.e., one bit of data transferred on each clock transition). Note that if the external clock was replaced with an intermittent data-transfer signal operating only when the memory device was actively transferring data (as in Inagaki), the above-illustrated operation would be impossible because the memory device would have no way of knowing how many clock cycles had elapsed since it received the read request. This is why the 7

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undisputed construction of synchronous memory devicerequiring timing of responses to transaction requestsrequires an external clock that runs continuously in the background while the system is operating, regardless of whether a particular memory device is actively transferring data. The PTOs brief does not address this argument at all, even though it was prominently presented in Rambuss opening brief (see, e.g., Rambus-Br. 46-47). Instead, the PTO simply argues that Rambuss proposed construction reads limitations into claim 1. PTO-Br. 28. To the contrary, this construction does not read anything into claim 1 that is not already there. Claim 1 explicitly recites a synchronous memory device, which undisputedly requires an external clock that governs the timing of the response to [a] transaction request. (emphasis added). A1067-68

As illustrated above, this ordinary understanding of

synchronous memory device mandates a clock signal that runs continuously in the background during system operations, not merely isolated pulses operating intermittently during periods of data transfer. Resonate Inc. v. Alteon Websystems, Inc., 338 F.3d 1360, 1365 (Fed. Cir. 2003) ([A] disputed claim limitation is construed in the context of other words and limitations in the claim . . . .). 2. The Specification and Prosecution History Demand the Same Construction

Rambuss opening brief showed that the specification discloses only continuously periodic clock signals and that the 097 patent relies on such signals 8

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to be able to perform the essential operations of prescheduling and interleaving read and write operations. Rambus-Br. 16-20, 47. The prosecution history

similarly demands the same construction, since Rambus distinguished its external clock signal from a prior-art references alleged clock signal on the basis that the references signals were not periodic and could not be used to orchestrate timing events. A2700 n.2. And the examiner, applying the 097 specification as a prior-art reference in a separate proceeding, described the 097 clock as always present. A2714; A2739-40; see Rambus-Br. 48-49. The PTOs brief does not respond to or even acknowledge Rambuss arguments regarding the prosecution history; accordingly, those arguments should be taken as undisputed. Regarding the specification, the PTO asserts that the repeated examples of a continuous, periodic clock throughout the specification are merely preferred embodiments. PTO-Br. 29. But the PTO ignores the purpose of synchronous memory devices, which can only respond synchronously to transaction requests if the external clock runs continuously in the background. 1 Such synchronous operation is not possible with Inagakis intermittent data-

The Board and the PTO assert that Rambuss proposed construction somehow requires a computer clock that runs forever or that cannot be turned off. A9; PTO-Br. 12. But Rambus is not proposing a clock that runs forever, e.g., even when the computer is turned off. Rather, the clock must simply run while the system is operating, such that the clock can be used by the claimed memory device to govern the timing of responses to transaction requests. 9

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transfer signal. To be sure, there are no examples in the specification suggesting that the external clock can be intermittent, as this would be flatly contrary to the undisputed purpose of a synchronous memory device. Thus, the intrinsic evidence and the very purpose of the claimed invention require Rambuss construction. Tech. Patents LLC v. T-Mobile (UK) Ltd., 700 F.3d 482, 493-94 (Fed. Cir. 2012) (construing a claim term to be consistent with [o]ne of the primary purposes of the invention); Trading Techs. Intl, Inc. v. eSpeed, Inc., 595 F.3d 1340, 1354 (Fed. Cir. 2010) (holding that broader construction would defy the inventions goal and would present the same problem as the prior inventions). 3. Even the Boards Extrinsic Evidence Leads to the Same Construction

As Rambus explained in its opening brief, even the dictionary definition the Board relied upon for the definition of clock states that a clock usually contain[s] a means for producing a regularly recurring action, consistent with Rambuss proposed construction of external clock signal. A36; Rambus-Br. 49; see Becton, Dickinson & Co. v. Tyco Healthcare Grp., 616 F.3d 1249, 1260-61 & n.9 (Fed. Cir. 2010) (relying on dictionarys definition that an articulated structure usually has a hinge or sliding joint). Rather than addressing Rambuss argument, the PTO simply repeats the portion of the dictionary definition that the

10

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Board relied upon, omitting the definitions reference to a regularly recurring action. PTO-Br. 12, 20, 31. The PTO also repeats the Boards only other extrinsic evidencethe use of the word clock in the translated Japanese Inagaki reference. PTO-Br. 29-32. But, as Rambus showed, Inagaki uses the word clock to describe many conventional transition-based signals such as the chip-enable signal and the CAS signal, which are clearly not periodic and do not even meet the Boards incorrect construction of external clock signal. Rambus-Br. 50; A2958 (referring to CAS clock). Such a translation from a foreign extrinsic reference cannot override the clear intrinsic evidence, including the claim language itself, the specifications consistent usage, and the undisputed prosecution history, all of which require an external clock signal to be continuous and periodic. See Phillips v. AWH Corp., 415 F.3d 1303, 1317 (Fed. Cir. 2005) (en banc). Finally, the PTO contends that the Northern District of California recently adopted the Boards construction that the claimed clock signal is a periodic signal [that] may be intermittent, e.g., present during read or write operations, without being always present. PTO-Br. 32 (alteration in original) (quoting

Rambus, Inc. v. LSI Corp., 2012 WL 4466578, at *7 (N.D. Cal. Sept. 26, 2012) (LSI)). But the court there simply determined that [n]either side ha[d] identified any persuasive evidence to suggest how a person skilled in the art would 11

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understand the term periodic, or, more generally, clock signal, and in the absence of evidence, the court defaulted to what it believed to be the Boards construction. LSI, 2012 WL 4466578, at *7. As explained in this appeal, however, the Board erred in implicitly construing external clock signal to include intermittent pulsed signals, and, therefore, to the extent the district court in LSI adopted this implicit construction (which is not clear), the district court likewise erred. A district courts adoption of an erroneous construction does not make that construction any less erroneous. 4. Under the Correct Construction, Inagaki Does Not Disclose an External Clock Signal that Governs the Timing of the Response to a Transaction Request

Under the proper construction, Inagakis irregular data-transfer pulses do not meet the external clock signal limitation because they are incapable of govern[ing] the timing of the response to [a] transaction request, as required by the proper construction. A1067-68. The PTO erroneously claims that Rambus recognizes that Inagaki uses an external clock. PTO-Br. 28. In fact, Rambus has consistently contended that Inagaki does not use an external clock signal, as that term is properly construed. See, e.g., Rambus-Br. 49-51. Although Inagaki calls its irregular pulsed signals clocks, they are not clocks within the meaning of the 097 patent for all of the reasons explained above and in Rambuss opening brief. Id. 12

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The PTO asserts that, regardless of the correct claim construction, Inagakis signals are sufficiently periodic to satisfy the external clock signal limitation. PTO-Br. 29; see also id. at 12, 29-32. But as even the PTO admits, Inagakis pulsed signals occur only intermittently (e.g., during read and write operations). PTO-Br. 31 (emphasis added). As Rambus has explained, such a signal cannot meet the claim requirement of an external clock signal that governs the timing of responses to transaction requests. Supra II.A.1-3; Rambus-Br. 46-51. Thus, the PTOs argument is simply another way of arguing for a different claim construction, which cannot defeat the clear intrinsic evidence requiring that the external clock signal be continuously periodic, such that it runs in the background, even when a particular memory device is not actively transferring data. Indeed, the PTO does not even address this Courts decision in Trading Technologies, 595 F.3d at 1354 (discussed at Rambus-Br. 50-51), in which this Court held that, where a claim requires continuity over time, a device cannot meet the limitation by occasionally complying. Cf. PTO-Br. 30-31. Thus, as Rambus explained in its opening brief, Inagakis disclosure of two isolated pulses included for the sole purpose of data transfer does not constitute an external clock signal under any fair reading of the 097 patent. Given the Boards incorrect construction of external clock signal, which is flatly contrary to the undisputed construction of synchronous memory device 13

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and the rest of the intrinsic evidence, the Boards decision finding anticipation by Inagaki is unsupported by substantial evidence and should be reversed. B. The PTOs Arguments Ignore This Courts Prior Construction of Write Request

This Court previously construed write request (in a related patent sharing a common specification with the 097 patent) as requiring a series of bits. Rambus Inc. v. Infineon Techs. AG, 318 F.3d 1081, 1093 (Fed. Cir. 2003) (Infineon). As Rambus explained in its opening brief, that construction, requiring a write request to convey more than one bit of information, is stare decisis and is further supported by the intrinsic evidence. Rambus-Br. 51-56. Yet, despite this Courts prior claim construction, the PTO insists that claim 1 does not limit the term write request to a series of bits. PTO-Br. 33 (emphasis added); see also id. at 20. The PTO is mistaken. As Rambuss opening brief explains, a write request, within the meaning of the 097 patent, must include more than one bit for a synchronous memory device to operate as intended. See Rambus-Br. 11-14. Specifically, as this Court has held, the claimed write request must convey at least (1) whether the request is a read or write, and (2) the mode (e.g., page mode or normal mode). Infineon, 318 F.3d at 1093; A62[10:20-23]; Rambus-Br. 23. Since each of these pieces of information requires at least one bit to convey, the write request itself must include more than one bit. 14

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In addition to this Courts prior construction of write request being stare decisis and being compelled by the intrinsic evidence, the PTOs assertions are also independently erroneous. Like the Board, the PTO argues that Mr. Murphy, Rambuss expert, somehow conceded that a write request need not be made up of bits because he said it is made up of bits or the state of a signal at a particular time. PTO-Br. 35; see id. at 21. The PTO argues that a write request can therefore be something other than bits, but it does not even address Rambuss point that Mr. Murphys statement, read in context, uses the word or to show an equivalent, such that a bit is the same thing as the state of a signal at a particular time. Rambus-Br. 55, 31-32; see A1810[20]. In other words, Mr. Murphy was simply explaining that a bit in a digital system can be conveyed by a signal having a voltage that is either high (e.g., to represent a 1) or low (e.g., to represent a 0) at a particular point in time. This does not change the fact that the claimed write request still must contain multiple bits, as this Court has held. Infineon, 318 F.3d at 1093. Thus, the PTOs reliance on Mr. Murphys declaration is misplaced and does not in any way justify the Boards refusal to follow this Courts prior construction of write request as requiring a series of bits. The PTO also asserts that, because a request packet contains multiple bits and is not claimed, a write request somehow cannot be construed as requiring more than one bit. PTO-Br. 33-34, 20. But as Rambus explained in its opening 15

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brief, this Court has already considered this issue and concluded that a write request does, in fact, require a series of bits. Rambus-Br. 32, 53. Specifically, this Court determined that a read [or write] request is distinct from a request packet. Infineon, 318 F.3d at 1093. This Court further concluded that the read (or write) request must nevertheless include a series of bits because it must contain at least two pieces of information: (1) whether it is a read or write, and (2) what type of read[/write] (e.g., page mode, normal mode, etc.) to perform. Id. Thus, as this Court has previously held, and as stare decisis compels, despite the distinction between a request packet and a write request, a write request must include a series of bits. Id.; see also Miken Composites, L.L.C. v. Wilson Sporting Goods Co., 515 F.3d 1331, 1338 n.* (Fed. Cir. 2008) (when a previous claim construction is derived from evidence that is before the later court, the Supreme Courts Markman decision requires giving the same construction). The PTO also asserts that a write request can consist of a single bit because the operation code that may be contained within the write request can consist of a single bit. PTO-Br. 34, 20-21. But again, Rambus already explained that the write request may contain information beyond the operation code, and nothing in the patent suggests that a write request can consist solely of a single-bit operation code. Rambus-Br. 54. The PTOs only response is that the claims do not mandate[ ] that other information beyond an operation code must be included 16

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as part of the write request. PTO-Br. 34-35 n.24. This is not true. As this Court has already determined, the construction of write request itself mandates that the write request include (1) whether it is a read or write, and (2) what type of read[/write] (e.g., page mode, normal mode, etc.) to perform. Infineon, 318 F.3d at 1093. Those two pieces of information necessarily require at least two bits. Thus, the PTOs assertion that a write request could be a single bit because it may contain a single-bit operation code is simply illogical in the context of the 097 specification and this Courts ruling in Infineon. The PTO next contends that the series of bits required by this Courts construction could be a single bit. PTO-Br. 36; A13-14 & n.7. But both the English language and the context of the Infineon decision require the series to include more than one bit. Specifically, the word series is ordinarily understood to encompass more than one object or thing. See, e.g., Karlin Tech. Inc. v.

Surgical Dynamics, Inc., 177 F.3d 968, 971 (Fed. Cir. 1999) (The relevant definition of series is a number of things or events of the same class coming one after the other in spatial or temporal succession. (citing WEBSTERS NINTH NEW COLLEGIATE DICTIONARY 1160 (1986))); accord Intel Corp. v. Broadcom Corp., 172 F.Supp.2d 478, 515 (D. Del. 2001) (construing a claim term as requiring a series (plural) of 1s and 0s). And this Court in Infineon, in construing write request to require a series of bits, clearly considered it to require more than one 17

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bit because it must convey at least two pieces of information, as explained above. Thus, contrary to the PTOs suggestion, this Court did in fact address whether a series of bits could be a single bit (PTO-Br. 36, 21) and determined that it could not. Finally, as a fallback, the PTO suggests (for the first time on appeal) that Inagakis external signal could somehow meet the write request limitation if it were modified to include more than one bit. PTO-Br. 37 (It is hard to understand why [Inagakis] external signal, in a digital environment, could not include one or more bits. (emphasis added)). This argument is a non-starter, however, because Inagaki was only asserted as an anticipation reference, so modifications are not permitted. See In re Bond, 910 F.2d 831, 832 (Fed. Cir. 1990). Moreover, nothing in Inagaki shows that the external signal constitutes one bit, let alone a series of bits, indicating a write. And the PTOs belated suggestion that the external signal could be more than one bit misunderstands the context of the digital environment in Inagaki. A digital signal must, by definition, convey only one piece of information at a time (i.e., either a 1 or a 0). For an asynchronous system like Inagaki to convey more than one bit at once, more than one line would have to be used. But in Inagaki, each line has already been dedicated to a signal, and the reference simply does not describe or suggest configuring the lines otherwise.

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Given the Boards incorrect construction of write request, which is contrary to the intrinsic evidence and this Courts prior decision in Infineon, the Boards decision finding anticipation by Inagaki is unsupported by substantial evidence and should be reversed. C. The PTOs Arguments Fail to Justify the Boards Erroneous Affirmance of the Examiners Obviousness Rejection on Alternative Grounds 1. The PTO Fails to Rebut that the Board Erroneously Relied on Its Own Conjecture and Presumed Expertise Rather Than Record Evidence

As Rambus explained, and as the PTO does not dispute, the examiners obviousness rejection assumed, incorrectly, that a person skilled in the art could simply combine iAPX and Inagaki by using unused edges of iAPXs CLKB clock to accomplish Inagakis dual-edge data-transfer technique, when, in fact, all of iAPXs other clock edges are already used for other (non-data) purposes and could not be modified to be dedicated to data transfer. Rambus-Br. 33-36, 56; cf. PTOBr. 22 (mischaracterizing Rambuss argument as stating that the Board, not the examiner, ignored the use of all edges). Thus, there appears to be no dispute that the entire premise of the examiners obviousness rejection (i.e., that iAPXs CLKB had unused clock edges) was factually incorrect. The Board, however, rather than reversing the examiners rejection based on this admitted factual error, proceeded to hypothesize various alternative ways to affirm the rejection, despite the

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complete lack of record evidence to support those grounds. Rambus-Br. 36-40, 56. The Boards hypotheses are both contradicted by the actual evidence and are outside the Boards purview as reviewer of the examiners decision. The Boards first two hypotheses were that iAPX could drop some of its functions that are performed on the other edges of its clocks in favor of transmitting data on those edges, or that iAPX could use other [clock] edges for data transmission. Rambus-Br. 36-38. Such vague hypothetical conjecture is not evidence. Moreover, as Rambus explained in its opening brief, there are no

unused edges in the iAPX system that could accommodate double-data-rate activity, and dropping existing functions would mean creating a write-only device because those functions include the ability to switch between reading and writing. Id.; A24; see also PTO-Br. 22 (conceding that iAPX uses only one clock edge for data transfer and uses the remaining clock edges for other functions). Regarding the Boards hypothetical write only device, the Board itself conceded that both input and output of data are necessary in a RAM memory device. See A10 ([A] RAM memory device necessarily must distinguish between a read and a write; otherwise, it could not function as the well-known RAM and perform input and output (I/O) of data. (emphasis added)). Indeed, it is hard to imagine the benefit of a device that could store data but never retrieve it. Certainly, the PTO has not identified any such benefit in its responsive brief. 20

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Quite the opposite, the PTO now attempts to reinterpret the Boards hypothetically modified iAPX system for handling mere one-way data transfers (A25) as not necessarily precluding both writing and reading because it allegedly permits reading of data in other ways (PTO-Br. 47). But there are at least two problems with this new interpretation: first, that is not at all what the Board said; second, there is no record evidence of any such other way[] of reading data in iAPX. See id. (citing no evidence). The PTO repeatedly cites KSR International Co. v. Teleflex Inc., 550 U.S. 398 (2007), in support of the alleged obviousness of the combination of iAPXs continuous, single-data-rate clocking and Inagakis intermittent, double-data-rate operation. PTO-Br. 23, 38, 41-45, 47. But KSR requires that, to show

obviousness, the combination would have to be according to known methods, KSR, 550 U.S. at 416, or the techniques actual application would have to be within the skill of a person of ordinary skill, id. at 417. See also id. at 421 (a person of ordinary skill would pursue the known options within his or her technical grasp (emphasis added)). Here, no one has explained how any of the Boards hypotheses for changing iAPX would have been carried out, nor is there any evidence (aside from the Boards say-so) that these modifications would have been within the technical grasp of a person of ordinary skill in the art in 1990. In contrast, Rambus has presented unrebutted evidence that such a combination 21

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would not work properly if done in the ways the Board hypothesized. See, e.g., A1795[127]; A1811-12[22-25]; A1711. Furthermore, iAPX teaches away from using both edges of either clock for data transmission because it holds data for a full clock cycle during data output, preventing a data transfer on both edges and therefore rendering the dualedge/double-data-rate feature infeasible. Rambus-Br. 39, 57-58. Indeed, the

Board and the PTO are factually incorrect in saying that iAPX could have been modified because it already ha[d] the circuitry available to send/receive data on both edges. A23 (citing A2772); PTO-Br. 17, 44. In fact, the circuitry to

send/receive data on both edges did not exist in iAPX precisely because it was designed to hold the data for a full clock cycle. A3290 (showing data being maintained over course of full clock cycle); A3331 (same). Moreover, the mere fact that iAPX uses both clock edges of CLKB for other purposes does not in any way mean it has the circuitry available to perform the double-data-rate technique recited in the claims-at-issue. That technique requires sampling data in response to a write request on two successive clock edges, thereby doubling the rate of data transfer. A1769[25]. In contrast, iAPX discloses referencing a data signal on odd clock edges (i.e., once per clock cycle) and another (non-data) signal on even clock edges (A3285; A1811-12[24]), which is not the same thing (and does not

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employ the same circuitry) as sampling a single data line twice per clock cycle to achieve a double data rate. The PTO contends that Rambus somehow waived the argument that iAPX teaches away from being combined with a dual-edge/double-data-rate feature. PTO-Br. 45. But Rambus clearly raisedin its opening brief to the Boardthe argument that iAPX is rendered inoperable by modifying its clocking scheme. A1754. Specifically, Rambus argued that, in iAPX, data is only transferred by devices in the system once per clock cycle. Id. Thus, Rambuss argument, even if more fully fleshed out in its reply brief before the Board in response to NVIDIAs brief, cannot be considered waived. See Yee v. City of Escondido, Cal., 503 U.S. 519, 534-35 (1992) (holding that waiver does not apply, even to separate arguments in support of same claim, because litigant generally possesses the ability to frame the question to be decided in any way he chooses, without being limited to the manner in which the question was [previously] framed); accord Powell v. Home Depot U.S.A., Inc., 663 F.3d 1221, 1230-31 (Fed. Cir. 2011). Regarding all of the Boards alternative grounds for affirming the examiner, the Boards own conjecture does not supply the requisite substantial evidence to support . . . rejections. In re Kao, 639 F.3d 1057, 1067 (Fed. Cir. 2011). To find obviousness, the Board may not substitute[ ] its own opinion for evidence of the knowledge of one of ordinary skill in the art. Brand v. Miller, 487 F.3d 862, 870 23

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(Fed. Cir. 2007). And contrary to the PTOs contention (PTO-Br. 42 n.28), the Board must base any substantive validity determinations on record evidence, not its own presumed expertise, Brand, 487 F.3d at 870-71. The following table shows the Boards various hypotheses (which it formulated on appeal after tacitly conceding that the examiners obviousness rejection was premised on an erroneous factual finding), along with the alleged evidence (or lack thereof) cited by the Board. Boards Hypothesis [C]ontrary to Rambuss assertions, skilled artisans would have understood how to implement the known feature of using both clock edges on data to maximize speed whether shift registers were employed or not. A23. Supporting Evidence Cited by the Board For this, the Board relies on NVIDIAs respondent brief at 12, which contains attorney argument stating that the fact that iAPX already uses both rising and falling edges of the clock for other purposes means that iAPX already has the circuitry available to send/receive data on both edges without a shift register. A23 (citing A2772). NVIDIAs brief cites no record evidence for this proposition. The Board again relies on NVIDIAs respondent brief, which contains only attorney argument, without citing any record evidence to support this point. See A2772 n.23.

Alternatively, skilled artisans would have recognized that buffer directional control could have been provided with other CLKA or CLKB edges (see NVIDIA Resp. Br. 12 n.25 [sic, n.23]), or even with other bused signals. A24.

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Boards Hypothesis

Supporting Evidence Cited by the Board

As such, given the claim breadth, The Board cites no evidence to support skilled artisans easily could have this proposition. A25. modified the iAPX system in view of Inagakis clocking scheme by dropping, instead of replacing, many functions. Such a modification would create a cleaner memory device for handling mere one-way data transfers embraced by broad claim 1. A25. Skilled artisans would have recognized that the iAPX system could have been modified to include the external slower Inagaki clock as a trigger for the faster CLKA and/or CLKBthereby retaining all existing APX functions. A25. [W]hile Rambus relies on an example to show that data is held over successive CLKB edges, this does not mean that the iAPX MACD data cannot be modified to correspond to rising and falling clock edges. Rambuss reliance on specific examples does not show that the iAPX system requires the data to be held for the duration argued, or that the data could not be modified to be held for less than the time defined by the CLKA pulse, or that the CLKA pulses could not be extended. A27-28. The Board cites no evidence to support this proposition. A25. Although the Board cites generally to Inagaki, it fails to cite any evidence as to what [s]killed artisans would have recognized in 1990 in light of iAPX and Inagaki. See A2526. The Board cites no evidence showing that these proposed modifications would have been obvious to a person of ordinary skill in the art in 1990. Instead, the Board simply argues that Rambus has failed to show that these modifications were not possible (which, of course, is not Rambuss burden).

As shown above, the facts of this case are very similar to those in Brand, in which this Court held that the Board had exceeded its authority under the Administrative Procedures Act. 487 F.3d at 870-71. 25 Brand involved an

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interference proceeding in which one issue before the Board was whether senior party Brand had derived the claimed invention from junior party Miller. This issue turned, in part, on certain drawings that Miller had shown to Brand, depicting a certain type of screw called a bugle-headed screw dog. Id. at 866.

Notwithstanding an unchallenged declaration submitted on Brands behalf, the Board concluded that Miller had proven derivation based on the following analysis: The Board reasoned that one skilled in the art . . . would have recognized [the] suitability [of Millers bugleheaded screw dogs MX2002] for securely supporting a tapered flitch in the position depicted in [MX2001]. The Board did not cite any testimony or record evidence to support its conclusion. The Board further held that [t]he ability of the bugle-headed screw dogs to tightly clamp the flitch would have been readily apparent. The Board also held, in the alternative, that the information in MX2001, taken alone, was sufficient to teach one of ordinary skill in the art how to practice the method of the count. Again without citing record evidence, the Board concluded that the drawing in MX2001 disclosed the invention. Id. at 867 (alterations in original) (citations omitted). On appeal, this Court held that the Board had improperly substituted its own opinion for evidence of the knowledge of one of ordinary skill in the art. Id. at 870. As the Court explained: The Boards conclusion that one skilled in the art . . . would have recognized [the] suitability [of Millers 26

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bugle-headed screw dogs MX2002] for securely supporting a tapered flitch in the position depicted in [MX2001] was not supported by any citation to the record. Similarly, the Board did not anchor in the record its conclusion that an artisan would have deduced from the drawing of a flitch in MX2001 standing alone a method of securely fastening a tapered flitch to a staylog, given that the drawing did not depict any dogs or holes in the flitch. Id. (alterations in original) (citation omitted). Here, as in Brand, the Boards various hypotheses as to what a person of ordinary skill in the art would have considered obvious in 1990 are not supported by record evidence. Instead, as shown in the table above, the Board relied solely on its own presumed expertise and, at times, on attorney argument provided by NVIDIA. Whether the Board has sufficient expertise in the field of DRAMs to justify these opinions is irrelevant, because such expertise, even if it exists, is not enough. As this Court made clear in Brand, the Board must base any substantive validity determinations on record evidence, not its own expertise. Id. at 870-71. Here, the overwhelming weight of the record evidence supports nonobviousness, not obviousness. 2. The PTOs Arguments Improperly Discount Rambuss Objective Evidence of Nonobviousness

Even if the examiner or the Board had established a prima facie case of obviousness (which they did not), Rambus rebutted that case with objective evidence of nonobviousness, including long-felt need, skepticism followed by 27

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praise, and commercial success in the form of licensing. Rambus-Br. 40-44, 6064. The PTO, like the Board, asserts in rote fashion that Rambus failed to establish a nexus between its objective evidence and the specific claimed features. PTO-Br. 48-55. But this is not true. As Rambus explained in its opening brief, the objective evidence shows a strong nexus to the specific combination of a dual-edge/double-data-rate feature with a synchronous memory device. Rambus-Br. 41. For instance, the addition of double data rate to synchronous memory devices was announced in the news and specifically touted by Micron (a Rambus competitor) as a revolutionary and pioneering technology . . . vastly improving performance over the synchronous memory device alone. A1711 (When we introduced DDR SDRAM [i.e., doubledata-rate synchronous DRAM], it was a revolutionary and pioneering technologyenabling applications to transfer data on both the rising and falling edges of a clock signaland vastly improving performance over SDRAM. (emphasis added)); see also A2633; A2105[145]; A2623; A2639 (articles all specifically touting dual-edge/double-data-rate feature). The PTO does not even address the Micron statement in alleging a lack of nexus. And while the PTO is correct that some of the articles also touted other features of the 097 patent (see PTO-Br. 49-50), the fact that they specifically called out the double-data-rate feature as a novel improvement to synchronous 28

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memory devices is sufficient to show a nexus, see Transocean Offshore Deepwater Drilling, Inc. v. Maersk Drilling USA, Inc., 699 F.3d 1340, 1350-51 (Fed. Cir. 2012) (finding sufficient nexus when evidence showed link between claimed feature and objective evidence, even where claimed improvements could not be separated from unclaimed improvements). The PTO also complains that Rambuss objective evidence was not commensurate in scope with the claims breadth. But the PTO does not even address this Courts holding in In re Glatt Air Techniques, Inc., 630 F.3d 1026, 1030 (Fed. Cir. 2011), in which this Court rejected such an argument. See

Rambus-Br. 62. And the PTOs assertion that Rambus somehow had to overcome the combined device resulting from iAPX and Inagaki is simply circular. PTOBr. 52; see also id. at 51 (Rambuss evidence . . . must exclude the alleged slower performing devices in prior art (e.g., the combination of iAPX and Inagaki).). The entire point of Rambuss objective evidence is to show that one of ordinary skill would not have combined iAPX and Inagaki in 1990. There is no logic to the PTOs alleged requirement that Rambus must show that its invention is better than that very combination.

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III.

CONCLUSION For the foregoing reasons and those explained in Rambuss opening brief,

this Court should reverse the Boards decision finding the 097 patent anticipated by Inagaki and rendered obvious by iAPX in view of Inagaki. 2

If the Court finds anticipation but not obviousness, claims 3-5, 26, 28-32, 34, and 35 should be confirmed because the anticipation finding applied only to claims 1, 2, and 7. Cf. PTO-Br. 26 n.22, 37 (asserting that all appealed claims stand or fall with claim 1). An anticipation rejection that was never applied cannot support invalidity. 30

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Dated: April 19, 2013

Respectfully submitted,

/s/ James R. Barney J. Michael Jakes James R. Barney Molly R. Silfen FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER, LLP 901 New York Avenue, NW Washington, DC 20001 (202) 408-4000 Attorneys for Appellant Rambus Inc.

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CERTIFICATE OF SERVICE I hereby certify I electronically filed the foregoing REPLY BRIEF FOR RAMBUS INC. using the Courts CM/ECF filing system. Counsel registered with the CM/ECF system were served by operation of the Courts CM/ECF SYSTEM per Fed. R. App. P. 25 and Fed. Cir. R. 25(c) on this 19th day of April 2013. Nathan K. Kelley William LaMarca Coke Morgan Stewart Office of the Solicitor United States Patent and Trademark Office Mail Stop 8, P.O. Box 1450 Alexandria, VA 22213-1450 Counsel for USPTO

/s/ Kay Wylie Kay Wylie

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CERTIFICATE OF COMPLIANCE I certify that the foregoing REPLY BRIEF FOR RAMBUS INC. contains 6,994 words as measured by the word-processing software used to prepare this brief.

Dated: April 19, 2013

Respectfully submitted,

/s/ James R. Barney J. Michael Jakes James R. Barney Molly R. Silfen FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER, LLP 901 New York Avenue, NW Washington, DC 20001 (202) 408-4000