Sharp UP-700 Cash Register SM

SERVICE MANUAL
MODEL
UP-700
SRV Key : LKGIM7113RCZZ PRINTER : PR-58HM (For "U & A" version)
CONTENTS
CHAPTER 1. SPECIFICATIONS ................................................................1 - 1 CHAPTER 2. OPTIONS ..............................................................................2 - 1 CHAPTER 3. SERVICE PRECAUTION ......................................................3 - 1 CHAPTER 4. SRV. RESET AND MASTER RESET ....................................... 4 - 1 CHAPTER 5. DIAGNOSTICS SPECIFICATIONS.......................................5 - 1 CHAPTER 6. CIRCUIT DESCRIPTION ......................................................6 - 1 CHAPTER 7. TCP/IP I/F PWB DESCRIPTION...........................................7 - 1 CHAPTER 8. CIRCUIT DIAGRAM ..............................................................8 - 1 CHAPTER 9. PWB LAYOUT.......................................................................9 - 1 PARTS GUIDE
Parts marked with " " are important for maintaining the safety of the set. Be sure to replace these parts with specified ones for maintaining the safety and performance of the set.
SHARP CORPORATION
This document has been published to be used for after sales service only. The contents are subject to change without notice.
CHAPTER 1. SPECIFICATION
1. APPEARANCE
External view
2) KEY TOP NAME

Standard key top KEY TOP DESCRIPTION Numeric keys Decimal Point key CL @/FOR RECEIPT JOURNAL
Mode switch
Front view
Journal cover Receipt paper
0-9,00,000
Customer display (Pop-up type) Operator display Contrast control Power switch
Clear key Multiplication key Receipt paper feed key Journal paper feed key Page up key Page down key Cancel key Cursor keys
PAGE UP PAGE DOWN CANCEL
Drawer Drawer lock
Keyboard
ENTER
Rear view
Enter key Refund Key Server code entry key Receipt print Key Tax 1 shift key Void Key PLU/SUB dept./UPC code entry key Direct PLU 1 to 100 keys Price shift menu key Automatic sequencing 1 and 2 keys Miscellaneous function key Currency conversion menu key Check Menu Key Charge Menu Key Subtotal Key Cash / amount tendered key Tentative finalization key PLU level shift menu key Service key Guest Look-up key
RFND SERV# RCPT TAX SHIFT VOID
Power switch Rear cover
PLU/SUB (D-PLU) 1 to 100 P.SHIFT# AUTO1, 2
2. RATING
External dimensions : With a drawer 445 (W) x 485 (D) x 312 (H) mm
MISC FUNC CONV# CHK# CH# SBTL 10%, 60Hz CA/AT FINAL LEVEL# SRVC GLU 120V AC
Weight : With a drawer 16.4kg Power source Power consumption Working temperatures
Stand-by : 16 W Operating : 57 W (max.) 0 to 40 C
3. KEYBOARD
1) STANDARD KEYBOARD LAYOUT
RECEIPT JOURNAL
87 73 60 50 40 30 20 11 3
88 74 61 51 41 31 21 12 4
89 75 62 52 42 32 22 13 5
90 76 63 53 43 33 23 14 6
91 77 64 54 44 34 24 15 7
92 78 65 55 45 35 25 16 8
93 79 66 56 46 36 26 17
94 80 67 57 47 37
95 81 68 RCPT SERV # PAGE UP
96 82 69 VOID @ FOR
97 83 70
98 84 MISC FUNC
99 85 AUTO 1
100 86 AUTO 2
71 58 48 38 28 18 9 1
72 59 49 39 29 19 10 2
*1
RFND CANCEL LEVEL CONV # #
7 4 1 00
8 5 2
CL 9
P-SHIFT
# PLU/ SUB CHK # CH # SBTL
TAX SHIFT GLU SRVC FINAL CA/AT
PAGE 27 DOWN ENTER
6 4
0 000
*1 Note: August Production: The [Auto 2] Key will be the [NC] Key.
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Optional key top KEY TOP (D-PLU) 101 to 123 (Dept) 1 to 99 %1 to 5 (-)1 to 5 CH1 to 9 CASH# FUNC. MENU RP SEND GRT EX CA2 to 5 CONV1 to 4 RA1 to 2 PO1 to 2 AUTO3 to 25 CHK1 to 5 P1 to 6 LEVEL1 to 5 FS SHIFT FS TEND GD1 to 3 SHIFT CASH TIP CHARGE TIP TIP PAID EAT IN1 to 3 TAX2 to 4 SHIFT NS SCALE OPEN TARE BAL DEPOSIT DEPOSIT RF DEPT# TAX BACL SPACE TRANS OUT TRANS IN RCP SW WASTE BS BT PRINT BILL PAST VOID SBTL VOID DESCRIPTION Direct PLU 101 to 123 Keys Department 1 to 99 Keys Percent 1 to 5 keys Discount 1 to 5 keys Charge 1 to 9 keys Cash menu key Function menu key Remote printer send key Gratuity exempt key Cash 2 to 5 keys Conversion 1 to 4 keys Received-on-Account 1 and 2 keys Paid out key 1 and 2 keys Automatic sequencing 3 and 25 keys Check 1 to 5 keys Price level shift 1 to 6 keys Menu level shift 1 to 5 keys Food stamp shift key Food stamp tender key Group discount shift 1 to 3 keys Cash tip key Charge tip key Tip paid key Eat in 1 to 3 keys Tax 2 to 4 shift keys No sale key Scale entry key Tare entry key Balance key Deposit key Deposit refund key Department number key Manual tax key Back space key Transfer out key Transfer in key Receipt ON/OFF key Waste mode key Bill separation key Bill totalize / bill transfer key (CHECK-ADD) Validation print key Bill print key Past void key Subtotal void key KEY TOP GDSC %1 to %3 COVER CNT N.C C_NEXT EDIT TIP RP ROUND PLU MENU1 to 50 MACRO1 to 4 UPSIZE CAP.1 to 10 GLU RECALL MSG1 to 5 MSG# DELETE NEXT $ MDSE SBTL TRAY SBTL RTN GAS SBTL AMT #/TM REPEAT IND. PAYMENT INQ CUST PRICE CHANGE BIRTH TABLE # VOID MENU RFND SALE DESCRIPTION Group discount %1 to 3 keys Cover count key New check key Condiments next key Edit tip key Repeat round key PLU menu 1 to 50 keys Macro 1 to 4 keys Upsize key Data capture 1 to 10 keys Table # recall key Message 1 to 5 keys Message menu key Delete key Next higher dollar key Merchandise subtotal key Tray subtotal key Return key Gasoline sales subtotal key Amount entry key Non-add code / Date & Time display key Repeat key Individual payment key Inquiry key Customer code entry key UPC price change key Birthday entry key Table no. (seat no.) entry key Void menu key Refund sale key
3) TEST PROGRAMMING KEY SHEET LAYOUT

RECEIPT JOURNAL
4) BLANK KEY SHEET LAYOUT

RECEIPT JOURNAL
? ) P
! Q A @ W S Z
(SHIFT)
,
( O L
<
= /
>
(INS)
(CANCEL) (RECALL)
# E D X
$ R F C
% T G V
^
Y H B
& U J N
(DEL)
I
K M
; .
(DC)
:
PAGE UP PAGE DOWN
(ENTER)
@ FOR
CL 8 5 2 9 6 3
SBTL CA/AT
(UPDATE)
7 4 1 00
0 000
: The shaded area contains the character keys which are used for programming characters. KEY TOP SHIFT DESCRIPTION Used for programming characters. Entering upper-case letters You can enter an upper-case letter by using this key. Press this key just before you enter the upper-case letter. You should press this key each time you enter an upper-case letter. Used for programming characters. Entering double-size characters This key toggles the double-size character mode and the normal-size character mode. The default is the normal-size character mode. When the double-size character mode is selected, the letter "W" appears at the bottom of the display. Used for programming characters. To select a text editing mode Toggles between the insert mode ("_") and the overwrite mode ("s"). Used for programming characters. To delete a character or figure Deletes a character or figure in the cursor position.
3. DISPLAY
1) OPERATOR DISPLAY Screen example 1 (REG mode)
Server code Scroll guidance: Mode name When a transaction information occupies more than 5 lines, scroll key(s) appears to indicate you can scroll to the direction.
DC
Status area 1: Sales information area: Sales information you have just entered such as items and prices will appear between 2nd line and 6th line. Total is always appear at 7th line. Status area 2: Time Numeric entry
INS
DEL
BACK SPACE Used for programming characters. To delete a character or figure Backs up the cursor for deleting the character or figure at the left of the cursor. When your POS terminal is in the insert mode, this key deletes the character or the value at the cursor position. Used to move the cursor. ENTER TL CANCEL PREV RECORD NEXT RECORD PAGE DOWN PAGE UP CL Used to program each setting. Used to finalize programming. Used to cancel programming and to get back to the previous screen. Used to go back to the previous record, e.g. from the department 2 programming window back to the department 1 programming window. Used to go to the next record, for example, in order to program unit prices for sequential departments. Used to scroll the window to go to the next page. Used to scroll the window to go back to the previous page. Used to clear the last setting you have programmed or clear the error state. Used to toggle between two or more options. SBTL RECALL Numeric keys Used to list those options which you can toggle by the [ ] key. Used to call up a desired code. Used for entering figures.
Price level shift indicator (P1-P6) PLU level shift indicator (L1-L5) Receipt shift indicator (r) Stock alarm indicator ( ! )
: Shows the PLU/UPC price level currently selected. : Shows the PLU level currently selected. : Shows the receipt shift status. : Appears when the stock of the PLU which you entered is zero, negative or reaches the minimum stock. : Appears when an electronic message is received. (Status 1 area) : Appears when the receipt ON-OFF function signs OFF. : Appears in the lower right corner of the screen when the cash in drawer exceeds a programmed sentinel amount. The sentinel check is performed for the total cash in drawer.
Electronic message indicator (M) Receipt ON/OFF status indicator (R) Sentinel mark (X)
Screen example 2 (PGM mode)

Programming item information area Programming area: Programmable items are listed.
4. KEYS AND SWITCHES

1) MODE SWITCH AND MODE KEYS
MA SM
REG
Double-size character mode indicator (W): Appears when the double-size character mode is selected during text programming.
Caps lock indicator (A/a): The upper-case letter A appears when caps lock is on, and the lower-case letter a appears when caps lock is off during text programming.
OP X / Z OFF PGM1 PGM2
MGR X1 /Z1 X2/Z2
Manager key (MA)
Submanager key (SM)
Screen save mode

When you want to save the electric power or save the displays life, use the screen save function. This function can turn the LCD off when a server does not operate the POS terminal for an extended period of time. You can program the time for which your POS terminal should keep the normal status (in which the backlight is "ON") before it goes into the screen save mode. To go back to the normal mode, press any key. Device type Dot format Dot size Dot space Dot color Back color LCD display 320(W) x 240(H) Full dot 0.24 (W) x 0.21 (H) mm 0.02 mm White Dark blue
Operator key (OP)
The mode switch has these settings: OFF: This mode locks all register operations. No change occurs to register data.
2) DISPLAY ADJUSTMENT (OPERATION DISPLAY)

You can adjust the contrast of the display by using the contrast control, and also you can adjust the display angle. Pull up the tab, the display will head up.
OP X/Z: This setting allows cashiers/clerks to take X or Z reports for their sales information. (This setting may be used only when your register has been programmed for "OP X/Z mode available" in the PGM2 mode.) REG: PGM1: For entering sales To program those items that need to be changed often: e.g., unit prices of departments, PLUs or UPCs, and percentages To program all PGM1 items and those items that do not require frequent changes: e.g., date, time, or a variety of register functions For managers and submanagers entries The manager can use this mode to make entries that are not permitted to be made by cashiers/servers -for example, after-transaction voiding and override entry. To take the X/Z report for various daily totals To take the X/Z report for various periodic (weekly or monthly) consolidation
MA OP
Service key (SRV)
SM
SRV
Tab Contrast control Turning the control backwards darkens the display and turning it forwards lightens the display.
PGM2:
MGR:
The backlight in the display is a consumable part. When the LCD display may no longer be adjusted and becomes darker, you should change the backlight.
X1/Z1: X2/Z2:
3) CUSTOMER DISPLAY (Pop-up-type)
2) DRAWER LOCK KEY

This key locks and unlocks the drawer. To lock it, turn 90 degrees counterclockwise. To unlock it, turn 90 degrees clockwise.
SK1-2
4) PRINTER COVER LOCK KEY

This key locks and unlocks the printer cover. To lock it, turn 90 degrees counterclockwise. To unlock, turn 90 degrees clockwise.
5. PRINTER
1) PRINTER (PR-58HA)
Item No. of station Validation Printing system No. of dot 2: Receipt and Journal No Line thermal Receipt: Journal Dot pitch Horizontal: Vertical: Font Printing capacity 10 dots (W) x 24 dots (H) Receipt: Journal: Character size Print pitch 1.25 mm (W) x 3.0 mm (H): Column distance: Row distance: Paper feed speed Reliability Paper end sensor Cutter Paper near end sensor Printing area
106(848dots) (7.0) 360dots (45) (5.5)
Description
360 dots 360 dots 0.125 mm 0.125 mm
Max. 30 characters Max. 30 characters At 10 x 24 dots 1.5 mm 3.75 mm
Approximate 65 mm/s Mechanism: Yes (Receipt and Journal) Manual No MCBF 5 milion lines
0.125
(5.5)
(7.0)
57.5 0.5
5.0
UNIT: mm
Item Printing format 12 x 24 font
Description
1.5 (12dots)
1.5 (12dots)
0.125
0.125
3.75 (30dots)
3.75 (30dots)
3.0 (24dots)
UNIT: mm
2) PAPER
Item Name Roll dimension Thickness Description Heat-quality paper 57.5 0.5 mm in width 0.06 mm to 0.08 mm
2) MONEY CASE
Separation from the drawer Allowed Separation of the coin compartments from the money case Bill separator Number of compartments U version Allowed Disallowed No 7B/5C A version Allowed Disallowed Standard (1 pcs) 4B/8C
6. DRAWER
1) SPECIFICATION
(1) Drawer box and drawer
Model name Size Color Material Bell Release lever Drawer open sensor SK-460 445 (W) x 464 (L) x 118 (H) GRAY 368 Metal Standard equipment; Front key Standard equipment
Bill separator
U version : 7B/5C
A version : 4B/8C
3) LOCK
Location of the lock Method of locking and unlocking Front Locking: Insert the drawer lock key into the lock and turn it 90 degrees counterclockwise. Insert the drawer lock key into the lock and turn it 90 degrees clockwise.
Unlocking:
Key No.
SK1-2
7. RS232 INTERFACE
This machine has two RS232 standard ports for communication to PC, Hand scanner (ER-A6HS1) and etc.
1) PORT 1 (CH1) (CN402)

Connector type: D-SUB 9pin Data rate: max. 38,400 bps
2) PORT2 (CH2) (CN403)

Connector type: Modular jack RJ45 8pin Data rate: max. 115,200 bps
1 2 3 4 5 6 7 8 9
/CD RD SD /ER GND /DR /RS /CS VCC(+5V) S401 /CI
1 2 3 4 5 6 7 8
/RS /ER SD GND RD /DR /CS
CD S404
CI
S403 GND VCC (+5V)
3) OPTIONAL DEVICES THAT CAN BE CONNECTED

Standard port Port No. Type CI/+5V selectable ER-A6HS1 (+5V necessary) Scanner (+5V not necessary) Modem PC Printer, Scale POS utility, 02fd.exe Port1: CH1 D-SUB 9pin Port2: CH2 Moduler RJ45 Option port (ER-A5RS) Port3: D-SUB 9pin Port4: D-SUB 9pin
The ER-A6HS1 cannot be connected to port 2, 3 or 4 because it requires +5V. The modem cannot be connected to port 2 because it uses a different signal line. For the modular RJ45 to D-Sub 9pin conversion cable, see the following.
Moduler RJ45 CD S404 CI /RS /ER SD GND S403 GND VCC (+5V) RD /DR /CS 1 2 3 4 5 6 7 8 (Open)
D-sub 9pin 7 4 3 1 5 2 6 8 9 /RS /ER SD /CD GND RD /RS /CS /CI
CHAPTER 2. OPTIONS
1. SYSTEM CONFIGURATION
Satellite machines Max 63 units (Batch communications) PC <Local purchase>
INLINE Communication
(Ethernet)
RS-232 Communication Master machine Std. 2/ Max.4 ports PC <Local purchase>
RS-232 Board ER-A5RS <Option>
Remote printer/Slip <Local purchase>
Pole Display <Option> UP-P16DP
Expansion memory board <Option> UP-S02MB UP-S04MB
Hand Scanner ER-A6HS1 Laser Scanner <Local purchase>
Scale
CAT Terminal <Local purchase> <Local purchase>
Remote Drawer <Option> ER-03DW/ 04DW
Coin Dispenser <Local purchase> MCR <Option> UP-E13MR
Symbol/PartsCod) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
2. SALES OPTIONS
No. 1 CLASSIFICATION Memory COMPONENT NAME Expansion RAM board MODEL NAME UP-S02MB UP-S04MB 2 3 Display Drawer Remote display (Pole type) Remote drawer UP-P16DP ER-03DW ER-04DW 4 5 6 On-line function Card reader Scanner RS232 I/F board MCR (Magnetic Card Reader) Bar code hand scanner ER-A5RS UP-E13MR ER-A6HS1 REMARK 2M bytes PS-RAM board 4M bytes PS-RAM board 11-Dig.7-Seg. + 16-Dig.Dot 7B/5C coin case 5B/5C coin case 2 ports RS232 I/F ISO Type 1 : 3 stripe card
3. LOCAL PURCHASE OPTIONS

No. 1 2 3 4 5 6 External printer Slip printer Scale I/F Coin dispenser Color kitchen monitor CAT terminal COMPONENT NAME MODEL NAME TM-T88/85, TM-88 (2), TM-T80 TM-U200, TM-300 TM-295 REMARK
1: Please consult with your Sharp regional sales manager.
4. SERVICE OPTIONS
No. 1 2 Mode key grip cover Drip proof mode switch cover NAME PARTS CODE PRICE AX BA DESCRIPTION For MA key only
5. SERVICE TOOLS
No. 1 2 3 4 5 Service key RS232 Loop Back Connector RS232 modular Loop Back Connector Expansion PWB for option board MCR test card NAME PARTS CODE PRICE AF BC BC BU BL For RS232 D-SUB 9pin connector For RS232 RJ45 Modular jack connector For ER-A5RS For UP-E13MR DESCRIPTION
6. SUPPLIES
No. 1 2 3 4 5 Thermal roll paper Thermal roll paper (High preservative type) Key sheet (Normal key layout) Key sheet (Character key layout) Key sheet (Blank key layout) NAME PARTS CODE PRICE BA BD AR AH AG DESCRIPTION 5 Rolls / pack 5 Rolls / pack
7. HOW TO USE SERVICE TOOLS

1) EXPANSION PWB : CKOG-6708RCZZ External view 2) MCR TEST CARD : UKOG-2357RCZZ Used when executing the diagnostics of the UP-E13MR. External view
Purpose 1 : Used for servicing and repairing of options (such as the ER-A5RS) which are connected with the main body option connector.
[Procedure 1]
Use an insulator base as shown in the shaded section when performing servicing.
UP-700 Expansion PWB (CKOG-6708RCZZ) A ER-A5RS PWB
Loop back connectors UKOG-6705RCZZ
Main PWB
Base
To check the option I/F PWB from the solder side, connect the I/F PWB to OPTCN2. To check from the parts side, connect to OPTCN3. (Note) The option I/F PWB should be held horizontally so that no excessive stress is applied to connecting section .
[Procedure 2]
Pop up String UP-700 Expansion PWB (CKOG-6708RCZZ) ER-A5RS PWB Control ROM Loop back connectors UKOG-6705RCZZ
Main PWB
Put a string between the pop up and the option PWB. Adjust the length of the string so that the CKOG-6708RCZZ and the option PWB are not binding. Once verified, then you may proceed with performing service.
CHAPTER 3. SERVICE PRECAUTION

1. IPL (Initial Program Loading) FUNCTION
1) INTRODUCTION
The application software of the UP-700 is written in the flash ROM. In the following cases, writing of the application software into the flash ROM is required. 4. 5. 6. Place the mode key to any position except OFF or SRV. Turn on the power switch of the UP-700. The following display is shown and the IPL procedure is started. When the procedure is completed, the message of "Completed" is shown.
When the flash ROM is replaced with a new one. The service part
flash ROM does not include the application software in it.
When IPL writing is required because of a change in the software.

The service part of the main PWB unit includes the flash ROM with the application software written in it, and there is no need for writing the application software when replacing the main PWB unit.
IPL from PROM Version check Erase
2) IPL PROCEDURE
There are two ways for the IPL procedures.
IPL from P-ROM IPL from PC communication (Please refer to the next section)
The detailed descriptions on the above procedures are given below.
26 27 28 29 2A 2B
IPL write start
3) IPL FROM P-ROM

Master ROM-1 : VHI27801RAU1A Master ROM-2 : VHI27801RAV1A Before installation, turn off the power switch on the UP-700 and unplug the AC cord from the AC outlet. 1. Insert a screwdriver into the slit on the right side of the lower cabinet to remove the option RAM case.
2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F Verify Completed. IPL write completed
7. 8. 9.
Turn off the power switch of UP-700. Remove the ROMs IC sockets on the IPL ROM PWB. IPL switch (SW301) on the IPL ROM PWB: Set the IPL switch (SW301) to the OFF position.
10. Perform one of the master reset procedures.
2. 3.
IPL switch (SW301) on the IPL ROM PWB: Set the IPL switch (SW301) to ON position. Install the ROMs into the IC sockets on the IPL ROM PWB as shown below.
ROM1 ROM2
ROM1
on off
ROM2
SW301
Symbol/PartsCod) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
2. UP-700 UTILITY TOOLS

1) OUTLINE
This Specification document describes the explanation about "POSUTILITYTOOL.EXE and "02FD.EXE". "POSUTILITYTOOL.EXE"and "02FD.EXE" works on Windows 95/98 of PC and they have the following Functions by connecting UP-700 with RS232. POSUTILITYTOOL.EXE 02FD.EXE : IPL of UP-700 Program Object : All RAM Data Upload/Download (PC software tool instead of the current ER-02FD.)
PC D-SUB 9pin - D-SUB 9pin cable UP-700:CH2
2) CONNECTION
PC and UP-700 are connected by RS232. Connect the CH2 port of the UP-700 to the RS-232 interface of the PC.
D-SUB 9pin - modular RJ-45 conversion cable
RS232 Cable Connecting:

[PC] D-sub 9pin 7 4 3 1 5 2 6 8 9 7 4 3 1 5 2 6 8 9 [UP-700] Moduler RJ45 7 4 3 1 5 2 6 8 9 1 2 3 4 5 6 7 8 (Open) /RS /ER SD GND RD /DR /CS
D-sub 9pin /RS /ER SD /CD GND RD /DR /CS /CI
CI S404
CD
SD GND RD
S403 VCC (+5V) GND
3) PROCEDURE
3) -1. POS UTILITY TOOL
No 1 Procedure on P.C. side Install "POSUTILITYTOOL.EXE" on the P.C. 2 3 Turn OFF the power. Select "IPL Mode". Set the "IPL Switch" (SW302) of the UP-700 to "ON". No Procedure on UP-700 side
on
off
on
off
SW302
4 5
Turn ON the power. Starting of "IPL Mode". The UP-700 displays. "IPL from Serial I/O"
IPL from Serial I/O
Connect the P.C. and the UP-700 (CH2) via RS232. (Fig 1)
No 7
Procedure on P.C. side Execute the "POSUTILITUTOOL.EXE" on the P.C. *Please close all other applications while using this utility.
No
Procedure on UP-700 side
Select the ROM object Files by clicking the "Add Files.." button.
Push the "SEND" button. Program data is sent to the UP-700 automatically.
Program data is received from P.C. automatically. The UP-700 display.

IPL from serial I/O Connected IRDA 115200 21 22 23 24 25 26 27 28
10
When data sending is completed, the initial Window is shown after "Complete" window.
10
The UP-700 displays "Completed."

IPL from Serial I/O Connected IRDA 115200 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F Completed. IPL from Serial I/O Connected IRDA 115200 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F Completed.
11 12 13
Turn OFF the power. Select "Normal Mode". Set the "IPL switch" to "OFF". (Ref. Hardware manual) Execute the "Service Reset" on UP-700.
3) -2. 02FD
No 1 Procedure on P.C. side Install the "02FD.EXE" on the P.C. ALL RAM Data UpLoad : Go to "2" ALL RAM Data DownLoad : Go to "9" ALL RAM Data UpLoad Connect the P.C. and the UP-700 (CH2) via RS232. (Fig 1) No Procedure on UP-700 side
Enter the SRV mode. Select " 2 SETTING ". Select " 14 BACKUP SEND" displays
BACKUP SEND SEND DATA SPEED ALL RAM PROGRAMMED SPEED
Execute the "02FD.EXE" on the P.C. *Please close all other apprications while using this utility.
Set the Communication method by pushing the "Setting" Button.
6 7
Push the "OK" Button. Push the "Receive Start" Button. And Select the Receiving File. Communication starts.
Push CA/AT key. The UP-700 displays

SENDING 00000
The UpLoad is completed. The initial Window is shown. Push the "Exit" Button. ALL RAM Data UpLoad Connect the P.C. and the UP-700 (CH2) via RS232. (Fig 1)
The UpLoad is completed. The SETTING menu is shown. Enter the SRV mode. Select " 2 SETTING". Select " 15 BACKUP RECEIVE" The UP-700 shows
BACKUP RECEIVE SPEED PROGRAMMED SPEED
10
Push the CA/AT key.
No 11
Procedure on P.C. side Execute the "02FD.EXE" on the P.C. *Please close all other apprications while using this utility.
No
Procedure on UP-700 side
12
Set the Communication method by pushing the "Setting" Button.
13 14
Push the "OK" Button. Push the "Transmit Start" Button. And Select the Sending File. Communication starts.
14
The UP-700 displays

RECEIVING 00000
15
The DownLoad is completed. The initial Window is shown. Push the "Exit" Button.
15
DownLoad is completed. The SETTING menu is shown. Execute the " Service Reset " on the UP-700
16
3. NOTE FOR HANDLING OF LCD

The LCD elements are made of glass. Use extreme care when
handling the LCD. Any strong shock applied to the LCD can cause damage.
If the LCD element is broken and the liquid has leaked, do not
come in contact with it. If the liquid is attached to your skin or cloth, immediately clean with soap.
Use the unit under the rated conditions to prevent against damage. Be careful not to drop water or other liquids on the display surface. The reflection plate and the polarizing plate are easily scratched.
Be careful not to touch them with hard objects such as glass, tweezers etc. Never hit, push, or rub the surface with hard objects.
When installing the unit, be careful not to apply stress to the LCD
module. If excessive stress is applied, abnormal display or uneven color may result.
CHAPTER 4. SRV. RESET AND MASTER RESET

The SRV key is used for operating in the SRV mode.
MRS-2 (Master resetting 2)

Used to clear all memory and keyboard contents. This reset returns all programming back to defaults. The keyboard must be entered by hand. This reset is used if an application needs a different keyboard layout other than that supplied by a normal MRS-1.
1. SRV. RESET (Program Loop Reset)

Procedure
Method 1
1) Turn off the AC switch. 2) Set the mode switch to (SRV) position. 3) Turn on the AC switch. 4) Turn to (SRV) position from (SRV) position.
Procedure
1) Turn off the AC switch. 2) Set the MODE switch to the (SRV) position. 3) Turn on the AC switch. 4) While holding down the JOURNAL FEED and RECEIPT FEED keys, turn to the (SRV) position from the (SRV) position. 5) Key position assignment: After the execution of a MRS-2, only the RECEIPT FEED and JOURNAL FEED keys can remain effective on key assignment. Any key can be assigned on any key position on the main keyboard. [key setup procedure]
MRS-2 executed
Method 2
1) Set the mode switch to PGM2 position. 2) Turn off the AC switch. 3) While holding down the JOURNAL FEED key and RECEIPT FEED keys, turn on the AC switch. Note: When disassembling and reassembling always power up using method 1 only. Method 2 will not reset the CKDC9. Note: SRV programming job#926-B must be set to a "4" to allow the PGM program loop reset.
Key position set
*2 Free key
PRG. RESET
*1
Free key setup complete.
Disable
MASTER RESET
NOTES: *1: When the 0 key is pressed, the key of the key number on the display is disabled. *2: Push the key on the position to be assigned. With this, the key of the key number on the display is assigned to that key position. *3: When relocating the keyboard, the PGM 1/2 modes use the standard key layout. Key No. 001 002 003 004 005 006 007 008 009 010 Key name Key No. 011 012 013 014 015 016 017 018 019 020 Key name Key No. 021 022 023 Key name
2. MASTER RESET (All memory clear)

There are three possible methods to perform a master reset.

Used to clear all memory contents and return the machine back to its initial settings. Return the keyboard back to the default layout.
Procedure
1) Turn off the AC switch. 2) Set the MODE switch to the (SRV) position. 3) Turn on the AC switch. 4) While holding down the JOURNAL FEED key, turn to the (SRV) position from the (SRV) position.
Symbol/PartsCod) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Master resetting 3 requires the entry of Serial No. data in addition to Master resetting 2. After completion of the MRS-3, the following operations and programming will be inhibited. 1. GT programming. 2. All memory download via RS-232. 3. GT resets with Z report. (Z report can be made, but the GT will not be reset.)
Procedure
1) Turn off the AC switch. 2) Set the reset switch to the "SRV" position. 3) Turn on the AC switch. 4) While holding down the JOURNAL FEED key and MRS-3 key, turn to the (SRV) position from the (SRV) position. MRS-3 key : UP-700=[PLU72] key 5) The product serial No. input window is displayed as shown below. DISPLAY:
SERIAL No. 00000000
Enter the product serial No. of this POS and enter the [CA/AT] key. 6) Key position assignment: After the execution of MRS-2, only the RECEIPT FEED and JOURNAL FEED keys can remain effective on key assignment. Any key can be assigned on any key position on the main keyboard. [key setup procedure]
MRS-2 executed
Key position set
*2 Free key
*1
Free key setup complete.
Disable
MASTER RESET
NOTES: *1: When the 0 key is pressed, the key of the key number on the display is disabled. *2: Push the key on the position to be assigned. With this, the key of the key number the on display is assigned to that key position. *3: When relocating the keyboard, the PGM 1/2 modes use the standard key layout. Key No. 001 002 003 004 005 006 007 008 009 010 Key name Key No. 011 012 013 014 015 016 017 018 019 020 Key name Key No. 021 022 023 Key name
CHAPTER 5. DIAGNOSTICS SPECIFICATIONS

1. GENERAL DESCRIPTION
This Diag Program consists of a number of Diag. programs for the UP-700, which facilitate the PWB check, process check and the operation check of the system during servicing. The Service Diag. programs are all contained in the standard ROM.
2) RAM & ROM & SSP DIAGNOSITCS

This program tests the standard RAM, expanded RAM, standard and service ROMs, and SSp circuit. RAM&ROM&SSP is selected on the MAIN MENU, the following sub-menu screen appears. The cursor shown in reverse video can be moved using the up/down arrow keys. Move the cursor to the menu item you want and press the ENTER key to execute the corresponding program. Press the CANCEL key to return the screen to this submenu.
RAM&ROM&SSP DIAG Standard RAM Check UP-S04MB Check UP-S02MB Check Standard ROM Check
2. SYSTEM COMPOSITION
UP-700 only
UP-700
Fig 2-1. Service
Service ROM Check SSP Check
2)-1. Standard RAM check
3. DIAG.
Starting the Diag. Program
The Diag. Program is written on the external ROM, which is executed by the CPU (H8/510) and runs under the following conditions: The logic power supply is normal. (+5V, VCKDC, POFF, +24V) Both the I/O pins of the CPU and the CPU internal logic are normal, and the CKDC9 and MPCA9, system bus, and standard ROM/RAM are normal.
Checking The program performs the following checks on the standard 512KB of RAM. Data in memory remains unchanged before and after the checks. The following operations are performed for the memory addresses to be checked (780000H - 7FFFFFH). PASS1 : Save data in memory PASS2 : Write data "0000H" PASS3 : Read and compare data "0000H" and write data "5555H". PASS4 : Read and compare data "5555H" and write data "AAAAH" PASS5 : Read and compare data "AAAAH" PASS6 : Return data into memory If any comparison is not normal during the check sequence from PASS 1 through 6, the error message appears. If any error is not found up to the final address, the sequence ends normally. Then, another round of address checks is carried out using the above check sequence If an error occurs, the error message appears and the check stops. The read/write of the address where the error occurs is repeated. Check point address = 780000H, 780001H 780002H, 780004H 780008H, 780010H 780020H, 780040H 780080H, 780100H 780200H, 780400H 780800H, 781000H 782000H, 784000H 788000H, 790000H 7A0000H, 7C0000H
1) EXECUTING DIAG PROGRAM

To start the Diag. Program, enter the SRV mode. Select the option item DIAGNOSTICS from the MENU using the cursor keys and press the ENTER key. The DIAG. MAIN MENU appears on the screen as shown below. The cursor is displayed in reverse video and can be moved using the up/down arrow keys. Move the cursor to the menu item you want and press the ENTER key to execute the corresponding Diag. program. When each Diag. program is completed, the screen returns to the DIAG. MAIN MENU. Press the CANCEL key to exit the Diag. Program and the screen returns to the SRV mode menu screen.
UP-700 DIAG V1.0A PRODUCT&TEST RAM&ROM&SSP CLOCK&KEY&SWITCH SERIAL I/O DISPLAY&PRINTER MCR&DRAWER TCP/IP
Symbol/PartsCod) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Display The capacity checked is displayed in units of 64KB.

UP-S02MB Check 2048KB:PASS!!(or ERROR!!) Error:XXXXXXH Write:XXXXH Read:XXXXH
Standard RAM Check 512KB:PASS!!(or ERROR!!) Error:XXXXXXH Write:XXXXH Read:XXXXH
The error address and bit are displayed only when an error occurs (They are not displayed if there is no error.) How to exit the program You can exit the program by pressing the CANCEL key after the results are displayed.
The error address and bit are displayed only when an error occurs (They are not displayed if there is no error.) How to exit the program You can exit the program by pressing the CANCEL key after the results are displayed.
2)-2. UP-S02MB Check

Checking The program checks for the presence of the UP-S02MB in the following procedure. Data in memory remains unchanged before and after checking. i. Write 55AAH in 9FFFFEH. ii. Read 9FFFFEH and compare the data with 55AAH.If both data are correct and BFFFFEH is the same as 55AAH, perform the following tests are performed. If not correct, the message "0KB: ERROR!!" appears and checking ends. The following checks are performed on the UP-S02MB. The following operations are performed for the address space to be checked (800000H - 9FFFFFH). PASS1 : Save data in memory. PASS2 : Write data "0000H". PASS3 : Read and compare data "0000H" and write data "5555H". PASS4 : Read and compare data "5555H" and write data "AAAAH". PASS5 : Read and compare data "AAAAH". PASS6 : Return data into memory. If any comparison is not normal during the check sequence from PASS 1 through 6, the error message appears. If any error is not found up to the final address, the sequence ends normally. Then, another round of address checks is carried out using the above check sequence. If an error occurs, the error message appears and the checking stops. The read/write of the address where the error occurs is repeated. Check point address = 800000H, 800001H 800002H, 800004H 800008H, 800010H 800020H, 800040H 800080H, 800100H 800200H, 800400H 800800H, 801000H 802000H, 804000H 808000H, 810000H 820000H, 840000H 880000H, 900000H
2)-3. UP-S04MB Check

Checking The program checks for the presence of the UP-S04MB in the following procedure. Data in memory remains unchanged before and after checking. i. After writing 55AAH in BFFFFEH, write AA55H in 9FFFFEH. ii. Read BFFFFEH and compare the data with 55AAH. Data in BFFFEH is correct, the following checks are performed. Data read is AA55H, the message "UP-S02MB!!" appears and the check ends. If the data read is not either 55AAH or AA55H, the message "0KB:ERROR!!" appears and the check ends. The following checks are performed on the UP-S04MB. The following operations are performed for the address space to be checked (800000H - BFFFFFH). PASS1 : Save data in memory. PASS2 : Write data "0000H". PASS3 : Read and compare data "0000H" and write data "5555H". PASS4 : Read and compare data "5555H" and write data "AAAAH". PASS5 : Read and compare data "AAAAH". PASS6 : Return data into memory. If any comparison is not normal during the check sequence from PASS 1 through 6, the error message appears. If any error is not found up to the final address, the sequence ends normally. Then, another round of address checks is carried out in the above check sequence. If an error occurs, the error message appears and the checking stops. The read/write of the address where the error occurs is repeated. Check point address = 800000H, 800001H 800002H, 800004H 800008H, 800010H 800020H, 800040H 800080H, 800100H 800200H, 800400H 800800H, 801000H 802000H, 804000H 808000H, 810000H 820000H, 840000H 880000H, 900000H A00000H
JOURNAL print
BLOCK Version. 20=** 21=** 22=** 23=** 24=** 25=** 26=** 27=** . . . . . . . . . . . 3C=** 3D=** 3E=** 3F=**
How to exit the program You can exit the program by pressing the CANCEL key after the result of checking is displayed.
UP-S04MB Check 4096KB:PASS!!(or ERROR!!) Error:XXXXXXH Write:XXXXH Read:XXXXH
2)-5. SERVICE ROM Check

The error address and bit are displayed only when an error occurs (They are not displayed if there is no error.) How to exit the program You can exit the program by pressing the CANCEL key after the results are displayed. Checking The SERVICE ROM area composed of two EPROMs (D00000H EFFFFFH) is added in units of bytes for each chip. If the lowest 2 digits are 10H, it is regarded as normal. In addition, the ROM version and model name code stored in the addresses D1FFE0H - D1FFFFH where the ROM version and checksum correction data are stored are displayed. Data (ASCII) is stored in the following formats: D1FFE0H~D1FFEFH : Model name CODE(Example: "UP-600", to be displayed until data is 00H.) D1FFF0H~D1FFF9H : 27801R****(****=PROGRAM VERSION) D1FFFAH~D1FFFBH : BLOCK NO.("20"~"2F") D1FFFCH : TERMINATOR("=") D1FFFDH~D1FFFEH : BLOCK VERSION(Example:"00") D1FFFFH : CHECK SUM correction DATA This SERVICE ROM is used to write data into FLASH ROM and if any error occurs during rewriting of the FLASH ROM, and it is not possible to resume the operation. Its configuration is the same as the standard ROM. 0 PAGE (BLOCK) where the IPL is stored displays the PROGRAM VERSION of the IPL to make it possible to manage individual programs. Display The capacity checked is displayed in units of 64KB.
2)-4. Standard ROM Check

Checking The standard ROM area (200000H - 3FFFFFH) is added in units of bytes. When the lowest 2 digits of the result is 20H, it is regarded as normal. In addition, the ROM version and model name code stored in the addresses 31FFE0H - 31FFFFH where the ROM version and checksum correction data are stored are displayed. Data (ASCII) is stored in the following formats: 31FFE0H~31FFEFH : Model name CODE (Example: "UP-600", to be displayed until DATA becomes 00H.) 31FFF0H~31FFF9H : 27801R****(****=PROGRAM VERSION) 31FFFAH~31FFFBH : BLOCK NO.("20"~"3F") 31FFFCH : TERMINATOR ("=") 31FFFDH~31FFFEH : BLOCK VERSION (Example: "00") 31FFFFH : CHECK SUM correction DATA FLASH ROM used as the standard ROM has 64K-byte-unit rewrite BLOCKs. To perform VERSION management in the BLOCK unit, these BLOCKs have the same 16 byte organization as those after the previous 31FFF0H and arranged every 64KBYTE. At this time, the checksum for each BLOCK is corrected to be 01H so that the entire 2MBYTE become a total of 20H. Regarding the display of the PROGRAM VERSION, the FLASH write MASTER EPROM has 2-chip 8Mbits to allow management of the block units of the chip. The PROGRAM VERSION stored in blocks at 21H and 31H are displayed. 0 PAGE (BLOCK) where the IPL is stored, displays the PROGRAM VERSION of the IPL to make it possible to manage individual programs. Display The capacity checked is displayed in units of 64KB.
Service ROM Check ROM1:PASS!!(or ERROR!!) ROM2:PASS!!(or ERROR!!) APL: 27801R**** 27801R**** IPL:**
JOURNAL print
BLOCK Version. 20=** 21=** 22=** 23=** 24=** 25=** 26=** 27=** . . . . . . . . . . . 3C=** 3D=** 3E=** 3F=**
How to exit the program You can exit the program by pressing the CANCEL key after the result of checking is displayed.
Service ROM Check PASS!!(or ERROR!!) APL: 27801R**** 27801R**** IPL:**
2)-6. SSP Check

Checking When started, this check program automatically sets the test SSP, performs SSP check and displays the check result. The SSP check sets check data in the empty space in the SSP entry register. After checking is completed, only the check data is erased. Any setting remains intact before and after this check program is executed. Display
3)-4. Mode Switch Check

Checking The mode switch position code is displayed in a hexadecimal number. SRV:0, PGM2:1, PGM1:2, OFF:E, OP X/Z:3, REG:4, MGR:5, X1/Z1:6, X2/Z2:7 Intermediate code:E, Multiple error F
4) RS232 I/F DIAGNOSTICS

SSP Check PASS!!(or ERROR!!)
The program tests the RS232 interface for the main PWB and the optional board ER-A5RS. Attach a 9-pin D-sub loop back connector (UKOG-6717RCZZ) wired as shown in Fig. 3-11, to the port you are going to test.
CD RD SD ER
How to exit the program You can exit the program by pressing the CANCEL key after the results are displayed.
1pin 2pin 3pin 4pin 5pin 6pin 7pin 8pin 9pin
GND DR RS CS CI
3) TIMER & KEYBOARD & CLERK SWITCH DIAGNOSTICS

This program checks the operation of the CKDCs clock crystal, keyboard and tests the clerk switch and mode switch. You can return to the Diag menu screen by pressing the CANCEL key.
Fig. 3-11. Wiring diagram of loop back connector (UKOG-6717RCZZ) The following menu appears on the screen. The cursor shown in reverse video can be moved using the up/down arrow keys. Move the cursor to the menu item you want to execute and select by pressing the Enter key to the corresponding Diag. Program. Press the CANCEL key to return the screen to this submenu. When setting the channel for the RS232 interface, do not set more than two ports to the same channel. The UP-700 accommodates up to one ER-A5RS board, but use caution not to allow each port to have the same channel; otherwise the hardware might be destroyed.
Timer&Key&Clerk DIAG YY/MM/DD&HH:MM:SS KEY CODE=*** CLERK CODE=*** MODE SWITCH=* (0~7,E:Intermediate position, F:Multiple ERROR)
RS232 I/F DIAG CH1 Check CH8 Check
3)-1. Timer Check

Checking Check the operation of the CKDC9s clock crystal. The area showing "YY/MM/DD & MM:HH" is continuously displayed. Check whether the display blinks in black and white every 0.5 seconds and the time shown is updated. When Diag. is started, the channel check is performed and only the channels already set appear on screen. Note: The channel numbers displayed are logical numbers on software, In practical terms, CH1 means the CH1 of the rear connector of the POS and CH8 means the CH2 of the rear connector of the POS. If options are installed, only the ones (CH2 - CH7) which have been set will be added and displayed.
3)-2. Keyboard Check

Checking The program check the input through the keyboard of the UP-700. A 3-digit position code corresponding to a key pressed appears on screen, along with a catch sound.
3)-3. Clerk SW Check (not for U version)

Checking The code of the key inserted into the clerk key switch appears in a decimal number.
4)-1. CHANNEL Check

Checking The screen shows only the channels for which have been set and are connected to the ECR. Compare the channels shown on the screen and the settings of the channel setting DIP SW of the RS232 interface board. The RS232 on the main PWB of the UP-700 is fixed to CH1 and CH8. It is therefore necessary for the ER-A5RS to set the channel to any of CH2 - CH7. (Ref) ER-A5RS channel settings ("1" = SW OFF, "0" = SW ON)
ER-A5RS CON3 (RSCN1)

S1-1 0 0 0 0 1 1 1 1 S1-2 0 0 1 1 0 0 1 1 S1-3 0 1 0 1 0 1 0 1 CHANNEL Disabled No setting allowed (Standard RS) CHANNEL 2 CHANNEL 3 CHANNEL 4 CHANNEL 5 CHANNEL 6 CHANNEL 7
iii. TIMER CHECK (RS232 ON BOARD TIMER) Before starting the check ii, perform the RCVDT start of the timer you want to check and set to 5 ms. Make sure::
No TRQ- is generated during the implementation of check ii. TRQ- is generated at 5 ms after check ii is completed.
Display
RS232 CH1 Check PASS!!(or ERROR!!)
ER-A5RS CON4 (RSCN2)

S1-4 0 0 0 0 1 1 1 1 S1-5 0 0 1 1 0 0 1 1 S1-6 0 1 0 1 0 1 0 1 Disabled No setting is allowed (Standard RS) CHANNEL 2 CHANNEL 3 CHANNEL 4 CHANNEL 5 CHANNEL 6 CHANNEL 7 Details of the errors are printed on the journal. ERROR No. 1 2 3 4 5 How to exit the program Press the CANCEL key to exit the program. 6 7 8 9 10 11 Cin OFF OFF ON ON CDn OFF ON OFF ON CSn OFF ON OFF ON 14 15 16 17 13 12 ERROR print ER-DR : ERROR ER-CI : ERROR RS-CD : ERROR RS-CS : ERROR CI INT : ERROR CD INT : ERROR CS INT : ERROR TXEMP : ERROR TXEMP INT : ERROR TXRDY : ERROR TXRDY INT : ERROR RCVRDY : ERROR Details of ERROR ER-DR LOOP ERROR ER-CI LOOP ERROR RS-CD LOOP ERROR RS-CS LOOP ERROR No CI interrupt occurs. No CD interrupt occurs. No CD interrupt occurs. TXEMP is not set. TXEMP interrupt does not occur. TXRDY is not set. TXRDY interrupt does not occur. RCVRDY is not set. (Not possible to receive. TRQ- occurs during the implementation of check ii.) CHANNEL
4)-2. CH1 Check

Checking If any channel is not set, the error message (ERROR: CHx) appears. When the channel is set, the following checks are performed. i. Control signal check ERn OFF OFF ON ON RSn OFF ON OFF ON DRn OFF OFF ON ON
RCVRDY INT : ERROR RCVRDY interrupt does not occur. SD-RD : ERROR SD-RD : ERROR TIMER : ERROR TIMER INT : ERROR SD-RD LOOP ERROR (DATA ERROR) SD-RD LOOP ERROR (DATA ERROR) TIMER ERROR (After check ii is completed) TRQ1- interrupt does not occur.
The program performs the read checks of the above inputs and interrupt checks of CS, CI, and CD. During the read check, ER and RS are changed over in the above order, checking the logic of DR, CI, CD and CS. If the check result does not agree with the logic in the table, the error message appears. "ON" in the table means active low and "OFF" means active high. In the interrupt check, the CS, CI and CD interrupts are permitted one by one (The mask is canceled.). The error message appears if an interrupt does not occur when each signal is active or if an interrupt occurs when each signal is not active. Four cycles of the above check is performed. ii. Data transfer check As check data, loop back data transfer of 256 bytes of 00H - 0FFH is performed. The baud rate is 38400 bps.
How to exit the program Press the CANCEL key to exit the program.
4)-3. CH2 Check

Checking The procedure for checking, display and the method of exiting the programs are the same as for the CH1 check.
PATTERN 1 ER8 OFF ON ON RS8 ON OFF ON CI8 OFF OFF OFF CD8 OFF OFF OFF
4)-4. CH3 Check

Checking The procedure for checking, display and the method of exiting the program are the same as for the CH1 check.
"No Connect" is displayed on the next line of PASS!!. PATTERN 2 ER8 OFF ON ON RS8 ON OFF ON CI8 OFF ON ON CD8 OFF OFF OFF
4)-5. CH4 Check

Checking The procedure for checking, display and the method of exiting the program are the same as for the CH1 check.
4)-6. CH5 Check

Checking The procedure for checking, display and the mothod of exiting the programs are the same as for the CH1 check.
"CI Connect is displayed on the next line of PASS!! PATTERN 3 ER8 OFF ON ON RS8 ON OFF ON CI8 OFF OFF OFF CD8 OFF ON ON
4)-7. CH6 Check

4)-8. CH7 Check

4)-9. CH8 Check

For checking CH8, the following loop-back connectors are used.
RS ER SD GND RD DR CS 1pin 2pin 3pin 5pin 6pin 7pin 8pin
"CD Connect! is displayed on the next line of PASS!! If the logic is different from those in PATTERN 1 - 3, the error message appears. "ON" means active low and "OFF" active high. The above checks are repeated for four cycles. ii. Data transfer check As check data, loop back data transfer of 256 bytes of 00H - 0FFH is performed, the baud rate is set for115200 bps. Display
RS232 CH8 Check PASS!!(or ERROR!!) CD Connect(or CI Connect, No Connect)
CI/CD 4pin
Checking The following checks are performed. i. Control signal check ER8 OFF OFF ON ON RS8 OFF ON OFF ON DR8 OFF OFF ON ON Ci8 OFF CD8 OFF CS8 OFF ON OFF ON Details of the errors are printed on the journal. ERROR No. 1 2 3 4 5 6 7 8 9 10 11 TXEMP : ERROR TXEMP INT : ERROR TXRDY : ERROR TXRDY INT : ERROR TXEMP is not set. TXEMP interrupt does not occur. TXRDY is not set. TXRDY interrupt does not occur. ERROR print ER-DR : ERROR ER-CI : ERROR RS-CD : ERROR RS-CS : ERROR Details of ERROR ER-DR LOOP ERROR ER-CI LOOP ERROR RS-CD LOOP ERROR RS-CS LOOP ERROR
The program performs the read checks of the above inputs. During the read check, ER and RS are changed over in the above order, checking the logic of DR, CI, CD and CS. If the logic is different from those listed in the table, the error message appears.
ERROR No. 12
ii. Reverse-videoed test pattern of i ERROR print RCVRDY : ERROR Details of ERROR RCVRDY is not set. (Not possible to receive. TRQoccurs during the implementation of check ii.)
13 14 15
RCVRDY INT : ERROR RCVRDY interrupt does not occur. SD-RD : ERROR SD-RD : ERROR SD-RD LOOP ERROR (DATA ERROR) SD-RD LOOP ERROR (DATA ERROR, FRAMING ERROR, and others) iii. Vertical stripe pattern with 1-dot spacing
16 17 18 19 CI : ERROR CD : ERROR The logic of C1 is ON, but different from those in 1~3. The logic of CD is ON, but different from those in 1~3. iv. Reverse-videoed test pattern of iii
How to exit the program. Press the CANCEL key to exit the program.
5) LCD/POPUP/POLE DISPLAY & PRINTER DIAGNOSTICS

The program tests the LCD, popup and pole displays of the UP-700. The following menu appears on screen. The cursor shown in reverse video can be moved using the up/down arrow keys. Move the cursor to the menu item you want to execute and select by pressing the Enter key to execute the corresponding Diag. program. You can return the screen to this submenu by pressing the CANCEL key.
v. Horizontal stripe pattern with 1-dot spacing
DISPLAY&PRINTER DIAG LCD Check POPUP Check POLE Check PRINTER Check PRINTER CG Check PES&NES SENSOR Check A/D CONVERTER Check
The test program displays the following test patterns in the order shown below. You can move to the next pattern by pressing the ENTER key. You can return the screen to this submenu by pressing the ENTER key when the final test pattern is shown on the screen or by pressing the CANCEL key during the implementation of the check.
vi. Reserve-videoed test pattern of v
vii. The outermost periphery of LCDs active area is displayed in 1-dot line.
5)-1. Liquid Crystal Display Check

Checking The screen shows the following test patterns. Press the ENTER key to move to the next test pattern. i. Black and white checkered pattern with 1-dot spacing.
HHHHHHHHHHHHHHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHHHHHHHHHHH
viii. "H" pattern. "H" is displayed in 20 digits and 8 lines. "H" is displayed in 19 digits only in the 8th line.
How to exit the program. You can exit the program by pressing the ENTER key when the final test pattern is shown on the screen or by pressing the CANCEL key during checking.
5)-4. PRINTER Check

Checking The printer prints on the RECEIPT/JOURNAL PRINTER. Display
5)-2. Pole Display Check

Checking The screen shows the following test patterns in the order given below. Press the ENTER key to move to the next pattern. i. The following test patterns are displayed.
PRINTER Check
DOT DISPLAY 7SEG DISPLAY
: 0 1 2 3 4 5 6 7 8 9 ; A a B b C : 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. -.
ii. The test pattern where all digits are turned ON is displayed. Display
JOURNAL/RECEIPT print
UP-600/700 DIAGNOSTICS V1.0A
POLE Display Check
30 digits are printed 30 digits are printed 30 digits are printed 30 digits are printed 30 digits are printed
How to exit the program
Enlargement
Enlargement
How to exit the program. You can return to the Diag. submenu by pressing the ENTER key after the 2nd test pattern where all digits are turned ON and are displayed. Or press the CANCEL key to erase the screen to exit the program.
One second after printing is completed, the screen returns to the PRINTER Check of the DISPLAY & PRINTER MENU.
5)-5. PRINTER CG Check

Checking The printer prints the built-in CG onto the RECEIPT/JOURNAL PRINTER. For standard characters are printed in 16 characters/line and extended ASCII characters (enlarged characters) are printed in 8 characters/line. Standard characters are printed first, followed by the extended ASCII characters. Check the outputted print to see if CG is correctly printed.
5)-3. Popup Display Check

Checking The screen shows the following test patterns in the order given below. Press ENTER to move to the next pattern. i. The following test patterns are displayed.
7 SEG DISPLAY : 0 . 1 . 2 . 3 . 4 . 5 . 6 .
ii. The test pattern where all digits are turned ON is displayed. Display
Display
PRINTER CG Check
POPUP Display Check
How to exit the program. How to exit the program You can return to the Diag. submenu by pressing the ENTER key after the 2nd test pattern where all digits are turned ON and are displayed. Or press the CANCEL key to erase the screen to exit the program. Press the CANCEL key to exit the program after 1 cycle of printing is completed.
5)-6. PES & NES SENSOR Check

Checking The screen displays the operating status of the paper end sensor and paper near end sensor of the receipt/journal printer. Display
6) TCP/IP STACK NETWORK DIAGNOSTICS

The program performs the TCP/IP stack test. The test requirements are as follows:
PES&NES SENSOR Check NES : 0 (or 1) RPES : 0 (or 1) JPES : 0 (or 1) OPBS : 0 (or 1)
UP-700 10BASE-T cable (for data transfer testing) HUB (for loop back test and data transfer test where 2 or more
units are used.) The following menu appears. The cursor shown in reverse video can be moved using the up/down arrow keys. Move the cursor to the menu item you want to execute and press the ENTER key to execute the corresponding check program. After the selected Diag. program is completed, the screen returns to this menu. Press the CANCEL key to return the screen to the Diag. submenu.
TCP/IP&PRINTER DIAG
Display Status NES 0 1 RPES 0 1 JPES 0 1 OPBS 0 1 Description Senses the near end of the journal paper roll. Does not sense the near end of the journal paper roll. Senses the end of the receipt paper roll. Does not sense the end of the receipt paper roll. Senses the end of the journal paper roll. Does not sense the end of the journal paper roll. IPL ROM PWB not connected IPL ROM PWB connected The program executes Diags built in TCP/IP stack board and displays the results. i. Execute the flash memory test command and display the result. ii. Execute the SRAM test command and display the result. iii. Execute the dual-port RAM test and display the result. iv. Execute the interrupt test command and display the result. The information inside the error status is as follows: b7 b6
A/D CONVERTER Check TM=*** VRF=*** VP=***
SELF Check LOOPBACK Check MAC ADDR&FIRM Ver. Read MAC ADDR&FIRM WRITE DATA Trans.(MA) DATA Trans.(SA)
6)-1. SELF Check

Checking
5)-7. A/D Converter Check

Checking The digital values of signals inputted into the A/D converter of the CPU are displayed one by one. The data on the screen are updated at an interval of about 1 second by the timer. Screen
Reserved ("0" is always displayed) Reserved ( "0" is always displayed) Reserved ("0" is always displayed) Reserved ( "0" is always displayed) HR_RST : If /INTHR cannot be canceled HR_ACK:If /INTHR does not enter after waiting for 10 ms HW_RST : If /INTHW cannot be canceled Reserved ("0" is always displayed)
b5 b4 b3 b2 b1 b0
Display Note 1: VRF means a VRF estimated voltage calculated on the assumption that VCC is +5V. Note 2: In the *** section, 10-bit data of the A/D converter is indicated in hexadecimal numbers. The numbers are from "000" to "3FF". How to exit the program Press the CANCEL key to exit the program.
SELF Check FLASH : PASS (or ERROR) SRAM : PASS (or ERROR) XXXXXXXX : XX : XX DPRAM : PASS (or ERROR) XXXXXXXX : XX : XX INTERRUPT : PASS (or ERROR) XXXXXXXX
When an error occurs, the address and data are displayed. When an error occurs, the address and data are displayed. When an error occurs, the data is displayed.
6)-2. LOOPBACK Check

Checking Install a straight cable between the RJ45 connector and the HUB and execute the loop back test command to send and receive 1 packet of data. Display
Input : DUAL PORT RAM (800000H)
08 00 1F XX YY ZZ
MAC ADDRESS (XX, YY, ZZ are converted to 16 hexadecimal numbers.) Output : DUAL PORT RAM (800800H) During writing
LOOPBACK Check LOOPBACK : PASS (or ERROR) LOOPBACK ERROR LANC ERROR Displayed when an error occurs. Displayed when an error occurs.
P L
When writing is completed (The same applies when the copy is skipped at the first verification.)
P L
O K
When the writing process ends with an error. How to exit the program Press the CANCEL key to exit the program.
P L
N G
6)-3. MAC ADDRESS&FIRM Ver. read Check

Checking The program reads the version of the MAC address and firmware and displays the result. Display
Display
MAC ADDR&FIRM Write MAC ADDRESS AAA BBB CCC 08 00 1F XX YY ZZ TCP/IP FIRM CHANGE IPL 00-07
Data of 6 bytes is displayed.
TCP/IP FIRM CHANGE :
Decimal numbers are input through keyboard. Data of 6 bytes is displayed as hexadecimal numbers
MAC ADDR&FIRM Ver. Read MAC ADDRESS : XX XX XX XX XX XX FIRMWARE VERSION : XXXXXXXXXX
XX (XX : 00~07 OK or NG)
10 digits are displayed.
A B
ERASE COPY FIRM
00-07 00-05 CHANGE PASS!!
00 00
6)-4. MAC ADDRESS&FIRM write UTILITY

Operation This utility writes the MAC address and firmware. (Procedure) Install master ROM EPROM on the TCP/IP board and turn the IPL switch on the board to the "program write mode." Turn on the ECR. The IPL program on the TCP/IP board starts. Input 3 sets of 3-digit decimal numbers through the keyboard of the ECR and press the ENTER key. Following the SHARP maker code (08, 00, 1F), the 3 sets of numbers input through the keyboard are converted into hexadecimal numbers. The program then writes a total of 6 bytes of MAC address into dual port RAM (800000H - ). Turn off the power supply. Remove the EPROM from the TCP/IP board and turn the IPL switch to the "normal mode."
While the address and firmware are being rewritten, the message A and then B appears. When the address and firmware have been rewritten, the message C is displayed. The following screen appears when the IPL switch is not turned to the write mode.
MAC ADDR&FIRM Write CHANGE IPL SW!!
How to exit the program. Press the CANCEL key to exit the program. After rewriting, make sure to turn the power off and then turn it on again.
6)-5. Data Transmission Check

The program performs a data transfer test using an actual established system. The system consists of 1 master machine and up to 63 satellite machines. Caution to be taken when starting the test.
i. Setting the master machine. On the menu screen, select DATA Trans. (MA). The screen looks like this:
DATA Trans.(MA) INPUT MA T-NO. : Enter a number within a range from 1~64.
If this test is performed on the ECRs set for LAN, cancel the
settings before starting the test.
If this test is performed using an established system, disconnect

the LAN cables from the ECRs you do not want to test or cancel their LAN settings. If the test is performed with those ECRs set for LAN, their data might be destroyed.
After canceling the LAN settings of all ECRs on the system, set
them for data the transfer test. Set the satellite machines first, and then set the master machine.
Enter the terminal No. of the machine you want to test (a 2-digit number from 1 - 64)+ Enter. The screen looks like this:
DATA Trans.(MA) INPUT MA T-NO. : XX INPUT SA T-NO. : The terminal No. you entered is displayed.
The Diag of the UP-700 uses a private IP address. Each IP address is unique on the Internet. When building a private network, you should be careful not to allow your internal packet used for your own network to leak to the Internet, because it might cause confusion. The Internet Assigned Numbers Authority (IANA) specifies IP addresses that can be used without registration. These addresses can only be used within a private network and are not route controlled between sites of the Internet. Class A : 10.x.x.x Class B : 172.16.x.x 172.31.x.x Class C : 192.168.0.x?192.168.255.x It is strongly recommended to use addresses within the above range when building a private network. In this Diag. program, the following private IP addresses are assigned to the terminal Nos. (1 - 64). TERMINAL NO.1 = 192.168.0.1 TERMINAL NO.2 = 192.168.0.2 ...... TERMINAL NO.31 = 192.168.0.63 TERMINAL NO.32 = 192.168.0.64 Setting i. Setting satellite machines On the menu screen, select DATA Trans. (SA). The screen is shown below:
DATA Trans.(SA) INPUT SA T-NO. Enter a number within the range from 1 64.
Enter the terminal No. (a 2-digit number from 1 -64) of the satellite machines which are connected to the test machine + Enter. The screen looks like this:
DATA Trans.(MA) INPUT MA T-NO. : XX INPUT SA T-NO. : XX( or XXXX) The terminal No. of the master machine you entered is displayed. The terminal No. of the satellite machine you entered is displayed.
Enter the terminal No. of the machine you are going to test (a 2-digit number from 1 - 32) + Enter. The screen looks like this:
DATA Trans.(SA) INPUT SA T-NO. : XX DATA SEQ.NO. : 0000 The terminal No. you entered is displayed.
When performing the test with multiple satellite machines, type their terminal numbers (2-digit numbers within the range from 1~64) and press Enter. In addition, you specify the satellite machines using the area specification function without typing terminal numbers. This is achieved by typing the first terminal number (2 digits) and the last terminal number (2 digits) of the satellite machines and then press Enter. For example, if you want to specify the terminal numbers of satellite machines from 5 to 15, type "0515" for T-No. and press Enter. When executing, press the Enter key without typing the terminal numbers. The display appears like this: Note that the terminal numbers of the master machine and satellite machines should not be the same. When the terminal numbers are to be specified using the area specification function, any terminal number that is used for the master machine will be excluded from the specification of satellite machine terminal numbers.
INPUT MA T-NO. : XX
The terminal No. of the master machine you entered is displayed.
DATA SEQ.NO. : 0000
With the above setting, data transfer is performed between the master machine and the satellite machines.
Checking i. The master machine sends data of the following format consisting of 2-byte sequence No. and 254-byte AAH data to the satellite machine. The master machine displays the sequence Nos. Test data format (1 packet: 256 bytes)
7) MCR & DRAWER Diagnostics

The program checks the MCR and drawer. The following menu appears on screen. The cursor shown in reverse video can be moved using the up/down arrow keys. Move the cursor to the menu item you want to execute and select by pressing the ENTER key to execute the corresponding program. Press the CANCEL key to return the screen to this submenu.
1 XX
2 XX
3 AA
4 AA
5 AA
254 255 256 byte AA AA AA
XXXX : Sequence No. 2 bytes (4-digit binary coded decimal number) AA : Transfer (AAH) ~ 254 bytes
MCR&DRAWER Check MCR Check DRAWER 1 Check DRAWER 2 Check
ii. The satellite machine returns the data it has received, to the master machine as it is. The satellite machine displays the sequence No. on the screen. iii. The master machine receives the data and sequence Nos. and 254-byte AAH data. If an master machine displays an error code and there are multiple satellite machines, steps peated. then checks the error occurs, the ends the test. If i and ii are re-
7)-1. Magnetic Card Reader Check

The program performs the read test of an optional UP-E13MR. The test program reads a magnetic card using the ISO7811/1-5 standard and prints data on the journal. Press the CANCEL key to return the screen to the submenu.
The master machine advances the sequence No. when data is transferred successfully between it and the satellite machines. Steps i - iii are repeated. Error display
Checking
INPUT MA T-NO. : XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX
The terminal No. of the master machine you entered is displayed. After executing, all the terminal Nos. of the satellite machines are displayed. Up to 63 units.
The program reads tracks 1 - 3 of a magnetic card using the ISO7811/15 standard and prints the data with the ASCII codes. JOURNAL print
MCR Check TRACK1: XXXXXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXX TRACK2: XXXXXXXXXXXXXXXXXXXXXXXXXXX TRACK3: XXXXXXXXXXXXXXXXXXXXXXXXXXX
TCP/IP ERROR : XX
The error code appears on screen.
The following error codes are used (same as for TCP/IP HANDLER) 01 02 03 04 Command error (excluding the time when data is sent) No data received Received data size present Received data left Receiving station not ready for receiving (when sending) "NRDY" is returned because the receiving station is not ready for receiving. Receiving buffer full(when sending) The receiving sides controller receive buffer is full. Resend error(When sending) The number of retries exceeds the setting (5 times) when no response is obtained. Collision error (When sending) If a collision occurs Line busy time out Data cannot be sent due to multiple stations communicating Receiving data size over (when receiving) Insufficient size of receiving buffer. Hardware error Interface error (No SRN interface or defective SRN controller) Data read by the MCR is printed in the areas XXXXX. If an error occurs, the following error codes are displayed. Until the program is terminated, the error code is repeated, standing by for reading. Display
MCR Check TRACK1 : BUFFER EMPTY TRACK2 : MCR ERROR TRACK3 : PASS
05 06
Receive data is empty Data error after detecting card. Data has been read successfully.
07 08 09 0A
7)-2. Drawer 1 Check

Checking The program turns on the drawer 1 solenoid, senses the value of the drawer open sensor every 100 ms, and displays the operating status. Display
DRAWER 1 Check Open Sensor : OPEN (or CLOSE)
7)-3. Drawer 2 Check

Checking The program turns on the drawer 2 solenoid, senses the value of the drawer to open the sensor every 100ms, and displays the operating status. The procedure for displaying the menu and exiting the program are the same as for the drawer 1 check.
CHAPTER 6. CIRCUIT DESCRIPTION

1. HARDWARE BLOCK DIAGRAM
DRAWER x 2 RS232 x 2 CPU H8/510 FLASH ROM Max.2MB
UP-P16DP (POLE-DISP) Controller CKDC9
SYSTEM G/A (MPCA9)
S-RAM(STD) Max.512KB
S-RAM(STD) Max.4MB UP-S02MB: 2MB UP-S04MB: 4MB
Thermal PRN. (PR-58HM) MCR UNIT UP-E13MR
KEY/SW/POP Controller CKDC9
LCD UNIT
LCD Controller M66271
Optional CARD ER-A5RS
RS232 x 2
Ethernet Controller (TCP/IP stack)
10base-T
UP-E10IN
Symbol/PartsCod) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
2. DESCRIPTION OF MAIN LSIs

1) CPU (HD6415108FX)
1)-1. Pin description
112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85
84 83 82 81 80 78 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57
STBY MD2 MD1 MD0 VCC RFSH LWR HWR RD AS E X VSS XTAL EXTAL VSS TXD2 RXD2 TXD1 RXD1 SCK2/IRQ3 SCK1/IRQ2 IRQ1 IRQ0 VCC AVCC P73 P72
RES NMI VSS P10 P11 P12 P13 P14 P15 P16 P17 D8 D9 D10 D11 D12 D13 D14 D15 VSS A0 A1 A2 A3 A4 A5 A6 A7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
P71 P70 AVSS VSS P67 P66 P65 P64 P63 P62 P61 P60 P57 P56 P55 P54 P53 P52 P51 P50 VSS P47 P46 P45 P44 P43 P42 P41
A8 A9 A10 A11 A12 A13 A14 A15 VSS A16 A17 A18 A19 A20 A21 A22 A23 VSS P30/WAIT P31/BACK P32/BREQ P33 P34 P35 P36 P37 VCC P40
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
D15 D14 D13 D12 D11 D10 D9 D8
P17
P16
P15
P14
P13
P12
P11
P10
1)-2. Block diagram
P27/A23
Data bus Port 1
P26/A22 P25/A21
Port 2
P24/A20 P23/A19 P22/A18 P21/A17 P20/A16
Data bus (Lower)
EXTAL XTAL X E MD2 MD1 MD0 RES STBY NMI AS RD HWR Refresh controller Interruption controller H8/500 CPU DTC Clock oscillator Watch dog timer
Data bus (Upper)
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 P37 P36 P35
Address bus
Port 3
LWR RFSH
16bit free running timer x 2ch
Address bus
P34 P33 BREQ
VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS AVCC AVSS Port 8
Wait state controller
8bit timer
BACK WAIT P47
A/D convertor
Serial communication interface x 2ch
P46 P45
Port 4
P44 P43 P42 P41/TMCI P40
Port 7
Port 6
Port 5
TXD2
RXD2
TXD1
RXD1
IRQ1
IRQ0
P54
P53
P52
P51
SCK2/IRQ3
SCK1/IRQ2
P73
P72
P67 P66 P65 P64 P63 P62 P61 P60
P57
P56
P71
P70
P55
P50

Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Symbol /RES NMI VSS D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 VSS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 VSS A16 A17 A18 A19 A20 A21 A22 A23 VSS P30 P31 P32 P33 P34 P35 P36 P37 VCC P40 P41 P42 Signal name /RESET NMI GND D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 GND A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 GND A16 A17 A18 A19 A20 A21 A22 A23 GND /WAIT /BACK /BREQ DOPS /DR0 /DR1 NC NC VCC VCC GND GND In/ Out In In In I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O In Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out In Out Out Out Out Out Out Out Out In In Out In In Out Out NC NC In In In In Function Reset signal Non-maskable interrupt input for SSP interrupt input. GND Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus GND Address bus Address bus Address bus Address bus Address bus Address bus Address bus Address bus Address bus Address bus Address bus Address bus Address bus Address bus Address bus Address bus GND Address bus Address bus Address bus Address bus Address bus Address bus Address bus Address bus GND Wait signal Bus control request acknowledge signal Bus control request signal Drawer open signal Option drawer open signal Option drawer open signal NC NC +5V +5V GND GND Pin No. 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 Symbol P43 P44 P45 P46 P47 VSS P50 P51 P52 P53 P54 P55 P56 P57 P60 P61 P62 P63 P64 P65 P66 P67 VSS AVSS P70 P71 P72 P73 AVCC VCC /IRQ0 /IRQ1 /IRQ2 /IRQ3 RXD1 TXD1 RXD2 TXD2 VSS EXTAL XTAL VSS X E /AS RD /HWR /LWR /RFSH VCC MD0 MD1 MD2 /STBY Signal name GND MCRINT GND /SHEN GND GND NC /STOP /IPLON0 /IPLON1 GND NORDY FVPON BANK GND GND GND GND GND GND GND GND VCC VCC /IRQ0 /IRQ1 UASCK SCKI /RCVDT2 TXD2 RXDI TXDI GND EXTAL XTAL GND # NC /AS /RD /HWR /LWR /RFSH VCC IPLON0 IPLON0 /IPLON0 VCC In/ Out In In In In In In Out In In In In Out In Out In In In In Out Out In In In In In In In In In In In In In Out In Out In Out In In In In Out NC Out Out Out Out Out In In In In In Function GND MCR interrupt signal GND CKDC interface shift enable signal GND GND /DTR2 : Data Terminal Ready2 /DSR2 : Data Set Ready2 /CTS2 : Clear To Send2 /DCD2 : Carriar Detect2 NC /RTS2:Request To Send2 /CI2:Calling Indicator2 System reset output signal From IPL SW From IPL SW GND Flash Memory ready ("H" active) Flash Memory write protect ("L" active) For IPL ROM GND GND GND GND GND GND GND GND +5V +5V Interrupt signal 0 Interrupt signal 1 Synchronizing shift clock signal for USART CKDC interface synchronizing shift clock RXD signal for RS232 TXD signal for RS232 CKDC interface shift input data CKDC interface shift output data GND Crystal oscillator connection 19.6MHz Crystal oscillator connection 19.6MHz GND System clock NC Address strobe Read signal Write signal (HIGH) Write signal (LOW) Refresh cycle signal +5V From IPL SW From IPL SW From IPL SW +5V
2) G.A.(MPCA9)
2)-1. Pin configuration
GND GND ST3# DOT3 ST2# DOT2 ST1# DOT1 NC TTHR RTS3# DTR3# RXRDY3 TRXRDY3 TXD3 TXRDY3 TRXC3 RXD3 BUSY3# EXINT3# EXINT2# EXINT1# EXINT0# EXWAIT# DSF2# VWAIT# DSF1# DSCX# GND VDD OPTCS# IPLON RXC1 RXD1 DSR1# RXC2 RXD2 DSR2# RXC4 RXD4 DSR4# STH2 SCK2# HTS2 INT4# RTS5# DTR5# TXD5 RXD5 CTS5# DSR5# CI5# CD5# GND GND
156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
VDD ST4# DOT4 ST5# DOT5 GND ST6# DOT6 LATCH# DOT7 SO DOT8 GND CLOCK DOT9 SI DTCS WO LCDWT DTST# INHDEC CSEN# TTST2# TTST1# TIRQ# INH# RPE JPE PHUP PE PCRES PFP VHCOM GND VDD RVPON TRG# JVPON TRG CTBO PCUT# CTAO FCUT# RDS PRST# RCS PTMG# RBS RJMTD RAS RJMTS JDS STAMP# JCS VF# JBS RF# JAS JF# PTRM RJTMG PTJM TRGI POPI RJRST BA15 BA14 GND BA13 BA12 BA11 BA10 BA9 BA8 VDD
GND GND BA7 BA6 BA5 BA4 BA3 BA2 BA1 GND BA0 BWR# BRD# BRAS BRAS# BD7 BD6 BD5 GND BD4 BD3 GND BD2 BD1 BD0 GND VDD INT3# INT2# INT1# INT0# HTS1 SCK1# STH1 IPLON# RESET# UTST# USEL0 USEL1 USEL2 MCRINT WAIT# FROS1# RASPN1 RASPN2 EPROM1# DSEX# RXDH TXDH SCKH GND GND
VDD A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 GND VDD D7 D6 D5 GND D4 D3 GND D2 D1 D0 GND SSPRQ# IRQ1# IRQ0# WR# RD# AS# PHAI MD0 MD1 UASCK GND OSI1 OSO1 VDD
104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53
2)-2. Block diagram
A23~A0 D7~D0 /AS,/RD,/WR PHAI,/RESET
MPCA9 INT4#~INT0# MCRINT WAIT# FROS1#,EPROM1# RASPN1,2 DSEX# RXDH,TXDH,SCKH OSO1,OSI1 USACK MD1,MD2 IRQ0# SSPRQ# HTS2,SCK2,STH2 RXD4,RXC4,DSR4# RXD2,RXC2,DSR2# RXD1,RXC1,DSR1# IPLON OPTCS# VMEMC#,VIOC# DSF2# VWAIT#,EXWAIT# EXINT0#,EXINT1# EXINT2#,EXINT3# BUSY3#,RXD3,TXD3 TRXC3,TXRDY3 TRXRDY3,RXRDY3 DTR3#,RTS3# VRESC DTCS,DTST# LCDWT DBTST OPC IRQ1# TXD5,RXD5 DTR5#,RTS5# DSR5#,CTS5# CD5#,CI5# MPCA TPRC1 BA15~BA0 BD7~BD0 BWR#,BRD# BRAS,BRAS# ST1#~ST6# LATCH# SI,SO,CLOCK PHUP,VHCOM CSEN#,INH# TIRQ# RPE,JPE PCRES,PFP RVPON,JVPON CTBO,CTAO RAS,RBS,RCS,RDS JAS,JBS,JCS,JDS PTRM,PTJM POPI TTST1#,TTST2#
USEL2~USEL0, UTST#,

Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 47 48 49 50 51 52 53 54 Name GND GND BA7 BA6 BA5 BA4 BA3 BA2 BA1 GND BA0 BWR# BRD# BRAS BRAS# BD7 BD6 BD5 GND BD4 BD3 GND BD2 BD1 BD0 GND VDD INT3# INT2# INT1# INT0# HTS1 SCK1# STH1 IPLON# RESET# UTST# USEL0 USEL1 USEL2 MCRINT WAIT# FROS1# RASPN1 RASPN2 DSEX# RXDH TXDH SCKH GND GND VDD OSO1 IN/OUT O O O O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I I I I O O I I I I I I I O O O O O O O O I I O GND GND Address bus 7 for PB-RAM Address bus 6 for PB-RAM Address bus 5 for PB-RAM Address bus 4 for PB-RAM Address bus 3 for PB-RAM Address bus 2 for PB-RAM Address bus 1 for PB-RAM GND Address bus 0 for PB-RAM PB-RAM write strobe signal PB-RAM read strobe signal PB-RAM chip select : Active High (NU) PB-RAM chip select : Active Low Data Bus 7 for PB-RAM Data Bus 6 for PB-RAM Data Bus 5 for PB-RAM GND Data Bus 4 for PB-RAM Data Bus 3 for PB-RAM GND Data Bus 2 for PB-RAM Data Bus 1 for PB-RAM Data Bus 0 for PB-RAM GND +3.3V Interrupt signal 3 (NU) Shift enable for CKDC9 Keyboard request for CKDC9 Power off signal input 8 bit serial port output (for CKDC9) Serial port shift clock output (for CKDC9) 8 bit serial port input (for CKDC9) IPL switch 0 ON signal MPCA reset MPCA test pin (+3.3V) MPCA test pin (GND) MPCA test pin (GND) MPCA test pin (GND) MCR interrupt signal Wait request signal Flash ROM 1 chip select signal RAM 1 chip select signal RAM 2 chip select signal EP-ROM 1 chip select signal EP-ROM 2 chip select signal 8 bit serial port output to CPU 8 bit serial port input from CPU Serial port shift clock input from CPU GND GND +3.3V System clock (7.37MHz) Description Pin No. 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Name OSI1 GND UASCK MD1 MD0 PHAI AS# RD# WR# IRQ0# IRQ1# SSPRQ# GND D0 D1 D2 GND D3 D4 GND D5 D6 D7 VDD GND A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 VDD GND GND CD5# CI5# IN/OUT I O I I I I I I O O O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I I I I I I I I I I I I I I I I I I I I Description System clock (7.37MHz) GND USAT clock to CPU MPCA test pin (GND) MPCA test pin (GND) System clock (9.83MHz) Address strobe Read Strobe Write Strobe Interrupt request 0 to CPU Interrupt request 1 to CPU SSP interrupt request to CPU GND Data Bus 0 Data Bus 1 Data Bus 2 GND Data Bus 3 Data Bus 4 GND Data Bus 5 Data Bus 6 Data Bus 7 +3.3V GND Address bus 0 Address bus 1 Address bus 2 Address bus 3 Address bus 4 Address bus 5 Address bus 6 Address bus 7 Address bus 8 Address bus 9 Address bus 10 Address bus 11 Address bus 12 Address bus 13 Address bus 14 Address bus 15 Address bus 16 Address bus 17 Address bus 18 Address bus 19 Address bus 20 Address bus 21 Address bus 22 Address bus 23 +3.3V GND GND RS-232 ch1 CD signal RS-232 ch1 CI signal
46 EPROM1#
Pin No. 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 133 134 135 137 138 139 140 141 142 143 144 145 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162
Name DSR5# CTS5# RXD5 TXD5 DTR5# RTS5# INT4# HTS2 SCK2# STH2 DSR4# RXD4 RXC4 DSR2# RXD2 RXC2 DSR1# RXD1 RXC1 IPLON OPTCS# VDD GND VIOC# VWAIT# DSF2# EXINT0# EXINT1# EXINT2# EXINT3# BUSY3# RXD3 TRXC3 TXD3 TXRDY3 RXRDY3 DTR3# RTS3# DBTST VRESC ST1# ST2# ST3# GND GND VDD ST4# ST5# GND ST6# LATCH#
IN/OUT I I I O O O I O O I I I I I I I I I I O O O O I O I I I I I I I I O O O O O O I O O O O O O O O
Description RS-232 ch1 DSR signal RS-232 ch1 CTS signal RS-232 ch1 RXD signal RS-232 ch1 TXD signal RS-232 ch1 DTR signal RS-232 ch1 RTS signal Shift enable for option display 8 bit serial port output (for option display) Serial port shift clock output (for option display) 8 bit serial port input (for option display) MCR track 3 CLS signal MCR track 3 RDD signal MCR track 3 RCP signal MCR track 2 CLS signal MCR track 2 RDD signal MCR track 2 RCP signal MCR track 1 CLS signal MCR track 1 RDD signal MCR track 1 RCP signal IPL switch 0 ON signal to CPU Chip select base signal for expansion option +3.3V GND VRAM chip select signal LCDC chip select signal LCDC wait signal DPRAM chip select signal External wait signal External interrupt signal 0 External interrupt signal 1 External interrupt signal 2 External interrupt signal 3 Fiscal memory BUZY signal (NU) Fiscal memory RXD signal (NU) Fiscal memory CLOCK signal (NU) Fiscal memory TXD signal (NU) NU NU Fiscal memory READY signal (NU) Fiscal memory DTR signal (NU) Fiscal memory RTS signal (NU) MPCA test pin (GND) NU Thermal head drive strobe signal 1 Thermal head drive strobe signal 2 Thermal head drive strobe signal 3 GND GND +3.3V Thermal head drive strobe signal 4 Thermal head drive strobe signal 5 (NU) GND Thermal head drive strobe signal 6 (NU) Thermal head latch signal
Pin No. 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
Name SO GND CLOCK SI DTCS LCDWT DTST# INHDEC CSEN# TTST2# TTST1# TIRQ# INH# RPE JPE PHUP PCRES PFP VHCOM GND VDD RVPON JVPON CTBO CTAO RDS RCS RBS RAS JDS JCS JBS JAS PTRM PTJM POPI BA15 BA14 GND BA13 BA12 BA11 BA10 BA9 BA8 VDD
IN/OUT O O I O I I I I I I O I I I I I I I O O O O O O O O O O O O I I I O O O O O O O O -
Description Thermal head serial output data GND Thermal head clock signal Thermal head serial return data Printer control select signal (GND) Wait request signal to CPU (+3.3V) MPCA test pin (+3.3V) CSEN# enable signal (GND) TPRC chip select (GND) MPCA test pin (+3.3V) MPCA test pin (+3.3V) TPRC interrupt request Thermal head drive inhibit Receipt paper end signal Journal paper end signal Printer head up signal Auto cutter unit reset signal Auto cutter unit FP signal Head drive common power control GND +3.3V Receipt side paper feed pulse motor common power control signal Journal side paper feed pulse motor common power control signal (NU) Cutter motor control signal Cutter motor control signal Receipt side paper feed pulse motor drive signal, phase D Receipt side paper feed pulse motor drive signal, phase C Receipt side paper feed pulse motor drive signal, phase B Receipt side paper feed pulse motor drive signal, phase A Journal side paper feed pulse motor drive signal, phase D Journal side paper feed pulse motor drive signal, phase C Journal side paper feed pulse motor drive signal, phase B Journal side paper feed pulse motor drive signal, phase A Receipt motor connector sens signal Journal motor connector sense signal GND Address bus 15 for PB-RAM Address bus 14 for PB-RAM GND Address bus 13 for PB-RAM Address bus 12 for PB-RAM Address bus 11 for PB-RAM Address bus 10 for PB-RAM Address bus 9 for PB-RAM Address bus 8 for PB-RAM +3.3V
132 VMEMC#
136 EXWAIT#
146 TRXRDY3
3) CKDC9 (HD404728B02FS)
3)-1. General description
The CKDC9 is a 4-bit microcomputer developed for the UP-700 and provides functions to control the real-time clock, keys, and displays. The basic functions of the CKDC7 are shown below. Keys: The CKDC9 is capable of controlling a maximum of 256 momentary keys. (Sharp 2-key rollover control) Simultaneous scanning of key and switch (When a key is scanned, the state of a mode and clerk switch is also buffered. The host can scan the state of switch together with the key entry data at the same time the key is scanned.)
Pin No. 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Symbol DCS VCC SCK HTS STH SDISP BUZZ DSCK SRES DS0 SHEN IRQ KR0 KR1 KR2 KR3 RESET OSC2 OSC1 GND CL1 CL2 TEST G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 PO0 PO1 PO2 PO3 SA
Signal name DCS VCKDC SCK HTS STH GND BUZZ DSCK RESET DSO SHEN KRQ KR0 KR1 KR2 KR3 CKDCR OSC2 OSC1 GND CL1 CL2 VCKDC G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 NC NC NC NC NC SA
In/ Out In In Out Out Out Out Out In In In In In Out Out Out Out Out Out Out Out Out Out Out Out
Function Dot display controller chip select DCS +5V Clock signal Key data from host Key data to host GND Buzzer Dot display controller SCK Reset signal Dot display controller SO Shift enable signal Key request signal Key return signal Key return signal Key return signal Key return signal CKDC reset signal Clock Clock GND Time clock Time clock +5V Display digit signal Display digit signal Display digit signal Display digit signal Display digit signal Display digit signal Display digit signal Display digit signal Display digit signal Display digit signal Display digit signal NC NC NC NC NC Segment A
Switches: Mode switch with 14 positions maximum 8-bit clerk (cashier) switch 2-bit feed switch 1-bit receipt on/off switch 1-bit option switch 4-bit general-purpose switch (1-bit is used for keyboard select) Displays: 16-column dot display 12-column 7-segment display (column digit selectable) All column blink controlled for the dot and 7-segment display decimal point and indicators Programmable patterns for 7-segment display: Four patterns Internal driver for 7-segment display Single tone control Year, month, day of month, day of week, hour, minute Hour, minute
Buzzer: Clock: Alarm:
Interrupt request (event control): Detection of key input, switch position change, alarm issue, and counter overflow

Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Symbol SB SC SD SE SF SG P4 P0 P1 P2 P3 MODR CFSR KEX0 KEX1 RQ SKR0 ST0 ST1 ST2 ST3 POFF STOP DDIG Signal name SB SC SD SE SF SG AP NC NC DP ID VCC CFSR NC NC GND VCC ST0 ST1 ST2 ST3 POFF STOP VCC In/ Out Out Out Out Out Out Out Out Out Out In Out Out Out Out Out Out In In Function Segment B Segment C Segment D Segment E Segment F Segment G NC NC Decimal point Indicator +5V Clerk key, Feed key, Switch return signal NC NC GND +5V Key strobe signal Key strobe signal Key strobe signal Key strobe signal Power off signal STOP signal +5V
4) LCD CONTROLLER (M66271FB)

4)-1. Pin configration
BHE D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 VDD VDD VDD VDD VDD VDD VDD
MPUCLK OSC1 CP LP UD0 UD1 UD2 UD3 FLM RESET WAIT MCS RD LWR HWR IOCS
9 78 66 67 69 70 71 72 68 11 7 6 5 4 3 2
14 60 59 58 57 56 55 54 53 50 49 48 47 46 45 44 43 77 63 52 42 34 23 8
31 30 29 28 27 26 22 21 20 19 18 17 16 15 62 61
A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 M LCDENB
MPUSEL OSC2 N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
12 79 76 74 73 75 32 39 38 37 36 33 51 80 65 1 40 35 24 13 25 64 41 10
4)-2. Pin configration

Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 Name VSS IOCS# HWR# LWR# RD# MCS# WAIT# VDD MPUCLK VSS RESET# MPUSEL VSS BHE# A0 A1 A2 A3 A4 A5 A6 A7 VDD VSS VSS A8 A9 A10 A11 A12 A13 N.C N.C VDD VSS N.C N.C N.C N.C VSS VSS VDD D0 D1 D2 D3 D4 D5 D6 D7 VSS VDD D8 D9 GND GND +5V MPU data bus 0 MPU data bus 1 MPU data bus 2 MPU data bus 3 MPU data bus 4 MPU data bus 5 MPU data bus 6 MPU data bus 7 GND +5V MPU data bus 8 MPU data bus 9 +5V GND GND Chip select input for control register High write strobe input Low write strobe input Read strobe input Chip select input for VRAM WAIT output to MPU +5V MPU clock GND Reset input 8/16-bit selective input to MPU GND Bus high enable input MPU address bus 0 MPU address bus 1 MPU address bus 2 MPU address bus 3 MPU address bus 4 MPU address bus 5 MPU address bus 6 MPU address bus 7 +5V GND GND MPU address bus 8 MPU address bus 9 MPU address bus 10 MPU address bus 11 MPU address bus 12 MPU address bus 13 Description Pin No. 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Name D10 D11 D12 D13 D14 D15 LCDENB M VDD VSS VSS CP LP FLM UD0 UD1 UD2 UD3 N.C N.C N.C N.C VDD OSC1 OSC2 VSS +5V Oscillation input terminal Oscillation output terminal GND Description MPU data bus 10 MPU data bus 11 MPU data bus 12 MPU data bus 13 MPU data bus 14 MPU data bus 15 LCD (ON/OFF) control signal input LCD AC-conversion signal output +5V GND GND Display data transfer clock Display data clutch pulse FIRST LINE MARKER signal output LCD display data bus 0 LCD display data bus 1 LCD display data bus 2 LCD display data bus 3
3. ADDRESS MAP
1) TOTAL MEMORY SPACE
The address map of the total memory space is shown below. As you can see, the memory space is divided into the following 5 blocks: 0page area (including the I/O area)
2) 0PAGE AREA
The 0page area consists of four spaces: the ROM mapped area, internal and external I/O areas. The ROM mapped area has been devised for the following purposes: Simplifying the procedure for booting the IPL program Achieving high-speed accessing, and accessing by abbreviated instructions.
000000h
* The ROM area 200000h to 20FFFFh (ROS1 lower 64KB) is mapped on the ROMmapping area.
VRAM RAM ROM Extended I/O area

000000h
0 page area (64KB)
00FFFFh 200000h Flash (4MB)
* In the 0 page area, lower 64KB or less of the flash area is mapped. By mapping the ROM area, the reset start and other vectors become addressable.
ROM mapping area

* The internal I/O area is used for peripheral modules inside the CPU; the external I/O area is used for peripheral modules outside the CPU. For more information, refer to the H8/510 hardware manual and peripheral device specification.
00FE80h
600000h STD RAM (2MB) 800000h

00FF80h 00FFFFh
Internal I/O area I/O area External I/O area
3) I/O AREAS
EXTEND RAM (4MB) C00000h C20000h D00000h
VRAM (128KB)
* The expanded I/O area means the space for the I/O device addressed in the area excluding the 0 page one. MPCA8 uses FFFF00h to FFFFFFh for the addressed register (BAR) of SSP. The I/O register for VGAC is included.
The addresses from 00FF80h to 00FFFFh are called the internal I/O area. The internal I/O area is a space where the control registers and built-in ports inside the CPU are addressed. The external I/O area is a space where the peripheral devices outside the CPU or devices on an optional card are addressed.
00FE80h
EP-ROM (2MB) F00000h Extended I/O area FFFFFFh (1MB)
Internal I/O area
00FF80h
* MPCCS and expanded MPC signals are base signals for MPCA9 internal register decode. There is no external signal. * MCR1Z and MCR2Z are chip
MPCCS
00FFA0h Expanded MPC (not used) 00FFB0h 00FFB4h MCR2Z 00FFB8h T/PZ 00FFBCh MCR3Z 00FFC0h OPCCS1 00FFD0h OPCCS2 00FFE0h CPCSZ (not used) 00FFF0h TPRC1 00FFFFh MCR1Z
* MCR1Z, MCR2Z and MCR3Z are chip select signals for the magnet card reader. (Use lower 2bytes.)
* T/PZ is the internal decode signal for USART built in MPCA9. Thereis no external signal. (Use lower 2bytes.) * OPCCS1 and OPCCS2 signals are decoded inside the OPC (OPTION PERIPHERAL CONTROLLER) using the option decode signal OPTCS. There is no external signal.
OPTCSZ
* CPCSZ is CPC select for Centronics Interface. TPRC1 is built in by MPCA9.
4) ROM SPACE
Fig.5 shows the ROM space. The UP-700 uses 2MB of NOR-type flash memory instead of conventional ROM, so that the FROS1# from the MPCA9 is input into the chip enable of the flash memory.
1) BLOCK DIAGRAM
Here is the block diagram of the LCD and its allied components.
200000h
CPU H8/510 RD#
SD0-7 A0-13 RD# LWR# CLK
8bitMPU connection setting MPUSEL : "L" BHE# : "H" HWR# : "H"
* Lower 64KB of the ROS1 is mapped on the 0 page area.
HWR# PHAI WAIT#
ROS1 (MAX4MB)
* ROS1 is decoded by MPCA9.
UD0-3 WAIT# MPCA8 LCDWT VIO# VMEM# LP IOCS# MCS# M66271 M FLM DCLK
LD0-3 LCD (320 x 240) LP FP DCLK VEE BACKLIGHT
5FFFFF
BIAS POWER
5) VRAM & RAM SPACE

The VRAM is the display memory of the LCD.
600000h RASPN1 (2MB) 800000h
LCDENB
* All the decode signals in the area in the figure are supported by MPCA9. * RAS1 signals from MPCA9 correspond to 2MB 600000h to 7FFFFFh. * OPTION RAM board (2MB and 4MB) interfaces using RAS2 as the base signal.
2) LCD PANEL
The LCD panel uses a dot-matrix liquid crystal module with monochromatic STN and CCFT backlight. The resolution is 320 x 240.
3) DISPLAY CONTROLLER
Matsushita VGAC (M66271) is used for the display controller. VRAM is present on the address space of the CPU and it is possible to write and read data from the CPU side through the lower 9600 byte address of 128 KB size in addresses C00000H ~ C1FFFFH. C00000H - C1FFFH:
A00000h
RASPN2 (4MB)
4) LCD ON CONTROL
The LCD is turned on and off by controlling the bias power supply for the LCD using the terminal LCDENB of the M66271. LCDENB is in low level when resetting. When bit 0 of the mode resistor of the M66271 by software is set to high level, the power is supplied to the LCD, thus turning on the LCD.
C00000h VRAM (1MB) CFFFFFh
* The actual VRAM is 128KB, but it is accessed by every 128KB of bank according to VGAC specification.
5) BACK LIGHT CONTROL

The backlight ON/OFF is controlled by the same LCDENB used for controlling the LCD ON mode.
6) EXTENDED I/O AREA

The addresses from F00000h to FFFFFFh are called an extended I/O area. The UP-700 uses the following addresses as the break address register (BAR) for SSP.
6) LUMINANCE AND CONTRAST ADJUSTMENT Luminance: Luminance is adjusted with an inverter which controls
the dimming function. (Fixed)
FFFF00h FFFFFFh
Contrast:
Contrast is adjusted by controlling the contrast adjustment voltage (VO) of the LCD.
4. LCD DISPLAY
The UP-700 uses a 320 x 240 dot monochromatic LCD for the main display and VGAC (M66271) for the display controller which is connected to H8/510 in the ISA bus connection mode.
5. CUSTOMER DISPLAY
The UP-700 can incorporate a UP-P16DP for the customer display.
6. SRAM (Standard)
The device is HYUNDAI 4MB SRAM (HY628400ALLT2-70 512K 8bit) with an access time of 70ns.
1) CPU INTERFACE
The figure below shows a typical pseudo SRAM interface in the UP700.
S RAM(Standard) A0~A18 A0~A18 D0~D7 /RD /WR /RESET /CE S RAM(Option) RASPN1 RASPN2 A0~A21 D8~D15 /RD MPCA9 /HWR
8. SSP CONTROL
The UP-700 uses flash memory in the place of EPROM, so it is possible to rewrite the contents of the flash memory in changing the program. However, since the existing gate array MPCA8 is used, it is also possible to use the conventional SSP.
1) OPERATION
Like the MPCA5 ~ 8, the MPCA9 adopts the break address register comparison method for detecting addresses. The operation of this method is briefly explained below. The gate array always compares the break address register (BAR) built in the gate array, with the address bus to monitor the address bus. If both agree, the gate array outputs the NMI signal to the CPU, which in turn shifts from normal handling to exception handling. In both the MPCA5 ~ 8 and the MPCA9, SSP is achieved by the above operation. The setting of the break address register (BAR) is directly written in the addresses from FFFF00h to FFFFFFh.
A0~ A18
74LV138 A,B,C Y /G
A19~ A21
9. INTERRUPT CONTROL
There are roughly two types of interrupts:
Internal interrupts: Controlled inside the CPU 2) SRAM ADDRESS

Standard SRAM is decoded as follows by the RASPN1 signal. 780000h 7FFFFFh The base signal is 2MB. It thus wraparounds with 600000H 7FFFFFH 1.5MB.
External interrupts: Input into the CPU from outside 1) INTERNAL INTERRUPTS
Device interrupts built in the CPU are used for the following applications: Event factor SC11 SC12 FRT1 (ICI) (OCRA) (OCRB) (OVF) FRT2 (ICI) (OCRA) (OCRB) (OVF) TMR (CMA) (CMB) (OVF) WDT (OVF) A/D NMI Application Interrupt source as RS232 : CH8 Not used (SC1 is used for CKDC interface.) INTMCR MCR interrupt (to FT11 terminal)
7. NOR-type FLASH MEMORY

Here is the explanation for the interface of NOR-type flash memory. The device is Sharps LH28F016SU flash memory which consists of 512 K words 16 or 1 MB 8, with 32 blocks of 64 KB.
1) CPU INTERFACE
The figure below shows a typical interface for the LH28F016SU of the UP-700 system.
5V DATA ADDRES DQ0~DQ1 A0~A2 WE# OE#
FVPON NORDY
Standard SHEN event (for CKDC) Simple IRC timer event RS232 timer event System timer (53 ms)
VCC VPP
H8/510
HWRRDPORT64 PORT63
WP# RY/BY# RP#
LH28F 016SUT
Drawer open timer Not used SSP request
2) EXTERNAL INTERRUPTS
The following types of external interrupts are available: NMI (SSP) IRQ0 (Standard I/O interrupt) IRQ1 (RS232 interrupt) IRQ2 (Not Used) IRQ3 (Used as SCK terminal)
RESET-
MPCA8 FROS1-
CE0# CE1#
BYTE# 3/5# GND
2) DEVICE CONTROL
After resetting, the device automatically enters the array read mode and performs the same action as the usual ROM, thus requiring no special consideration when reading data. Data can be written at a high speed by using the page buffer.
10. WAIT CONTROL

The weight control function built in the MPCA9 is used to provide an interface with low-speed devices.
1) BLOCK DIAGRAM
The block diagram of the wait control function is shown.
CLK
WAIT RESET Counter
START
/AS /RESET for 1,2,3WAIT
WAIT enable For RASP-
D Selector /Q
WAIT enable For MISC
D Selector /Q
/RESET WAIT Count For
/RESET WAIT Count For
WAIT enable For VRAM VGA I/O
D /Q
D Selector /Q
/RESET for 1WAIT
/RESET WAIT Count For WAIT Count For
RASP
MISC
RASPN
RASPN
Terminal autoweight signal /EXWAIT /VWAIT /LCDWAIT /WAITZ
In the figure, the decoder, wait enabling register, AND-OR sections are the same as those in the MPCA6 or 7, but other components are newly incorporated in the MPCA5. EXWAITZ and WAITZ are external weight signals which are to be ORed inside the MPCA9 and output to the WAITZ. The EXWAITZ is a general-purpose wait request terminal, and WAITZ is the wait request signal from the VGA controller.
1) INTERFACE
The CKDC9 is connected through the MPCA8.
UP-P16DP MPCA8
HTS2 SCK2 STH2
H8/510
CKDC9
HTS SCK STH SHEN HTS SCK STH RESET
VFDC
VFD
11. CKDC9
The UP-700 uses one CKDC9 for the CKDC PWB and one CKDC9 for the POLE display (option) to carry out the following control operations. CKDC PWB CKDC9:
TXD2(P87) SCK2(P83) RXD2(P84) HTS SCK STH TXDI SCKI RXDI IRQ0
INT4 HTS1 SCK1 STH1 INT1 IRQ0 RES STOP (P57) FTI2 RESET RESET
reset from MAIN
Key
CKDC9
KRQ SHEN SRES STOP RESET SW Buzzer
Clock (second data readable) Buzzer System reset Key/Clerk switch
POLE DISPLAY PWB (UP-P16DP)
Customer display tube
12. OPTION RAM INTERFACE

1) INTERFACE
The expanded RAM connector terminals are shown in the table below. The 40-pin RAM is used for the connector. Extension RAM connector terminals Signal Name +5V HWR GND A20 A18 A16 A14 A12 A10 A8 A6 A4 A2 A0 D7 D5 D3 D1 RASPN2 GND Pin No. 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 Pin No. 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 Signal Name N.C. N.C. A21 A19 A17 A15 A13 A11 A9 A7 A5 A3 A1 RD D6 D4 D2 D0 VCKDC GND
1) POWER ON/OFF
The flow of signal processing at the time of the power supply turning On/Off is as follows: <Power OFF> Power supply 1 2 3 4 <Power ON> Power supply 1 2 3 POFF H STOP H RESET H (System reset) Table 20 MPCA9 CPU CKDC9 POFF L IRQ0 L STOP L RESET L (System reset) Table 19 MPCA9 CPU CKDC9
The table below shows the timing chart.

Power supply On +5V,+12V PG GOOD (POFF) RESET (System) STOP SHEN Power supply Off
10ms MIN
13. RESET SEQUENCE

SCK
The reset sequence block diagram is shown below. Note that the RESET signal (system reset) and CKDCR signal (CKDC reset) are different from each other.
8 PULSE
14. DRAWER
VCC SLIDE SW
The UP-700 can use up to 2 optional external drawers.

CKDCR (CKDC reset)
1) DRAWER SOLENOID DRIVE

P34 P37 inside the CPU are allocated for the port output of the drawer solenoid drive. Built-in port Signal name DR0 DR1 DR2 DR3 Remarks Drawer 1 (optional drawer) Drawer 2 (optional drawer) Reserved Reserved
STOP
CKDC9
POFF
P34
POFF
P35 P36 P37
CPU RESET (System reset)
POWER SUPPLY
One port corresponds to one drawer. If a power failure is detected, the drawer solenoid drive must be stopped as soon as possible. The drawer solenoid drive time must be controlled in the range of 40 ms to 50 ms by the timer.
MPCA9 IRQ0 INT0
2) DRAWER OPEN/CLOSE SENSE

The drawer open/close sense signal is input into the built-in port of the CPU. The sense signal of an optional drawer sensor is also wired ORed before inputting.
P33=1: Any of the drawers is open.
15. TCP/IP STACK

The LAN of the UP-700 uses as the protocol Ethernet, which supports TCP/IP. The interface with the TCP/IP board is achieved through 2 interrupt signals and dual-port RAM. The decode of dual-port RAM is located in the following space: DP-RAM: F20000H - F2FFFFH (max. 64 KB) The interruption from the TCP/IP is allocated as follows: EXINTO: INTSW (SLAVE WRITE interrupt) bit 6 of 00FF81H EXINT1: INTSR (SLAVE READ interrupt) bit 0 of 00FF80H <TCP/IP connector terminals> Signal Name +5V +5V A14 A12 HWR A10 A0 A2 A4 A6 A8 D7 D5 D3 D1 LRES INTSW GND GND Pin No. 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 Pin No. 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 Signal Name +5V +5V A15 A13 DPCS A11 RD A1 A3 A5 A7 A9 D6 D4 D2 D0 INTSR GND GND
17. MCR
This paragraph describes the MCR option (UP-E13MR) control defined by the UP-700 hardware architecture. 3 channels of the serial port (interchangeable with 8251) built in the MPCA9 are used. 3 tracks of data are read simultaneously. (UPE13MR)
1) CPU INTERFACE
The CPU interface for the USART (8251) and magnetic card reader (MCM-21) in the UP-700 system is shown below.
8251 x 2
RCVCLK1 RCP1 RCP1 RDD1 RCP2 RDD2 CLS1 CLS2 RCP3 RDD3 CLS3
Integrated as MPCA8 in the UP-700 system. CPU MPCA7

RCVRDY1 INTMCR ICI INTMCR RCVRDY2 CLS1, CLS2 /DSR2
RCVDT1 RCVCLK2 RCVDT2 /DSR1 CLS2 RCVCLK3 RCVRDY1 RCVDT3 /DSR3 RCVRDY2 RCVRDY3
SYNC
Signal description RCP1 RDD1 RCP2 RDD2 RCP3 RCD3 CLS1 CLS2 CLS3 RCVRDY1 RCVRDY2 RCVRDY3 INTMCR TRACK 1 CLOCK PULSE TRACK 1 DATA SIGNAL TRACK 2 CLOCK PULSE TRACK 2 DATA SIGNAL TRACK 3 CLOCK PULSE TRACK 3 DATA SIGNAL TRACK 1 CARD DETECTION SIGNAL TRACK 2 CARD DETECTION SIGNAL TRACK 3 CARD DETECTION SIGNAL TRACK 1 DATA RECEIVING SIGNAL TRACK 2 DATA RECEIVING SIGNAL TRACK 3 DATA RECEIVING SIGNAL INTERRUPT SIGNAL OR-SYNTHESIZED from RCVRDY and SYNC input
16. RS232
Two standard RS232 channels are compatible with the ER-A5RS. However, while the ER-A5RS uses the IRQ2 terminal of the CPU for interruption of the RS232, the UP-700 cannot use the IRQ1 terminal instead of it. (The IRQ2 terminal is used for IR as the SCK1 terminal.) The standard RS232 is fixed to the logic channels 1 and 8. Use the channels 2, 3, 4, 5, 6 and 7 for the ER-A5RS.
2 chip select signals for the 8251 are generated inside MPCA8.
2) MCR INTERFACE
The operating timing of the MCR interface signals is given below. (1) Example of timing
CLS1/CLS2 CLS3 RCP1/RCP2 RCP3 RDD1/RDD2 RDD3
(2) Detailed timing (relation between DATA and CLOCK PULSE)

RCP1/RCP2 RCP3 RDD1/RDD2 RDD3
"0"
"1"
"1"
Approx. 16 s
Min. 5 s
The "NULL" CODE is basically written prior to the opening code. The opening code detection algorithm is considered because data may become corrupt before and after the CARD detection signal due to a worn magnet stripe.
CHAPTER 7. TCP/IP I/F PWB DESCRIPTION

1. GENERAL DESCRIPTION
This control board is an Ethernet board that supports the TCP/IP protocol.
3. CONFIGURATION
CPU : [HitachiSH-2 Series SH7014 (20MHz)]
As external memory spaces, CS0 - CS3 and DRAM space are provided. This board assigns FLASH Memory to CS0, SRAM to CS1, dual-port SRAM to CS2, and LAN controller to CS3.
2. BLOCK DIAGRAM
10MHz /CS0 CPU (SH-2) /CS1 /CS2 /CS3 /HWACK /HRACK /SWRQ /SRRQ LA0~LA18
Address Bus Data Bus
LAN Controller : [RealtekRTL8019AS(20MHz)]

LAN controller is assigned to CS space. Because of pseudo ISA connection, each register is assigned to addresses of H00C00300 and after.
/CS1
CN
/INTSR /INTSW
LOGIC
/INTHR /INTHW
ROM(FLASH Memory) : [SharpLH28F004BVT(4Mbits)]<Access Time = 90ns>

ROM (FLASH Memory) is assigned to CS0 space. Data is written onto FLASH Memory from UV-EPROM by switching the CSO space to UV-EPROM and the CS3 space to FALSH Memory. MAC Address is written on FLASH Memory.
LD0~LD7 SRAM 128k byte
/DPCS, /WR,/RD Address Bus
/CS2
/CS0
Dual-Port RAM 4k byte
LD0~LD7
LD0~LD7 FLASH 512k byte
Company code is assigned to "08001FH". The serial number and adjustment byte are stored in an area of 4
bytes from the address H0007C000. <The serial number is acquired according to Sharps in-house specification(SS).>
Data Bus
LA0~LA11
LA0~LA18
RAM : [S-RAM 1Mbits]<Access Time=70ns>

/CS3 /CS0
Assigned to CS1 space.
LD0~LD7 RJ-45 LAN Cnt. (8bit-Bus) LA0~LA19
LD0~LD7
LA0~LA18
EP-ROM (Writing in to FLASH) 512k byte
[IDT Dual-Port SRAM IDT7134]<Access Time=55ns>

Assigned to CS2 space. The IDT7134 does not have any LOGICiBusy or Semaphorej, access to the same address from both sides is inhibited.
Pulse Trans : [Pulse78Z034]

When writing data into FLASH, switch /CS0to EP-ROM and /CS3 to FLASH Memory. It is used for the 10Base-T standard and has a choke coil built in at the output side.
Symbol/PartsCod) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
4. MAIN LSI DESCRIPTION

1) CPU (SH7014)
1)-1. SH7014 Overview
The SH7014 CMOS single-chip microprocessors integrate a Hitachioriginal architecture, high-speed CPU with peripheral functions required for system configuration. The CPU has a RISC-type instruction set. Most instructions can be executed in one clock cycle, which greatly improves instruction execution speed. In addition, the 32-bit internal-bus architecture enhances data processing power. With this CPU, it has become possible to assemble low cost, high performance/high-functioning systems, even for applications that were previously impossible with microprocessors, such as real-time control, which demands high speeds. In particular, the SH7040 series has a 1-kbyte on-chip cache, which allows an improvement in CPU performance during external memory access. In addition, this LSI includes on-chip peripheral functions necessary for system configuration, such as large-capacity ROM (except the SH7014, which is ROMless) and RAM, timers, a serial communication interface (SCI), an A/D converter, an interrupt controller, and I/O ports. Memory or peripheral LSIs can be connected efficiently with an external memory access support function. This greatly reduces system cost.
Cache Memory:
1-kbyte instruction cache Caching of instruction codes and PC relative read data 4-byte line length (1 longword: 2 instruction lengths) 256 entry cache tags Direct map method On-chip RAM, and on-chip I/O areas not objects of cache Used in common with on-chip RAM; 2 kbytes of on-chip RAM used as address array/data array when cache is enabled
Interrupt Controller (INTC):
Seven external interrupt pins (NMI, IRQ x 6) Twenty-eight internal interrupt sources Sixteen programmable priority levels
Bus State Controller (BSC):
Supports external extended memory access

8-bit, or 16-bit external data bus
Memory address space divided into five areas (four areas of

SRAM space, one area of DRAM space) with the following settable features: Number of wait cycles Outputs chip-select signals for each area During DRAM space access:
1)-1-1. SH7014 Features

CPU:
Original Hitachi architecture 32-bit internal data bus General-register machine

Sixteen 32-bit general registers Three 32-bit control registers Four 32-bit system registers
Outputs RAS and CAS signals for DRAM Can generate a RAS precharge time assurance Tp cycle DRAM burst access function
Supports high-speed access mode for DRAM
RISC-type instruction set

Instruction length: 16-bit fixed length for improved code efficiency Load-store architecture (basic operations are executed between registers) Delayed branch instructions reduce pipeline disruption during branch Instruction set based on C language
DRAM refresh function

Programmable refresh interval Supports CAS-before-RAS refresh and self-refresh modes
Wait cycles can be inserted using an external WAIT signal Address data multiplex I/O devices can be accessed
Note: No bus release
Direct Memory Access Controller (DMAC) (2 Channels):
Instruction execution time: one instruction/cycle (35 ns/instruction

at 28.7-MHz operation)
Address space: Architecture supports 4 Gbytes On-chip multiplier: multiplication operations (32 bits x 32 bits Five-stage pipeline
64 bits) and multiplication/accumulation operations (32 bits x 32 bits + 64 bits 64 bits) executed in two to four cycles
Supports cycle-steal and burst transfers Supports single address mode and dual address mode transfers Priority order: fixed at channel 0 > channel 1 Transfer counter: 16 bits Transfer request sources: external DREQ input, auto-request, and on-chip supporting modules
Address space: 4 Gbytes Choice of 8-, 16-, or 32-bit transfer data size
Multifunction Timer/Pulse Unit (MTU) (3 Channels):
Maximum 8 types of waveform output or maximum 16 types of

pulse I/O processing possible based on 16-bit timer, 3 channels
8 dual-use output compare/input capture registers 8 independent comparators 8 types of counter input clock Input capture function Pulse output mode One shot, toggle, PWM
Phase calculation mode

2-phase encoder calculation processing
1)-2. Block Diagram

Figure 1. is a block diagram of the SH7014.
PA6/TCLKA/CS2 PA5/SCK1/DREQ1/IRQ1 PA4/TXD1 PA3/RXD1 PA2/SCK0/DREQ0/IRQ0 PA1/TXD0 PA0/RXD0
Compare Match Timer (CMT) (Two Channels):

CS0 PA9/TCLKD/IRQ3 PA8/TCLKC/IRQ2 PA7/TCLKB/CS3
PB9/IRQ7/A21 PB8/IRQ6/A20/WAIT PB7/A19 PB6/A18
PB5/IRQ3/RDWR PB4/IRQ2/CASH PB3/IRQ1/CASL PB2/IRQ0/RAS
PA15/CK
RD WRH WRL CS1
Watchdog Timer (WDT) (One Channel):
Watchdog timer or interval timer Count overflow can generate an internal reset, external signal, or
interrupt
RES WDTOVR MD3 MD2 MD1 MD0 NMI EXTAL XTAL PLLVCC PLLCAP PLLVSS VCC A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 Direct memory access controller Interrupt controller Bus state controller A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3
PE2/TIOC0C/DREQ1 PE1/TIOC0B/DRAK0 PE0/TIOC0A/DREQ0
Serial Communication Interface (SCI) (Two Channels): (Per Channel):
RAM (3 kB)/ cache (1 kB)
Asynchronous or clock-synchronous mode is selectable Can transmit and receive simultaneously (full duplex) On-chip dedicated baud rate generator Multiprocessor communication function
PLL
VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS AVCC AVSS
CPU
I/O Ports:
SH7014
Input/output: 35 Input: 8 Total: 43
Serial communication interface ( 2 channels)
Multifunction timer/ pulse unit
Compare match timer ( 2 channels)
A/D converter
Watchdog timer
A/D Converter:
PE15/DACK1 PE14/DACK0/AH PE13 PE12 PE11
PE10 PE9 PE8 PE7/TIOC2B
PF7/AN7 PF6/AN6
PF5/AN5 PF4/AN4
PF3/AN3 PF2/AN2
PF1/AN1 PF0/AN0
PE6/TIOC2A PE5/TIOC1B PE4/TIOC1A PE3/TIOC0D/DRAK1
10 bits 8 channels The SH7014 has a high-speed A/D converter.

On-Chip Memory:
A17 A16
16-bit free-running counter One compare register Generates an interrupt request upon compare match
D2 D1 D0
ROM
SH7014: ROMless
: Peripheral address bus : Peripheral data bus : Internal address bus : Internal upper data bus : Internal lower data bus
RAM: SH7014: 3 kbytes (1 kbyte when cache is used)

Operating Modes:
Figure 1. Block Diagram of the SH7014
Operating modes
Non-extended ROM mode
1)-3. Pin Arrangement and Pin Functions 1)-3-1. Pin Arrangment

Figure 2. shows the pin arrangement for the SH7014 (top view).
RES PA15/CK PLLVSS PLLCAP PLLVCC MD0 MD1 VCC NMI MD2 EXTAL MD3 XTAL VSS D0 D1 D2 D3 D4 VCC D5 D6 D7 VSS D8 D9 D10 D11
PE0/TIOC0A/DREQ0 PE1/TIOC0B/DRAK0 PE2/TIOC0C/DREQ1 PE3/TIOC0D/DRAK1 PE4/TIOC1A VSS PF0/AN0 PF1/AN1 PF2/AN2 PF3/AN3 PF4/AN4 PF5/AN5 AVSS PF6/AN6 PF7/AN7 AVCC VSS PE5/TIOC1B VCC PE6/TIOC2A PE7/TIOC2B PE8 PE9 PE10 VSS PE11 PE12 PB13 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112
Processing states
Program execution state Exception processing state
Power-down modes
Sleep mode Software standby mode
84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57
Clock Pulse Generator (CPG):
On-chip clock pulse generator

On-chip clock-doubling PLL circuit
QFP-112
Figure 2. SH7014 Pin Arrangement (QFP-112 Top View)
PE14/DACK0/AH PE15/DACK1 VSS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 VCC A17 VSS PB2/IRQ0/RAS PB3/IRQ1/CASL PB4/IRQ2/CASH VSS PB5/IRQ3/RDWR
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
D12 VSS D13 D14 D15 PA0/RXD0 PA1/TXD0 PA2/SCK0/DREQ0/IRQ0 PA3/RXD1 PA4/TXD1 PA5/SCK1/DREQ1/IRQ1 PA6/TCLKA/CS2 PA7/TCLKB/CS3 PA8/TCLKC/IRQ2 PA9/TCLKD/IRQ3 CS0 CS1 VSS WRL VCC WRH WDTOVF RD VSS PB9/IRQ7/A21 PB8/IRQ6/A20/WAIT PB7/A19 PB6/A18
CPU
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 CPU PE14 PE15 Vss A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 Vcc A17 Vss /IRQ0 /IRQ1 /IRQ2 Vss /IRQ3 A18 A19 /WAIT PB9 Vss /RD /WDTOVF /WRH Vcc /WRL Vss /CS1 /CS0 PA9 PA8 /CS3 /CS2 PA5 PA4 PA3 PA2 PA1 PA0 D15 D14 D13 Vss D12 D11 D10 D9 D8 Signal name PE14 /WP GND LA0 LA1 LA2 LA3 LA4 LA5 LA6 LA7 LA8 LA9 LA10 LA11 LA12 LA13 LA14 LA15 LA16 +5V LA17 GND /INTHW /INTHR /INTLAN GND /IRQ3 LA18 LA19 IOCHRDY PB9 GND /MRD /WDTOVF /WRH +5V /MWE GND /CS1 /CS0 PA9 PA8 /CS3 /CS2 PA5 PA4 PA3 PA2 PA1 PA0 HD15 HD14 HD13 GND HD12 HD11 HD10 HD9 HD8 I/O I I O O O O O O O O O O O O O O O O O O I I I I O O I I O O O O O O I I O O I I I I I I I/O I/O I/O I/O I/O I/O I/O I/O Remarks N.U. (GND) FLASH write Status Address Bus No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 CPU Vss D7 D6 D5 Vcc D4 D3 D2 D1 D0 Vss XTAL MD3 EXTAL MD2 NMI Vcc MD1 MD0 PLLVcc PLLCAP PLLVss PA15 /RES PE0 PE1 PE2 PE3 PE4 Vss PF0 PF1 PF2 PF3 PF4 PF5 AVss PF6 PF7 AVcc Vss PE5 Vcc PE6 PE7 PE8 PE9 PE10 Vss PE11 PE12 PE13 Signal name GND HD7 HD6 HD5 +5V HD4 HD3 HD2 HD1 HD0 GND XTAL MD3 EXTAL MD2 NMI +5V MD1 MD0 PLLVcc PLLCAP PLLVss PA15 /LRES PE0 PE1 PE2 PE3 PE4 GND PF0 PF1 PF2 PF3 PF4 PF5 GND PF6 PF7 +5V GND PE5 +5V PE6 PE7 /SRRQ /SWRQ /HRACK GND /HWACK PE12 /RSTDRV I/O Remarks
I/O I/O I/O I/O I/O I/O I/O I/O O I I I I I I
DATA Bus
DATA Bus
Oscillator connection terminal Mode terminal Oscillator connection terminal Mode terminal 2 N.U. (+5V) Mode terminal 1 Mode terminal 0
Address Bus Host write end interrupt Host write end interrupt Interrupt from LANC N.U. (+5V) Address Bus Address Bus Wait from LANC N.U. (GND) Memory Read N.U. (OPEN) N.U. (OPEN) Memory Write SRAM Chip Select FLASH Chip Select N.U. (GND) N.U. (GND) LANC Chip Select DP-RAM Chip Select N.U. (GND) N.U. (GND) N.U. (GND) N.U. (GND) N.U. (GND) N.U. (GND) N.U. (Pull-Down) N.U. (Pull-Down) N.U. (Pull-Down) N.U. (Pull-Down) N.U. (Pull-Down) N.U. (Pull-Down) N.U. (Pull-Down) N.U. (Pull-Down)
I I I I I I I I I I I I I I I
N.U.(Pull-Down) Hardware Reset N.U. (GND) N.U. (GND) N.U. (GND) N.U. (GND) N.U. (GND) N.U. (GND) N.U. (GND) N.U. (GND) N.U. (GND) N.U. (GND) N.U. (GND) N.U. (GND) N.U. (GND)
I I I O O O O O O
N.U. (GND) N.U. (GND) N.U. (GND) Slave read end request Slave write end request Host read interrupt cancel Host write interrupt cancel N.U. (OPEN) Soft Reset for LANC
Note: Signals prefixed with a slash "/" are active in low level.
2) LAN CONTROLLER (RTL8019AS)

2)-1. Features:
2)-3. Pin Configuration
100-pin PQFP Supports PnP auto detect mode Compliant to Ethernet II and IEEE802.3 10Base5, 10Base2,
10BaseT
Software compatible with NE2000 on both 8 and 16-bit slots Supports both jumper and jumperless modes Supports Microsofts Plug and Play configuration for jumperless
mode
66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
BA21 [PNP] BA20 [BS0] BA19 [BS1] BA18 [BS2] VDD BA17 [BS3] BA16 [BS4] BA15 BA14 [PL0] BCSB EECS BD7 [PL1][EEDO] BD6 [IRQS0][EEDI] BD5 [IRQS1][EESK] BD4 [IRQS2]
65 64 63 62 61
JP AUI LED2 [LED_TX] LED1 [LED_RX] [LED_CRS] LED0 [LED_COL] [LED_LINK] 60 LEDBNC 59 TPIN+ 58 TPIN57 VDD 56 RX+ 55 RX54 CD+ 53 CD52 GND 51 X2
Supports Full-Duplex Ethernet function to double channel bandwidth
81 BD3 [IOS0] 82 BD2 [IOS1] 83 GND 84 BD1 [IOS2] 85 BD0 [IOS3] 86 GND 87 SD15 88 SD14 89 VDD 90 SD13 91 SD12 92 SD11 93 SD10 94 SD9 95 SD8 96 IOCS16B [SLOT16] 97 INT7 [IRQ15] 98 INT6 [IRQ12] 99 INT5 [IRQ11] 100 INT4 [IRQ10]
Supports three level power down modes:

Sleep Power down with internal clock running Power down with internal clock halted
RTL8019AS
Built-in data prefetch function to improve performance Supports UTP, AUI & BNC auto-detect Supports auto polarity correction for 10BaseT Supports 8 IRQ lines Supports 16 I/O base address options --- and extra I/O address fully decode mode
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
X1 TX+ TXVDD TPOUTTPOUT+ GND SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 IOCHRDY AEN RSTDRV SMEMWB SMEMRB
Supports 16K, 32K, 64K and 16K-page mode access to BROM (up
to 256 pages with 16K bytes/page)
Supports BROM disable command to release memory after remote

boot
1 INT3 [IRQ5] 2 INT2 [IRQ4] 3 INT1 [IRQ3] 4 INT0 [IRQ2/9] 5 SA0 6 VDD 7 SA1 8 SA2 9 SA3 10 SA4 11 SA5 12 SA6 13 SA7 14 GND 15 SA8
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IOWB IORB GND SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 VDD SA9
Supports flash memory read/write 16k byte SRAM built in Uses a 9346 (64*16-bit EEPROM) to store resource configurations
and ID parameters
LAN Controller
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 CPU INT3 INT2 INT1 INT0 SA0 VDD SA1 SA2 SA3 SA4 SA5 SA6 SA7 GND SA8 SA9 VDD SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 GND IORB Signal name INT3 INT2 INT1 /INTLAN LA0 +5V LA1 LA2 LA3 LA4 LA5 LA6 LA7 GND LA8 LA9 +5V LA10 LA11 LA12 LA13 LA14 LA15 LA16 LA17 LA18 LA19 GND /MRD I/O O O O O I I I I I I I I I I I I I I I I I I I I I Remarks N.U. (Pull-Down) N.U. (Pull-Down) N.U. (Pull-Down) Interrupt to CPU Address Bus Address Bus
Capable of programming blank 9346 on board for manufacturing

convenience
Support 4 diagnostic LED pins with programmable outputs 2)-2. General Description
The RTL8019AS is a highly integrated Ethernet Controller which offers a simple solution to implement a Plug and Play NE2000 compatible adapter with full-duplex and power down features. With the three level power down control features, the RTL8019AS is made to be an ideal choice of the network device for a GREEN PC system. The full-duplex function enables simultaneously transmission and reception on the twisted-pair link to a full-duplex Ethernet switching hub. This feature not only increases the channel bandwidth from 10 to 20 Mbps but also avoids the performance degrading problem due to the channel contention characteristics of the Ethernet CSMA/CD protocol. The RTL8019AS provides the auto-detect capability between the integrated 10BaseT transceiver, BNC and AUI interface. Besides, the 10BaseT transceiver can automatically correct the polarity error on its receiving pair. The RTL8019AS is built in with 16K-byte SRAM in a single chip. It is designed not only to provide more friendly functions but also to save the effort of SRAM sourcing and inventory.
Address Bus
Address Bus
Memory Read
No. 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92
CPU IOWB SMEMRB SMEMWB RSTDRV AEN IOCHRDY SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 GND TPOUT+ TPOUTVDD TXTX+ X1 X2 GND CDCD+ RXRX+ VDD TPNTPN+ LEDBNC LED0 LED1 LED2 AUI JP PNP BS0 BS1 BS2 VDD BS3 BS4 BA15 PL0 BCSB EECS PL1 IRQS0 IRQS1 IRQS2 IOS0 IOS1 GND IOS2 IOS3 GND SD15 SD14 VDD SD13 SD12 SD11
Signal name /MWE SMEMRB SMEMWB RSTDRV /CS3 /WAIT LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 GND TPOUT+ TPOUT+5V TXTX+ X1 X2 GND CDCD+ RXRX+ +5V TPINTPIN+ LEDBNC LED0 LED1 LED2 AUI JP PNP BS0 BS1 BS2 +5V BS3 BS4 BA15 PL0 BCSB EECS PL1 IRQS0 IRQS1 IRQS2 IOS0 IOS1 GND IOS2 IOS3 GND SD15 SD14 +5V SD13 SD12 SD11
I/O I I I I I O I/O I/O I/O I/O I/O I/O I/O I/O O O O O I O I I I I I I O O O O I I I I I I I I O I O O I I I I I I I I I/O I/O I/O I/O I/O
Remarks Memory Write N.U. (Pull-Up) N.U. (Pull-Up) Hardware Reset Chip Select Wait to CPU DATA Bus
No. 93 94 95 96 97 98 99 100
CPU SD10 SD9 SD8 SLOT16 INT7 INT6 INT5 INT4
Signal name SD10 SD9 SD8 SLOT16 INT7 INT6 INT5 INT4
I/O I/O I/O I/O I O O O O
Remarks N.U. (Pull-Down) N.U. (Pull-Down) N.U. (Pull-Down) Pull-Down N.U. (Pull-Down) N.U. (Pull-Down) N.U. (Pull-Down) N.U. (Pull-Down)
Note: Signals suffixed with the letter "B" are active in low level.
5. MEMORY MAP
10Base-T output + 10Base-T output N.U. (Pull-Down) N.U. (Pull-Down) Oscillator connection terminal Oscillator connection terminal N.U. (OPEN) N.U. (OPEN) N.U. (OPEN) N.U. (OPEN) 10Base-T input 10Base-T input + N.U. (OPEN) N.U. (OPEN) N.U. (OPEN) N.U. (OPEN) GND Pull-Up OPEN OPEN OPEN OPEN OPEN OPEN N.U. (OPEN) OPEN N.U. (OPEN) N.U. (OPEN) OPEN OPEN OPEN OPEN OPEN OPEN OPEN OPEN N.U. (Pull-Down) N.U. (Pull-Down) N.U. (Pull-Down) N.U. (Pull-Down) N.U. (Pull-Down)
H'FFFFF000 Built-in RAM H'FFFFFFFF H'00400000 SRAM H'00407FFF H'00000000 Flash H'0007FFFF CS0 SPACE
1 The CS0 space is a physical of 4 MB. It uses LA0~LA16 alone and thus LAP AROUND occurs. In addition, the data bus size is set to 8 bits using the operation mode setting terminal of the CPU.
CS1 SPACE
2 The CS1 space is a physical space of 4 MB. Is uses LA0~LA14 alone and thus LAP AROUND occurs. The data bus size is 8 bits.
H'00800000 Dual-Port SRAM H'00800FFF
CS2 SPACE
3 The CS2 space is a physical space of 4 MB. It uses LA0~LA11 alone and thus LAP AROUND occurs. The data bus size is 8 bits.
H'00C00000 H'00C***** LAN Controller
CS3 SPACE
4 The CS3 space is a physical space of 4 MB. Is uses LA0~LA19 alone and thus LAP AROUND occurs. The data bus size of the LAN controller is fixed to 8 bits.
H'01000000
DRAMS space
H'02000000
Reserved
H'FFFF8000 Built-in peripheral Module H'FFFF8800 Reserved
6. INTERFACE WITH HOST CPU

1) SIGNAL LINES
The following signal lines are required for the interface with the host CPU. Signal name A0~A11 D0~D7 /RD /WR /DPCS /LRES /INTSR /INTSW A13~A15 Vcc GND I/O I I/O I I I I O O I Address Bus from host CPU Data Bus from host CPU Read signal from host CPU Write signal from host CPU Chip select from host CPU Rest signal for this board from host CPU Data read end interrupt from board CPU Data write end interrupt from board CPU Address bus from host CPU (for decode) Power(+5V) GND Description Connected to DP-RAM DP-RAM DP-RAM DP-RAM DP-RAM Board CPU LOGIC LOGIC LOGIC Connection pin A0R~A11R D0R~D7R /OER R/WR /CER /RES
Signals prefixed with a slash "/" are active in low level.
Cautions to be taken when designing the host side

1. It is preferable that /LRES signal to be input into the board can also be controlled by software. 2. The access timing satisfies the dual-port SRAM specification.
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing (1,5,8)

tWC
ADDRESS
Timing Waveform of Read Cycle No. 1, Either Side (1,2,4)

tRC
ADDRESS
OE
tAS(6) tAW tWR(3) tHZ(7)
CE
tWP(2)
tAA tOH
DATAOUT PREVIOUS DATA VALID
(5)
R/W
tOH
tLZ(7)
DATA VALID
tWZ(7) tOW
(4)
tHZ(7)
(4)
DATAOUT
tDW
tDH
Timing Waveform of Read Cycle No. 2, Either Side (1,3)

tACE
CE
DATAIN
NOTES:
tHZ(2) tHZ(2)
VALID DATA(4)
tAOE(4)
OE
1. R/W or CE must be HIGH during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of a CE =VIL and R/W = VIL. 3. tWR is measured from the earlier of CE or R/W going to VIH to the end-of-write cycle. 4. During this period, the I/O pins are in the output state, and input signals must not be applied. 5. If the CE = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal (CE or R/W) is asserted last. 7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 500mV from steady state with the Output Test Load (Figure 2). 8. If OE = VIL during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
tLZ(1)
DATAOUT
ICC
tPU
tLZ(1)
50%
tPD
50%
CURRENT
ISB
NOTES: 1. Timing depends on which signal is asserted last, OE or CE. 2. Timing depends on which signal is de-asserted first, OE or CE. 3. R/W = VIH. 4. Start of valid data depends on which timing becomes effective, tAOE, tACE or tAA 5. tAA for RAM Address Access and tSAA for Semaphore Address Access.
2) DATA COMMUNICATION
Data is transmitted from the host CPU to the TCP/IP board or vice versa through the dual-port SRAM. If data is written into the same address of the dual-port SRAM from both sides or written into and read from the same address from both sides, data is not assured. The following procedure should be observed. The format of data to be handled should meet the software specifications.
7. LAN CONTROL
This board fixes RTL8019AS to the 8-bit mode on hardware.
CPU /CS3 A19-A0 D7-D0 /RD /WRL AEN SA19-SA0 SD7-SD0 IORB IOWB INT0 IOCHRDY RTL8019AS SLOT16 GND
Write
Read
/IRQ2 /WAIT
Preceding data read end interrupt?

Y
Data write end interrupt?

Y
The initial values of the items in the table are set as shown below by hardware. Item I/O Base Address Network Media Type 300H TP/CX automatic detection Disable INT0 Setting Remarks IOS3~0=0,0,0,0 PL1~0=0,0 BS4~0=0,0,0,0,0 IRQS2~0=0,0,0
Write data
Read data
Generation of write end interrupt
Generation of read end interrupt
BROM Size & Memory Base Address IRQ Select
Interrupt signals from host to board : Write/INTHW (Host Write),

Read/INTHR (Host Read) /INTHW (Host Write) is generated by writing into the address H7*** of the dual-port SRAM and cancelled by outputting the /HWACK signal by 100ns LOW pulse. /INTHR (Host Read) is generated by reading the address HB*** of the dual-port SRAM and cancelled by outputting the /HRACK signal by 100ns LOW pulse.
Any data loading EEPROM is not used. MAC address should be written by the CPU reading data on the flash memory and writing the register of the LAN controller.
8. PORT SETTING
The common pins of the CPU are set as shown below. Pin No 2 24 25 26 28 29 30 31 44 45 106 107 108 110 112 I/O I I I I I O O I O O O O O O O Selection signal PE15 /IRQ0 /IRQ1 /IRQ2 /IRQ3 A18 A19 /WAIT /CS3 /CS2 PE8 PE9 PE10 PE11 PE13 Remarks /WP(FLASH write STATUS) Host write end interrupt ( Host read end interrupt ( Interrupt from LANC ( Reserve ( Edge detection) Edge detection)
Interrupt signals from board to host : Write /INTSW (Slave Write),

Read /INTSR (Slave Read) /INTSW (Slave Write) is generated by outputting the /SWRQ signal by 100ns LOW pulse and cancelled by writing data into the address HB*** of the dual-port SRAM from the host side.. /INTSR (Slave Read) is generated by outputting the /SRRQ signal by 100ns low pulse and cancelled by reading data from the address H7*** of the dual-port SRAM.
Edge detection)
Edge detection)
Address Bus Address Bus wait from LANC Chip Select for LAN (Usual access space) Chip Select for dual-port SRAM /SRRQ (Board side read end request) /SWRQ (Board side write end request) /HRACK (host side read end interrupt cancel) /HWACK (host side write end interrupt cancel) /RSTDRViActive Lowj
9. CONNECTOR PIN TABLE

1) HOST I/F CONNECTOR
Pin No. 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 Signal name +5V +5V A15 A13 /DPCS A11 /RD A1 A3 A5 A7 A9 D6 D4 D2 D0 /INTSR NC GND GND Pin No. 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 Signal name +5V +5V A14 A12 /WR A10 A0 A2 A4 A6 A8 D7 D5 D3 D1 /LRES /INTSW NC GND GND
10. SWITCH SETTING

The board has two switches on it: program loading EPROM(Master ROM) selection switch (SW1) and flash memory write protect switch (SW2).
1) LOCATION OF SWITCHES
The two switches are located on the board as shown below.
SW2
SW1
2) SWITCH SETTING AT SHIPPING

The factory setting of the switches are as follows: Switch SW1 SW2 Setting 4pin side GND side Details of setting Boot from FLASH MEMORY Write protect into FLASH MEMORY
3) FUNCTIONS OF THE SWITCHES

3)-1. Program loading EPROM (Master ROM) selection switch: SW1
SW1 selects booting from EPROM (Master ROM) to write program data into flash memory. When writing data from EPROM (Master ROM) to flash memory, switch over to 6-pin side. Usually, SW1 is set to marking side.
2) RELAY CABLE
Pin No. 1 2 3 4 5 Signal name TX+ TXRX+ RXGND
FLASH Usual setting 4 5 Writing from EPROM (Master ROM) 6 EPROM 1 2 3 SW1
3) RJ-45 CONNECTOR
Pin No. 1 2 3 4 5 6 7 8 Signal name TX+ TXRX+ NC NC RXNC NC
SW2 Usual setting
3)-2. Flash memory write protect switch: SW2

SW2 inhibits writing into flash memory. When writing data from the EPROM (Master ROM) to the flash memory. Usually, the switch is set to the marking side.
Writing from EPROM (Master ROM)
GND
VCC
11. WRITING / READING THE MAC ADDRESS / FIRMWARE PROGRAM

1) WRITING THE MAC ADDRESS & FIRMWARE PROGRAM
1) Install the EPROM (Master ROM) to the TCP/IP I/F PWB (IC5:IC socket). 2) Set the following switches to the (Writing mode) on the TCP/IP I/F PWB. Display : [5. DIAGNOSTIC]
SW2
Normal mode Writing mode
IC5: IC socket
GND VCC
UP-600/700 DIAG V1.0A PRODUCT & TEST RAM & ROM & SSP CLOCK & KEY & SWITCH SERIAL I/O DISPLAY & PRINTER MCR & DRAWER TCP/IP
Select the [TCP/IP] and press the ENTER key Display : [TCP/IP]
4 FLASH 1 2 3
EPROM
SW1:
Normal mode 5 Writing mode 6
[EPROM] SW1 : [FLASH] SW2 : [GND] [VCC] 3) Set the mode switch of the UP-700 to SRV position. 4) Turn ON the AC switch of the UP-700. 5) Display : [SRV MODE]
TCP/IP & PRINTER DIAG SELF Check LOOPBACK Check MAC ADDR & FIRM Ver. Read MAC ADDR & FIRM WRITE DATA Trans. (MA) DATA Trans. (SA)
SRV 1 2 3 4 5 READING SETTING IRC SET UP DOWN LOAD DIAGNOSTIC

Select the [MAC ADD&FIRM WRITE] and press the ENTER key
Select the [5. DIAGNOSTIC] and press the ENTER key
Display : [MAC ADD&FIRM WRITE]
When writing is completed, the following message is displayed as shown below. Display :
MAC ADDR & FIRM Write MAC ADDRESS: AAA BBB CCC 08 00 1F XX YY ZZ
MAC ADDR & FIRM Write MAC ADDRESS: AAA BBB CCC 08 00 1F XX YY ZZ TCP/IP FIRM CHANGE: FIRM CHANGE PASS!!
AAA BBB CCC MAC Address : Decimal number XX YY ZZ MAC Address : Hexadecimal number
6) 7)
Press the CANCEL key to exit. Turn OFF the AC switch of the UP-700. Remove the EPROM (Master ROM) from the TCP/IP I/F PWB (IC5: IC socket). Set the following switches to the (Normal mode) on the TCP/IP I/F PWB. SW1 : [EPROM] [FLASH] SW2 : [VCC] [GND]
Input the MAC address and press the ENTER key.
8) 9)
MAC address:
The TCP/IP I/F PWB has a seal carrying a MAC address of hexadecimal number attached on its CPU. Enter this unique code (XXYYZZ) of hexadecimal number as the values (3 values of 3 digits) converted to decimal numbers, through the keyboard. Example: When XX,YY,ZZ = 10,00,EB, enter 016,000,224 as decimal numbers.
SW2
10) Execute the "Service reset" .
SW1
IC1 CPU MAC ADDRESS 08001F : Fixed code XXYYZZ : Unique code
08001F XXYYZZ
Start the writing of the MAC address & Firmware program
2) READING THE MAC ADDRESS & FIRMWARE PROGRAM

1) Set the mode switch of the UP-700 to SRV position. 2) Display : [SRV MODE] Display : [MAC ADD&FIRM Ver. Read]
SRV 1 2 3 4 5 READING SETTING IRC SET UP DOWN LOAD DIAGNOSTIC
MAC ADDR & FIRM Ver. READ MAC ADDRESS: 08 00 1F XX YY ZZ FIRMWARE VERSION: 27040
XX YY ZZ MAC Address : Hexadecimal number
Select the [ 5. DIAGNOSTIC ] and press the ENTER key Display : [ 5. DIAGNOSTIC ]
: Version number
3) Press the CANCEL key to exit .
UP-600/700 DIAG V1.0A PRODUCT & TEST RAM & ROM & SSP CLOCK & KEY & SWITCH SERIAL I/O DISPLAY & PRINTER MCR & DRAWER TCP/IP
Select the [ TCP/IP ] and press the ENTER key Display : [TCP/IP]
TCP/IP & PRINTER DIAG SELF Check LOOPBACK Check MAC ADDR & FIRM Ver. Read MAC ADDR & FIRM WRITE DATA Trans. (MA) DATA Trans. (SA)
Select the [MAC ADDR&FIRM Ver. Read] and press the ENTER key
8
IPLON0 VCC
CHAPTER 8. CIRCUIT DIAGRAM

8 7 6 5 BR39 10K*4 R58 10K 1 2 3 4
1/8
1. MAIN PWB CIRCUIT DIAGRAM

R64 /RFSH /HWR /RD /AS # 100pFX3 C46 X1 19.66MHz NOT USED ! Be Short Pattern IC2 R70 5 CLK VDD FS1 OE# 6 C53 (0.1uF) 7 8 C52 (10uF/10V OS) FOR RS232C CH8 VCC FB1 (BFW7550R2) NOT USED (19.6608MHz) (8pF) (33) FS0 GND X2 X1 (W42C31-03) 1 4 3 C54 2 2 1 X2 C55 (8pF) R71 (0) R72 VCC NOT USED C47 C48 C49 C50 R66 R67 VCC R68 R69 IC1 47 47 VCC 47 47 47
1) CPU
VCC
BR23
10K*4
BR24
10K*4
1 2 3 4 1 2 3 4
8 7 6 5 8 7 6 5
D0 D1 D2 D3 D4 D5 D6 D7
C1 D[0..15] BR33 100*4 /RESET NMI
C3
C5
C7
100pF X8
C2
C4
C6
C8
BR25
10K*4
BR26 100*4
BR34
10K*4
1 2 3 4 1 2 3 4 BR35 100*4 D[0..15] BR36 100*4
8 7 6 5 8 7 6 5
D8 D9 D10 D11 D12 D13 D14 D15
100pF X8
C9
C11
C13
C15
C10
C12
C14
C16
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 TXDI RXDI /TXD2 /RCVDT2 SCKI UASCK /IRQ1 /IRQ0
1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4
8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5
A[0..23]
C
TM VCC VRF 8 7 6 5 BR37 10K*4 /VPTEST VPR
C
VCC +24V
VCC
BR27 10K*4
BR28 1 2 3 4
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 /SRESET FVPON NORDY /IPLON1 /IPLON0 /CI2 /RTS2 C191 330pF C56 330pF
D1 1SS353 /VPTEST /IPLON1 /IPLON0 /STOP PNLSNS
10K*4
R78 16KF
BR29 10K*4
BR30 10K*4
A16 A17 A18 A19 A20 A21 A22 A23
R79 3.6KF FOR RS232C CH8
C59
BR31
/DCD2 /CTS2 /DSR2 /DTR2
10K*4 DOPS /DR0 /DR1 C23 C24
BR32 10K*4
/TPRCRQ C57 JSDOWN RSDOWN 470pF VCC FVHS
1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4
8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 C25 C29 C31 C27 C32 C30 C26 C28 HD641510810 C33 C35 C37 C39 C34 C36 C38 C40 C58 100pF X8 /OPBS C51 330pF VCC 330pF 100pF X8
C17
C19
C21
C18
C20
C22
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 RES NMI VSS D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 VSS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 VSS A16 A17 A18 A19 A20 A21 A22 A23 VSS P30 WAIT P31 BACK P32 BREQ P33 P34 P35 P36 P37 VCC P40 STBY MD2 MD1 MD0 VCC RFSH LWR HWR RD AS E X VSS XTAL EXTAL VSS TXD2 RXD2 TXD1 RXD1 SCK2 IRQ3 SCK1 IRQ2 IRQ1 IRQ0 VCC AVCC (P73)VPPS (P72)VPTEST (P71)VPR (P70)VPJ AVSS VSS P67 P66 P65 P64 P63 P62 P61 P60 P57 P56 P55 P54 P53 P52 P51 P50 VSS P47 FTI2 P46 P45 FTI1 P44 P43 P42 P41 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57
100pF
X8
B
MCRINT D2 1SS353 VCC VPR R80 16KF
R82 10K R84 C43 0.1uF C44 0.1uF C45 10uF/10V OS C60 1000pF C41 8 7 6 5 100pF BR38 10K*4 C42 100pF 10K R85 (10K) /WAIT /BACK /BREQ
R83 (0) CN1 1 2 REJ CN(5267-02A RED) R86 0
R81 3.6KF
VCC
|LINK
1 2 3 4 VCC
/OPBS /BREQ MCRINT /TPRCRQ
R87 10K R89 10K C61 1000pF R90 (10K)
R88 (0) CN2 1 2 NEJ CN(5267-02A WHITE) R91 0
|POWER.SCH |NEW_GA.SCH |FLASH.SCH |LCDC.SCH |RS232C.SCH |DRAWER.SCH |CN.SCH |FMC.SCH
2) POWER
2/8
D
VO
D
MICP1 +24V SHORT HEAT SINK L1 180uH FUSE2.0A/250V(LT5)
Symbol/PartsCod)
UL/CSA T2A/250V Q6 KTD998 F2 BD1 IC31 5 2 LM2574HVN 6,8PIN:NC R213 1.2KF 3 D6 RB160L-60 1 7 R210 18K 4 C177 10uF/50V CP301 C193 0.1uF CN12 F1 C175 M0.033u C176 6800uF/63V 1 2 PS CN R211 10
F3,ICP2 +24VL
POWER UNIT UL/CSA 3.15A/125V
R212 22KF C178 2200uF/35V ZD4 PTZ30B
[+24V]
CORE
+24VL
4 L2 MICP2 +5V VCC 100uH SHORT 5 D7 RB060L-40 C180 0.01uF R215 1KF 1SR159-200 D9 C181 1000uF/16V ZD1 UDZ6.2B R214 3KF 2
IC32 PQ1CG2032FZ
VCKDC
[+5V]
R56A 160
C179 10uF/35V
MICP3 VCKDC SHORT 2 C43A 0.1uF 1 BT CN (5267-02A BLUE) R57A 150 CN10A
B
IC25 4 PQ1CG2032FZ L3 220uH 5 3 C183 0.01uF D8 RB060L-40 C184 1000uF/16V R217 1KF R216 3.6KF ZD2 UDZ6.8B 2
+24VL
B
MICP4 +5.7V SHORT VLED
[VLED POWER]
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
C182 10uF/35V
8
+24V R184 VRES R183 5.6K 10K F4,ICP4 FUSE2.5A/250V(LT5) FB21 VH 8 7 6 5 4 3 BR7 10k*2 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 FB34 VJCOM R186 10K CB3225 1 2 3 4 S Q5 G D VRCOM FB35 CB3225 D5 1SS353 VCKDC VCC 4 9 12 8 11 13 IC11C 74HC00 IC11D 74HC00 10 IC11B 74HC00 7PIN:GND VRESC VCC3 6 5 VCC +24V VRES R135 18KF 5 1K 6 4 8 7 6 5 8 VCC VCC 47pF*25 BR15 1K*4 1 2 3 4 1 2 3 4 TP2 TP5 TP6 RAS RBS RCS RDS TP4 JAS JBS JCS JDS BR16 1K*4 0.1uF*3 1 2 R139 R171 1K FB32 C132 47pF /TPRCRQ IC7B 4 6 13 74LV08 RRRRJ J J J DCBA DCB A SS SS S SS S R150 1K R151 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 5 5 5 6 6 6 6 6 6 6 6 6 6 7 7 7 7 7 7 7 7 7 7 8 8 8 8 8 8 8 8 8 8 9 9 9 9 9 9 9 9 9 9 0 0 0 0 0 0 0 0 0 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 IC9 NEW G_A 0 VCKCD 74LV08 1K VCC3 B A 1 4 B B B B B B A A A A A A 1 1 1 1 9 8 3 2 1 0 VCC 5 R261 BA[0..14] VCC PTJM PTRM R172 1K R176 1K 4.7K C109 TM 0.1uF CUTS PHUPS VCC CB3225*2 FB33 C133 R177 1K 47pF 4 IC12A BA10393 R170 1K VCC VCC 3 R137 1.15KF R138 133F 8 7 6 5 C111 C112 C113 VRES R192 4.7K IC12B BA10393 7 A1036 SMD 68F 8 Q1 R157 5.6K R158 1 4 1 4 1 4 VCC VCKDC MTD2955V VCC R187 1W 8.2 JP3 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 R180 2.2K Q4 C2412 R181 10K 7 1 2 6 IC18 TA8428K R264 10K R263 10K VCC R136 R185 33K R140 20K CB3225 C110 10uF/50V G D Q3 MTD2955V BR1 10K*4 BR2 10K*4 BR3 10K*4 BR4 10K*4 BR5 10K*4 BR6 10K*4 +24V VCC Q2 C2412 S C131 2200uF/35V
3) GATE ARRAY
R179 2.2K R182 10K
3/8
+24V C135 10uF/35V
D
C136 0.1uF 4 CB3225*2 FB36 3 5 C137 0.1uF FB37
AUTO CUT
CUTM+
CUTM-
VCC
FB20
TM1
BA0 BA1 BA2 BA3 BA4 BA5 BA6 BA7 BA8 BA9 BA10 BA11 BA12 BA13 BA14 BD0 BD1 BD2 BD3 BD4 BD5 BD6 BD7 /BRD /BWR /BRAS
CB3225
C108 100pF
VCC
VCC
8 7 6 5
8 7 6 5
BR17 10K*4 IC7D 12 11 R262 1K
BR18 10K*4
IC36 BA033F VCC C234 0.47uF 4 8 C233 22uF/16V 6 VCC3
1 2 3 4
1 2 3 4
C
VCC3
SI CLOCK SO /LATCH /STRB4 /STRB3 /STRB2 /STRB1
CB3225*8 FB12 FB13 FB14 FB15 FB16 FB17 FB18 FB19
C114 C115 C116 C117 C118 C119 C120 C121 C122 C138 C139 C140 C141 C143 C144 C145 C146 C147 C148 C149 C150 C151 C152 C153 C154 C155
C
1 74HC00 4 VCC
1 IC10 /RESET 2 IC11A 3
C100 330pF
C101 330pF
C102 330pF
C103 330pF
C104 330pF
C105 330pF
C106 330pF
C107 330pF
C123 0.1uF +24V R152 4.7K 7 C126 330pF VCC IC15B 4 BA10393 R153 4.7K 1 C127 330pF 3 IC15A BA10393 VCC R154 240 1 3 C130 1000pF +24V VCC D3 1SS353 8 2 R163 33K 1 3 R165 5.6K 4 8 2 FB23 CB3225 5 8 6 FB22 CB3225
V S S G S L S G C S DW D I C T T T I R J P P P V G V R J C C DT T NT AONL I TOT NS T T I NP P HCF HNDVVT T DO C S HE S S RHE E URPCDDPPB A D4 5 D6 T OOOO P E O # CD C S L T DNT T Q# # # NN S M C # E# 2 1 # HO K P F P C # # D D# T T T CC E W D O 8 RRUU T O T D GGT T T 6 O # # # 9 T 7 28 27 26 25 24 23 BA13 BA8 BA9 BA11 BA10 22 21 20
RR RRJ J J J P P P B B GB B B B B B V DC B A D C B A T T OA A NA A A A A A D SS SS S S S SRJ P1 1 D1 1 1 1 9 8 D 3 2 1 0 MMI 5 4 PP RRS V RJ RT J J T F F F RT R S MMMA # # # J R J T GR T GT T M MI S # # DS P G T #
C124 (10uF/16V)
C125 10uF/16V VJCOM(MAX46V) VRF /JPES R155 100K CB3225*4 C128 0.1uF C195 10uF/35V /RPES 1 1 0 5 1 6 IC16 2 JAS KIA431A JDS 5 14 INA INB R156 100K C129 0.1uF /JPFA /JPFB /JPFD /JPFC
VRESC
/FMRTS /FMDTR FMRDY OE A10 CS
BA7 BA6 BA5 BA4 BA3 BA2 BA1 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 VCC /WE A13 A8 A9 A11 D0 D1 D2 GND D7 D6 D5 D4 D3
BA14 1 BA12 2 3 BA7 4 BA6 5 BA5 BA4 6 BA3 7 BA2 8 9 BA1 BA0 10 BD0 11 BD1 12 BD2 13 14 RAM(256K) SOP 19 18 17 16 15 BD7 BD6 BD5 BD4 BD3
BA0 /BWR /BRD BRAS /BRAS BD7 BD6 BD5 BD4 BD3
FB24 FB25 FB26 FB27 8 V S SYNCA SYNCB RR RE ER GGS F F S BA B B AA 2 11 OOOO UUUU T T T T B/ A / B A IC13
FMSD FMSCK FMRD /BUSY /TRQ2 /TRQ1 /INTSR /INTSW /EXWAIT /DPCS /VWAIT /VIO /VMEM BD2 BD1 BD0 BD[0..7] VCC3 VCC3
G/A
/SHEN /KRQ /POFF HTS1 /SCK1 STH1 /IPLON0 /RESET
R230 9.1kF
1 1 2 4 9 3 3 7
SMA7036M
PTJM /JPFA R164 100K 4 IC17A BA10393 D +24V
R231 3.09kF
R232 1kF
B
R234 1F(1W) G VCC D4 1SS353 8 6 /RPFA R173 33K R174 7 5 4 IC17B BA10393 PTRM CB3225*4 S Q7 2SK1826 R175 5.6K JSDOWN R233 1F(1W) VRCOM(MAX46V)
VCC BR11 10K*4 8 7 6 5 S SI I U PRR P A OO V A A AA AA AA AA A A AA GV G G G R Q Q WR A H M M S G S S V D 2 2 2 2 1 1 1 1 1 1 1 1 1 1 A A A A A A A A A A N D DDD N DD NDD D NQ1 0 RD S A D D CNI OD D3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 DD7 6 5 D4 3 D2 1 0 D# # # # # # I 0 1 K D1 1 D VCC
/OPTCS IPLON0 RCP1 RDD1 CLS1 RCP2 RDD2 CLS2 RCP3 RDD3 CLS3 STH2 /SCK2 HTS2 /SHEN2 /RTS1 /DTR1 /TXD1 /RCVDT1 /CTS1 /DSR1 /CI1 /DCD1
R266 1K
R267 1K
BR9 10K*4
BR10 10K*4
156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 DD GND OO T T GND 4 5 ST3# DOT3 ST2# DOT2 ST1# DOT1 NC TTHR RTS3# DTR3# RXRDY3 TRXRDY3 TXRDY3 TXD3 TRXC3 RXD3 BUSY3# EXINT3# EXINT2# EXINT1# EXINT0# EXWAIT# DSF2# VWAIT# DSF1# DSCX# GND VDD OPTCS# IPLON RXC1 RXD1 DSR1# RXC2 RXD2 DSR2# RXC4 RXD4 DSR4# STH2 SCK2# HTS2 INT4# RTS5# DTR5# TXD5 RXD5 CTS5# DSR5# CI5# CD5# GND GND GND GND BA7 BA6 BA5 BA4 BA3 BA2 BA1 GND BA0 BWR# BRD# BRAS BRAS# BD7 BD6 BD5 GND BD4 BD3 GND BD2 BD1 BD0 GND VDD INT3# INT2# INT1# INT0# HTS1 SCK1# STH1 IPLON# RESET# UTST# USEL0 USEL1 USEL2 MCRINT WAIT# FROS1# RASPN1 RASPN2 EPROM1# DSEX# RXDH TXDH SCKH GND GND MCRINT /WAIT /FROS1 RASPN1 RASPN2 /EPROM1 /EPROM2 RXDI TXDI SCKI
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
4 3
8 7 6 5
8 7 6 5
BR41 10K*2
1 2
1 2 3 4
1 2 3 4 1 2 3 4
1 1 1 1 1 9 9 9 9 9 9 9 9 9 9 8 8 8 8 8 8 8 8 8 8 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 4 3 2 1 0
VCC3 R260 220 OSO1 OSI1 UASCK R259 N.U OSI1 7.37MHz OSO1 X3
100K
C197 10uF/35V FB28 FB29 FB30 FB31 1 1 0 5 1 6 8 V S RAS RDS 5 14 INA INB SYNCA 2 11 SYNCB RR RE ER GGS F F S BA B B AA D11 1SS353 IC37D JBS 11 13 JAS 12 74HC02 IC7A 1 IC7 7Pin---GNG 14Pin---VCC D12 1SS353 D R237 3.09kF R238 1kF R236 9.1kF 1 1 2 4 9 3 3 7 IC14
/RPFA /RPFB /RPFC /RPFD
/POFF /KRQ HTS1 /SCK1 /SHEN /SHEN2 /SCK2 HTS2 A[0..23] D[8..15] A AAA A A AA A A A AAA A A AA A A AA AA 2 2 2 2 1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0 3 2 1 0 9 8 7 6 5 4 3 2 1 0 DDD 1 1 1 5 4 3 DD 1 1 2 1 DDD 1 9 8 0
RASPN1 RASPN2 /OPTCS /VMEM /WAIT /FROS1 /VIO UASCK
OOOO UUUU T T T T B/ A / B A # /AS /RD /HWR /IRQ0 /IRQ1 NMI
330pF*8 VCC BR14 10K*4 8 7 6 5 R265 10K 1 2 3 4 VCC3 VCC
C205 C206 C207 C208
C209 C210 C211 C212
100pF*8
C213 C214 C215 C216
C217 C218 C219 C220
VCC
BR12 10K*4
BR13 10K*4
SMA7036M
8 7 6 5
8 7 6 5
A
C94 10uF/16V C95 0.1uF
A
R240 1F(1W) /SRESET /RES C96 74LV08 VCC RAS IC7C 9 8 /RESET 10 74LV08 /RES /RES 6 74HC02 3 2 /LRES For TCP/IP CN IC37B RBS 5 4 S G Q8 2SK1826 RSDOWN R239 1F(1W)
1 2 3 4
1 2 3 4
IPLON0 /TXD1 /DTR1 /RTS1 /DPCS
**
/EPROM1 /EPROM2 RXDI /IRQ0 NMI /TWAIT /INTSW /INTSR C241 330pF
100pF*8
C221 C222 C223 C224 C229 C230 C231 C232
C225 C226 C227 C228
330pF*4
8
D[8..15] A[0..21] IC3 A21 NOT USED VCC IC4 1 2 3 (7S04FU) 4 /A21 5
4) FLASH ROM
4/8
A21
D8 D9 D10 D11 D12 D13 D14 D15
R93 R92 0
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 D0 D1 D2 D3 D4 D5 D6 D7 C62 0.1uF VCC C63 10uF/16V
33 35 38 40 44 46 49 51 34 36 39 41 45 47 50 52
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 3 29 30 A21 D[0..7]
32 28 27 26 25 24 23 22 20 19 18 17 13 12 11 10 8 7 6 5 4
IC3 VCC --- GND
VCC /RD /HWR FVPON /RES /IPLON0 VPP VCC VCC VCC 9 37 43 VCC 15 21 42 48 GND GND GND NC NC NC
/FROS1
R94 1K
NORDY
C64 100pF
/RD /HWR FVPON /RES NORDY /IPLON0
14 2 54 55 56 16 53 31 1 CE0 CE1 OE WE WP RP RY/BY BYTE 3/5
LH28F016SUT
A[0..21]
A[0..21]
B
VCC IC3A A17 /IPLON0
2 IC35A (74LS125) 1
A0 4 * IC35 7Pin : GND 14Pin : VCC 8 /IPLON0 1 0
IC35B (74LS125)
B
9 IC35C (74LS125)
/HWR /RES
A16 A15 A14 A13 A12 A11 A10 A9 A20 A21 /HWR /RES D7 D15 D6 D14 D5 D13 D4 D12 D3 D11 D2 D10 D1 D9 D0 D8 /RD /FROS1 A1
11
12 IC35D (74LS125) 1 3
FVPON
/RD /FROS1
FVPON NORDY A19 A18 A8 A7 A6 A5 A4 A3 A2 (MBM29F160(FLASH 16M))
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 A15 A14 A13 A12 A11 A10 A9 A8 A19 NC /WE /RESET NC /WP RY/BY A16 A17 A7 A6 A5 A4 A3 A2 A1 A16 /BYTE VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 /OE VSS /CE A0
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
A
D[8..15] D[8..15] D[0..7] D[0..7]
8
[POFF]
5) LCDC_MEMORY
D[8..15] +24V VCC
5/8
D10 IC28
D D D D D D D D 1 1 1 1 1 1 9 8 5 4 3 2 1 0 VCC (1SS353) R222 9.1KF R227 4.7K R226 IC22 56K A[0..13] R223 9.1KF 8 3 1 2 BA10393 4 ZD3 RD4.3MB1 C190 1000pF R224 4.7KF C189 1uF/50V /POFF IC27A
D
R225 3.9K(1/4W)
D
(KIA7045F)
1 6 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 7 6 5 4 3 2 4 0 9 8 7 6 5 4 3 0 9 8 7 6 5 4 3 7 3 2 2 4 3 8
B D D D D D D D D D D D D D D D D V V V V V V V H 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0 D D D D D D D E 5 4 3 2 1 0 D D D D D D D
LCD Controller M66271FB
VCC
/RESET /VWAIT /VMEM /RD /HWR M LCDENB VCC
CP LP LD0 LD1 LD2 LD3 FLM /RESET /VWAIT /VMEM /RD /HWR
C
LCDC(M66271FP)
/VIO
/VIO
9 78 66 67 69 70 71 72 68 11 7 6 5 4 3 2 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 M LCDENB 31 30 29 28 27 26 22 21 20 19 18 17 16 15 62 61 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 M LCDENB
C
R241 *150F R245 56K R242 *150F 5 7 R243 C240 0.1uF 2.2KF 6 4 BA10393 +24V 8 IC27B
VCC
MPUCLK OSC1 CP LP UD0 UD1 UD2 UD3 FLM RESET WAIT MCS RD LWR HWR IOCS M P U S E L
O S N N N N N N N N N N V V V V V V V V V V V V C . . . . . . . . . . S S S S S S S S S S S S 2 C C C C C C C C C C S S S S S S S S S S S S
1 7 7 7 7 7 3 3 3 3 3 3 5 8 6 4 3 2 1 2 6 4 1 2 9 6 4 3 5 2 9 8 7 6 3 1 0 5 1 0 5 4 3 5 4 1 0
C235 10uF/16V
C236 0.1uF
R244 2KF
A[0..18]
B
VCKDC RASPN1 VCKDC 1 4 9 A15 A17 /HWR /HWR /RESETS 8 10 IC24C 74LV00A R208 10K /RD A10 /RASPN1 /RD C171 1000pF 2 IC24A 74LV00A 7PIN:GND 1 3 VCKDC 1 4 4 5 IC23 4M-SRAM
VCKDC 1 4 6 /RASPN1
IC24B 74LV00A /RESET
VCC A15 A17 WR A13 A8 A9 A11 A13 A8 A9 A11
32 31 30 29 28 27 26 25
C173 1000pF
A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 1 2 3 4 5 6 7 8 9 10 11 12 A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 RD A10 CS 24 23 22
VCKDC 1 4 12 C172 1000pF 11 RASPN2 13 IC24D 74LV00A /RASPN2 /RASPN2 (OPT RAM)
D8 D9 D10 D8 D9 D10 GND C168 0.1uF TSOP VCKDC 16 D15 D14 D13 D12 D11 C170 100pF
13 14 15
21 20 19 18 17
D15 D14 D13 D12 D11
A
RASPN2
C169 (10uF/16V)
D[8..15]
8
< RS232C RELAY PWB >
VSC S401 1 2 3 PF401 VCC POLY SW C158 0.1uF R401 (R1) (0) SSS312
6) RS232C
6/8
VCC
D [ CH1 ]
TO MAIN BY CABLE
IC19 V+ C160 0.47uF CN401 27 VCC 2 6
28 C1+ C1C2+ C2T1IN T2IN T3IN R1OUTB R2OUTB R1OUT R2OUT R3OUT R4OUT R5OUT EN VCC CHANNEL 1 FOR RS232C RELAY PWB MAX3241 G N D SHDN 2 5 22 CIA ERA CSA SDA RSA RDA DRA CDA FOR D-SUB 9Pin R5IN 8 * CN6 1Pin-10Pin FB45 CSA BLM31 CN6 R4IN 7 FB44 DRA BLM31 VCC R3IN 6 FB43 CIA BLM31 R2IN 5 FB42 CDA BLM31 R1IN 4 FB41 RDA BLM31 T3OUT 11 FB40 SDA BLM31 T2OUT 10 FB39 ERA BLM31 T1OUT 9 FB38 RSA BLM31 V3 C159 0.47uF
C156 0.1uF
V C C
CN402
24
C157 0.47uF
CH1
/RTS1
14
/DTR1
13
GND CIA ERA CSA SDA RSA RDA DRA CDA
5 9 4 8 3 7 2 6 1 D-SUB 9Pin
/TXD1
12
21
VCC GND CIA ERA CSA SDA RSA RDA DRA CDA
20
CN403
/RCVDT1
19
/DCD1
18
S404_1 S404_2 VSC S403_1 S403_2
JMP JMP
RSB ERB SDB
CH8
/CI1
17
/DSR1
16
/CTS1
15
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DRB ERB CSB SDB RSB RDB CIB CDB
RDB DRB CSB JMP
1 2 3 4 5 6 7 8
MODULAR(RJ45) JMP
23
VCC +24V * CN6 11Pin-20Pin FOR MODULAR RJ45 CHANNEL 8 FOR RS232C RELAY PWB
RS232C RELAY CABLE CN(20Pin,2mmPitch)
F5,ICP5
[ CH8 ]
C163 0.1uF T500mmA250V(LT5) 2 6 IC20 27 C165 0.47uF C166 (10uF/35V) * CN6 21Pin-29Pin
C237 10uF/16V
DRB ERB CSB SDB RSB RDB CIB CDB
VCC
< TCP_IP(RJ45),UPP16DP,MCR RELAY PWB >

+24V BFR601009C8NG FB501 FOR ETHERNET(RJ45),UPP16DP,MCR RELAY PWB FOR UPP16DP CN501 CN502
R 10K
C1C2+ C2T1IN T1OUT T2OUT T3OUT 11 FB48 SDB BLM31 10 FB47 ERB BLM31 T2IN T3IN R1OUTB R2OUTB R1OUT R1IN R2IN R3IN R4IN R5IN SHDN VCC MAX3241 22 8 FB53 BLM31 7 FB52 BLM31 DRB CSB 6 FB51 CIB BLM31 5 FB50 CDB BLM31 R2OUT R3OUT R4OUT R5OUT EN 4 FB49 RDB BLM31 9 FB46 RSB BLM31 V3 C164 0.47uF
C161 0.1uF C1+ V+
28
V C C
24
C162 0.47uF
/RESA RESA SCK2A /HTS2A /STH2A SHEN2A
/RTS2
14
* CN6 30Pin-40Pin TO MAIN FOR ETHERNET(RJ45),UPP16DP,MCR RELAY PWB FOR MCR
/DTR2
13
/TXD2
12
VCC
1 2 3 4 5 6 7 8 9 10 UPP16DP CN.53014-1010 CN503 RELAY CABLE CN(40Pin,2mmPitch))
21
CLS1# RDD1# RCP1# CLS2# RDD2# RCP2# CLS3# RDD3# RCP3#
20
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
/RCVDT2
19
/DCD2
18
/CI2
17
CLS1# RDD1# RCP1# CLS2# RDD2# RCP2# CLS3#
/DSR2
16
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
/CTS2
15
RDD3# RCP3#
23 G N D 2 5
1 2 3 4 5 6 7 8 9 10 11 MCR CN.35312-1110
UPP16DP,MCR RELAY CABLE CN(20Pin,2mmPitch)
CN504 1 2 3 4 5 TCP/IP CN.53014-0510 RXRX+ TXTX+ FG
CN505 1 2 3 4 5 6 7 8 MODULAR(RJ45)
+24V
7) DRAWER_MCR
VRES C99 0.1uF /DR0 /DR1
7/8
/DRAW0 /DRAW1
+24V
<DRAWER>
IC8 TD62308F FB11 BFR601009C8NG CN4 3 2 1 C87 0.1uF 3 2 1 C89 0.1uF 5046-03A DRAWER CN0 5046-03A DRAWER CN1 CN5 FB9
BFR601009C8NG C86 0.1uF FB10
C
BFR601009C8NG C88 0.1uF
FB8 DRSNS BFR601009C8NG
R119 10K
R121 DOPS 47K
R120 2.2K VCC
C90 1000pF
8 7 6 5 R107 4.7K BR19 4.7K*4
8 7 6 5 BR20 4.7K*4
B
1 2 3 4
<MCR>
B
1 2 3 4
FB2 FB3 FB4 FB5 FB6 FB7 FB60 FB61 FB62 R113 10K BLM31*9 1 2 3 4 CLS1 BR21 8 7 6 5 10K*4 1 2 3 4 BR22 8 7 6 5 10K*4 RDD1 RCP1 CLS2 RDD2 CLS1# RDD1# RCP1# CLS2# RDD2# RCP2# CLS3# RDD3# RCP3# CLS1# RDD1# RCP1# CLS2# RDD2# RCP2# CLS3# RDD3# RCP3#
A
RCP2 CLS3 RDD3 RCP3
8
VCC
+24v
VCC
8) MAIN_CN
CN9 /RD /HWR A[0..23] VH CUTM+ CUTMCUTS VJCOM /JPFA /JPFB /JPFC /JPFD /JPES VCC TM1 IC21A FB54 /RESA 2 1 BLM31 X2 IC21B FB55 SI RESA 4 /RES 3 /STH2A FB58 13 12 R206 4.7K 74LV14A IC21F /STRB4 /STRB3 SO VH BLM31 X4 74LV14A
CN8
8/8
A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4
STH2
A1 A0 IC21C FB56 SCK2A 6 5 /RESET /OPTCS VCC /RPES VRCOM FB57 /HTS2A 8 9
CLOCK /LATCH /STRB2 /STRB1
/SCK2 FB59 11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 IC21E SHEN2A IC21D HTS2 C167 470pF R207 1K
10
/SHEN2
VCKDC BR40 4.7K*4
8 7 6 5
C
1 2 3 4 T_PRINT CN(40Pin)00 6229 640 003 800 /DPCS /EXWAIT /BREQ /BACK /TRQ2 /TRQ1 /INTSR /INTSW
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 /RPFA /RPFB /RPFC /RPFD PHUPS FVHS
C
IC21(74LV14A) 7Pin : GND 14Pin : VCC
A[0..15] D[8..15]
/IRQ1 /RFSH /IPLON0
VCC VCC CN16 CN304
D15 D14 D13 D12 D11 D10 D9 D8 /POFF /OPBS
A3
/DPCS /HWR
35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 A2 /RES /AS /LRES
/RD
OPT_CN(68Pin)10 5072 0681 09 856
VCC
D[8..15]
CN17 STH1 HTS1 /SCK1 /KRQ /SHEN /STOP /POFF STH1 HTS1 /SCK1 /KRQ /SHEN /STOP /POFF VCKDC BACK-UP POWER +5.7V POWER VLED VCKDC VLED
A15 A14 A13 A12 /DPCS /HWR A11 A10 /RD A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 D15 D14 D13 D12 D11 D10 D9 D8 /LRES /INTSR /INTSW
/LRES /INTSR /INTSW
/RESETS BLM31*9
C194 22uF/16V
/RASPN2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 /EPROM1 /EPROM2 TCP_IP CN(53553-0409)
C185 1000pF
A
FB68 FB69 FB70 FB71 PNLSNS PNLSNS TP1 M LCDENB LP CP M LCDENB LP CP
FB63 FB64 FB65 FB66 FB67
VO FLM LD3 LD2 LD1 LD0 VO FLM LD3 LD2 LD1 LD0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 ROM FPC CN.(45Pin)XF2H-4515-1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
VCC /OPBS /HWR /IPLON0 /IPLON1 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 /RD D15 D14 D13 D12 D11 D10 D9 D8 /RASPN2 VCKDC VCKDC /EPROM1 /EPROM2 /OPBSI GND GND GND
CKDC CN.30P(C03-30-A-G-1)
2. CKDC PWB
SA IC9 BA00ASFP VLED SHORT LCDENB 1 6.8kF C45 22uF/16V R62 2.4kF 3 VCC C44 0.47uF 5 R61 FOR BACKLIGHT 2 4 +4.1V R71 VBLED PG10 PG9 PG8 PG7 PG6 PG5 TP1
1/3
1) DISPLAY1
VCKDC
C39 10uF/16V 6 6 6 6 6 5 5 5 5 5 5 5 5 4 3 2 1 0 9 8 7 6 5 4 3 2 IC1 C11 X1 15pF 32.768KHZ VCC C12 15pF CN1 S P P P P G G G G G G G G A O O O O 1 1 9 8 7 6 5 4 3 2 1 0 1 0 PG4 PG3 PG2 PG1 VCKDC X2 4.19MHz 1 2 3 R17 1M
C29 0.1uF R34 47K
SB SC SD SE SF SG
CKDC9
DP
C
CKDCR
/MODR /CFSR KEX0 KEX1 PDS
/MODR /CFSR KEX0 KEX1
R5 R6
47K 47K
STH1 HTS1 /SCK1 /KRQ /SHEN /STOP /POFF VCKDC VLED
STH1 HTS1 /SCK1 /KRQ /SHEN /STOP /POFF VCKDC VLED
C1 470pF S P S D D B D S S O T D D V S H S I U S T T F O I C C C T T S Z C 2 3 F P G S C K S H P Z K 2 2 2 2 2 2 2 2 2 2 3 3 3 0 1 2 3 4 5 6 7 8 9 0 1 2 C6 470pF CKDC9
C2 1000pF
R7 4.7K
R8 4.7K
ST0 ST1 R18 220 C13 0.1uF
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 SB SC SD SE SF SG P4 P0 P1 P2 P3 MODR CFSR KEX0 KEX1 RQ SKR0 ST0 ST1 G3 G2 G1 G0 TEST CL2 CL1 GND OSC1 OSC2 RESET KR3 KR2 KR1 KR0 IRQ SHEN DS0 SRES 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
/RESETS VO FLM LD3 LD2 LD1 LD0 VO FLM LD3 LD2 LD1 LD0
ST2 ST3 C5
ST2 ST3
/KR3 /KR2 /KR1 /KR0 /KRQ /SHEN C14 C15 C16 C17 C18 C19 C14-C19 470pF*6
/KR3 /KR2 /KR1 /KR0 /KRQ /SHEN
M LCDENB LP CP PNLSNS
/POFF
/POFF 470pF
M LCDENB LP CP PNLSNS
/STOP
/STOP
C7 470pF C8 470pF C9 1000pF
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CKDC CN.30P CABLE
VCKDC /SCK1 VCC HTS1 STH1 33 1 BZ1 BUZZER 2 R9 /RESETS C20 2200pF
FOR MAIN
C3 0.1uF
C4 0.1uF
/SCK1
B
VO VCC
HTS1
STH1
|LINK
CN2 D1 1SS353 BLM31*9
|DISPLAY2.SCH |KEYBOARD.SCH
VCKDC R11 2.2K R12 12K C31 0.1uF C30 10uF/16V CN10 2 1 BT CN.5267-02BLUE C33 0.1uF C32 10uF/16V
FB9 FB10 FB11 FB12 FB13 Q1 C2412K VCC FB14 FB15 FB16 FB17 VBLED PNLSNS
FLM LD3 LD2 LD1 LD0 M LCDENB LP CP
R58 180
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 LCD CN.00 6200 500 015 000 VLED
C42 10uF/16V
R57 150
C43 0.1uF
2) DISPLAY2
/S[2..9]
2/3
WMF I/F CIRCUIT
D
/S9 R63 12K R19 12K R22 12K 1 A1664 3 2 BLM21 IC3A 74LS125 /S8 Q21 KRC106S*10 4 FB2 6 5 BLM21 G9' G3' G[1'..10'] G2' G1' /S7 1 0 FB3 8 *POP UP CN(15Pin)WIRE TYPE DESIGN BLM21 IC3C 74LS125 /S6 1 3 FB4 11 12 9 G8' G7' G6' G5' G4' IC3B 74LS125 PG8 PG7 PG2 PG1 PG6 PG5 PG4 PG3 Q15 Q14 Q13 Q9 Q12 Q11 Q10 Q8 R32 220 FB1 A1664 A1664 Q7 R31 220 Q4 Q5 R29 220 R30 220 Q6 R28 220 A1664 A1664 A1664 Q16 Q2 R26 220 R27 220 R68 220 Q3 A1664 A1664 R20 12K R21 12K R24 12K R23 12K R25 12K A1664 Q17
VLED
CN4
D
VCC /X7
R65 12K
R64 12K
A1664
Q18
R66 220
R67 220
Q19
Q20
PG10
PG9
1 2 3 4 5 6 7 8 9 10 11 12 /X6 GIL-G12P-5ST2-E WMF CN
PG[1..10]
G10'
CN3
CN3A
/X5
/X4
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
DP' G' F' E' D' C' B' A' G7' PDS G6' G5' G4' G3' G2' G1'
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
G1' G2' G3' G4' G5' G6' G7' A' B' C' D' E' F' G' DP'
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
DP' G' F' E' D' C' B' A' G7' PDS G6' G5' G4' G3' G2' G1'
*IC3
VCC PDS R69 (0) C40 0.1uF
*IC4
/S5 VCC
BLM21 IC3D 74LS125
(POP UP CN.52807-1510) PDS
POP CN.53014-1510
1 C41 0.1uF FB5 3 2 BLM21 IC4A 74LS125 /S4 4 FB6 6 5 BLM21 IC4B 74LS125 /S3 1 0 FB7 8 9 C' B' A' VCC /S2 1 2 1 3 C22 C23 6 IC2F IC2E 5 IC2D C24 4 IC2C 1 4 1 5 C25 3 IC2B 1 6 C26 2 IC2A 1SS353 IC4D 74LS125 SD SC SB SA 1 7 C27 1 1 8 C28 1000pF*8 /CFSR /CFSR R33 4.7K D2 11 12 BLM21 1 3 FB8 /X0 IC4C 74LS125 BLM21 /X1 /X2 R70 0 /X3
FISCAL : PDS NORMAL : G7'
B
G7' G7'
CN9
G7' G8' G9' G10' PDS'
1 2 3 4 5
G7' G8' G9' G10' PDS'
(POP CN.52807-0510)
DP'
G'
F'
E'
D'
*IC2 : 65083 : 9Pin--GND 10Pin--NU C21 7 IC2G
1 1
A
SG SF SE
KID65083AP
A
* IC3,IC4 : 7Pin--GND 14Pin--VCC
IC2H
DP
3) KEYBOARD
3/3
VCC
R35 47K
D
KEYBOARD CN5 /S10 1 1 VCC /S11 2 2 1SS353 /RS0 3 3 1SS353 4 4 /S0 D14 1SS353 D13 1SS353 D12 1SS353
/MODR
/MODR
CKDCR
CKDCR
VCC
C34 0.1uF /S12 C38 10uF/16V /S2 /C0 SW1 5 /S3 /C1 /S3 6 6 1SS353 /C2 7 7 1SS353 8 8 /S4 D18 1SS353 D17 1SS353 D6 1SS353 /S2 5 D16 1SS353 /S0 /S1 /S2 /S3 /S4 /S5 /S6 /S4 D3: FLAT K/B NOT USE /S7 /S13 C35 0.1uF /S6 /C4 /S7 1SS353 /C5 1SS353 /S8 D22 1SS353 D21 1SS353 10 D9 1SS353 1SS353 NOT USE /S6 9 D20 9 1SS353 /S5 /C3 D8 1SS353 D3 /S5 D19 D7 D5 1SS353 /S1 D15 D4
IC5
ST0 ST1 ST2 ST3
1 2 3 4 5 6 7 8
A B C G2A G2B G1 Y7 GND
VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6
16 15 14 13 12 11 10 9
74LS138
VCC
C
/S7 D10 11 /S9 /S8 /C6 /S10 /S15 /CFSR /CFSR /S12 /S11 FLAT K/B NOT USE D25 1SS353 14 D26 1SS353 D24 1SS353 13 D11 1SS353 D23 /S8 /S9 /S10 /S11 /S12 /S13 /S14 12
IC6
10
C
11 12
1 2 3 4 5 6 7 8
A B C G2A G2B G1 Y7 GND
VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6
16 15 14 13 12 11 10 9
74LS138
13
14 15 D27 1SS353
15 /S13 16 D28 /S14 1SS353
16 17 1SS353 /S15 D29
KEX0
17 18
KEX1
18 KEY_CN_18P(5229-18CPB) KEY144
VCC VCC VCC IC8 C37 0.1uF
VCC C36 0.1uF
IC7
CN6
B
/KR2B /KR2A 47K 47K R44 R45 /KR3B /KR3A 47K 47K R42 R43 R39 R40 R41 47K 47K 47K /KR1C /KR1B /KR1A 74HC153
KET_CN_11P(5229-11CPB)
/KR0C /KR0B /KR0A
R36 R37 R38
47K 47K 47K
1 1 1 1 VCC R46 R47
1 0 1 0
9 9
8 8
7 7
6 6
5 5
4 4
3 3
2 2
1 1
B
R48 R49 R50 R51 R52 R53 R54 R55 R56
/KR0
1 2 3 4 5 6 7 8 1G B 1C3 1C2 1C1 1C0 1Y GND VCC 2G A 2C3 2C2 2C1 2C0 2Y 16 15 14 13 12 11 10 9
1G B 1C3 1C2 1C1 1C0 1Y GND
VCC 2G A 2C3 2C2 2C1 2C0 2Y
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
74HC153
/KR1 47K*11
/KR2
/KR3 / K R 1 C / K R 0 C / K R 3 B / K R 2 B / K R 1 B / K R 0 B / K R 3 A / K R 2 A / K R 1 A / K R 0 A
VCC
CN7
1 2 3 4 5 6 7 8 9 10 11
CKDCR /S1 /S2 /S3 /MODR /S4 /S5 /S6 /S7 /S8
MODE SW.CN.52011-1110
3. IPL ROM PWB
1/1
IPL-ROM RELAY PWB]
D
VCC SW301 IPL SW SLIDE SSS812-B-2B 3 2 1
CN301
VCC SLIDE SSS812-B-2B 3 CN303 VCC /HWR
SW302 IPL SW 1 2
C
VCC IC302
TO MAIN C303 0.1uF
A19 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D8 D9 D10 VCC C308 8M ROM1 10uF/16V A19 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D8 D9 D10 GND A18 A17 A14 A13 A8 A9 A11 /RD A10 /EPROM1 D15 D14 D13 D12 D11 C304 (100pF) VCC A18 A17 A14 A13 A8 A9 A11 OE A10 CE D15 D14 D13 D12 D11
45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
VCC /OPBS /HWR /IPLON0 /IPLON1 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 /RD D15 D14 D13 D12 D11 D10 D9 D8 /RASPN2 VCKDC VCKDC /EPROM1 /EPROM2 /OPBSI GND GND GND
IPL ROM FPC CN.XF2H-4515-1
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 /RD D15 D14 D13 D12 D11 D10 D9 D8 /RASPN2 VCKDC GND GND
Option RAM STACK CN.35773-4020 VCC IC303 TO RAM PWB
C305 0.1uF
A19 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D8 D9 D10 VCC C9
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
A19 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D8 D9 D10 GND 8M ROM2 10uF/16V
VCC A18 A17 A14 A13 A8 A9 A11 OE A10 CE D15 D14 D13 D12 D11
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
A18 A17 A14 A13 A8 A9 A11 /RD A10 /EPROM2 D15 D14 D13 D12 D11
C306 (100pF)
4. LCD I/F PWB

IC1 V0 V1 V4 GND FLM M LCDENB +5V O120 120 (0,0)
1/1
D
LP
121 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 138
LCD
O1 1
V0L V0L V1L V4L V5L VSS DIO2 FR DISPOFF# SHL MODE DMIN CK DIO1 VDD V5R V4R V1R V0R V0R LH1530
1 2 3 4 5 6 7 8 9 1 0
320X240 LF10036KGT
O120 120
IC2
CN201 VR201 5k
1 2 3
VR CN.53261-0390
C
O1 1 CN4 FPC 10PIN CABLE 1 IC3 LH1540 G + F M L L V V V N 5 L C P 4 1 0 D V M D E N B C11 0.1uF Y 1 1 1 2 3 4 5 6 7 8 9 0 LH1530
121 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 138 V0L V0L V1L V4L V5L VSS DIO2 FR DISPOFF# SHL MODE DMIN CK DIO1 VDD V5R V4R V1R V0R V0R 1 6 0 Y 1 6 0
C
(320X240) 1 Y 1 Y 1 6 0 D I S P E E O V V V V V V I X D D D D D D D D I S V V V V V V F 0 0 2 3 5 S O F F L C I I I I I I I I O H MD 5 3 2 0 0 R R R R R S 1 R # P K 7 6 5 4 3 2 1 0 2 L D D L L L L L 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 8 8 8 8 8 8 8 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 8 8 8 8 8 8 8 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 1 L L L L D D D D 3 2 1 0 L L L L D D D D 3 2 1 0 1 6 0 IC4 LH1540
VR PWB
D I S P E O E V V V V V V I F X D D D D D D D D I S V V V V V V 0 0 2 3 5 S O F F L C I I I I I I I I O H MD 5 3 2 0 0 R R R R R S 1 R # P K 7 6 5 4 3 2 1 0 2 L D D L L L L L
R1 R2 18
18
IC5 R3 R4 18 LD[0..3] 18
R6 OPEN
V0 V2 V3 GND +5V
B
R5 18 C4 1uF*5 VO CN1 C5 C6 C7 C8 LD[0..3]
R7 0
1 2 3 4 5 6 7 8 9 10 CP LP LCDENB M
NC VIN3 V3 RX4 RX3 RX2 V4 NC VEE NC
NC VCC NC V2 VIN2 RX1 V1 STR VREF NC
20 19 18 17 16 15 14 13 12 11
B
C2 0.1uF C3 0.1uF
R8 0
LA5312V
R9 OPEN
R10 0 C1 1uF
VO C9 4.7uF/50V
IC6
2,3 6,7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 LCD CN(15P)ELCO 00-6200-157-032-800
VO +5V FLM LD3 LD2 LD1 LD0 GND M LCDENB LP CP GND VBLED
C10 1uF/50V
R11 240
A
CN3 1 2 3 CN2 1 2 LED CN.53261-0290 VR CN.53261-0390
LM317L
5,8Pin:NU
R13 2.2k
R12 3k
5. POP UP DISPLAY PWB
1/1
DIG7' DIG4' DIG3' DIG2' DIG1'
DIG6'
DIG5'
FND4
1 4 FND3 FND2 1 4 FND1 1 4 1 3 1 3
1 3
1 4
1 3
CN1
4 1 1 1 2 3 1 1 9 7 1 5 6 8 1 1 4 1 1 1 2 3 1 1 9 7 1 5 6 8 1 1 4 1 1 1 2 3 1 1 9 7 1 5 6 8 1 1 4 1 1 1 2 3 1 1 9 7 1 5 6 8 1 1 7 8 5 6 2 0 1 7 8 5 6 2 0 1 7 8 5 6 2 0 1 7 8 5 6 2 0 1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 POP UP CN.CABLE(15P)
R10 27
R12 27
R14 27
R16 27
R18 27
R20 27
R22 27
R24 27
DP'
G'
F'
E'
D'
C'
B'
A'
8
VCC
1/4
1 PLLVCC R71 R70 3k 200 C42 1 1 2 3 4 1 2 3 4 0.1uF 1 18pF LD[0:7] (C4) BR3 2 18pF LD1 LD2 2 LD3 0.1uF HD[0:7] LD4 LD5 LD6 33*4 LD7 VCC BR5 H H H HH D D D DD 0 1 2 3 4 1 2 3 4 C5 C6 C7 C8 1 1 1 1 100pF*8 2 BR6 2 2 2 2 2 2 2 C9 1 C10 1 C11 1 C12 1 10k*4 8 7 6 5 H H H D D D 5 6 7 HD4 HD5 HD6 HD7 1 2 3 4 8 7 6 5 BR4 33*4 C43 1 LD0 HD0 HD1 HD2 HD3 1 2 3 4 8 7 6 5 1 VCC R7 680 X1 5MHz CSTCR 2 (C3) 2 PLLVSS BR1 10k*4 BR2 10k*4 C41 470pF 8 7 6 5 8 7 6 5 2
6. TCP/IP INLINE I/F PWB 1) CPU
VCC
(R5)
10k
R4
10k
R75 10k
R76 10k
(R6) 10k
R3 10k
R2 10k
R1
10k
/LRES 8 8 8 8 8 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 5 5 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 IC1 RP P E A L S 1 L 5 V / S CS K P L L C A P 1 2 3 4 10k*4 HD12 8 7 6 5 P MMV NME MX V D D D D D V D D D V DD D D L D DC MD X D T S 0 1 2 3 4 C 5 6 7 S 8 9 1 1 0 1 S C L 0 1 C I 2 T 3 A S L A V L C C
H H HH D D DD 8 9 1 1 0 1
PLLVSS
VCC
C
HD13 HD14 HD15 BR17 10k*4 8 7 6 5 1 2 3 4
BR11
1 2 3 4
10k*4 8 7 6 5
/RTS1 /DTR1 /DCD1 /CI1 /DSR1
RXD1 TXD1 /CSDPRAM /CS3 1 2 3 4 BR18 10k*4 VCC BR7 10k*4 8 7 6 5 8 7 6 5
R138 10k 1 2 3 4 BR12 1 2 3 4 BR13
8 7 6 5 10k*4 8 7 6 5 10k*4
CPU
VCC
R139 /MWE
10k
SH7014
/CS0 /CS1
/CTS1
8 7 6 5 BR8 10k*4 BR9 10k*4
8 7 6 5 BR10 10k*4
8 7 6 5 R132 10k R133 10k
R73
10k /MRD
1 2 3 4 LA19 LA18 VCC R15 10k
10k R74 8 7 6 5
1 2 3 4
1 2 3 4
1 2 3 4
1 2 3 4
BR14 10k*4
85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112
PE0/TI0C0A/DREQ0 PE1/TIOC0B/DRAK0 PE2/TIOC0C/DREQ1 PE3/TIOC0D/DRAK1 PE4/TIOC1A VSS PF0/AN0 PF1/AN1 PF2/AN2 PF3/AN3 PF4/AN4 PF5/AN5 AVSS PF6/AN6 PF7/AN7 AVCC VSS PE5/TIOC1B VCC PE6/TIOC2A PE7/TIOC2B PE8 PE9 PE10 VSS PE11 PE12 PE13
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
LA[0:17]
/SRREQ R136 10k 10k IOCHRDY LA19 LA18 R131
/SWREQ
LA0 LA1 LA2 LA3 LA4 LA5
LA0 LA1 LA2 LA3 LA4 LA5
B
VCC 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 R8 1 C39 100pF 2 2 10k 1 C40 100pF CPU_SH7014
/HRACK
/HWACK
P E 1 4 / D A C K 0 / ~ A H P B 2 / P ~ E I 1 R 5 Q / 0 D / A ~ A A A A A A A V A V R C V K S A A A A A A A A A A 1 1 1 1 1 1 1 C 1 S A 1 S 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 C 7 S S
P B 3 / ~ I R Q 1 / ~ C A S L P B 4 / ~ I R Q 2 / ~ C A S H
D12 VSS D13 D14 D15 PA0/RXD0 PA1/TXD0 PA2/SCK0/DREQ0/IRQ0 PA3/RXD1 PA4/TXD1 PA5/SCK1/DREQ1/IRQ1 PA6/TCLKA/CS2 PA7/TCLKB/CS3 PA8/TCLKC/IRQ2 PA9/TCLKD/IRQ3 CS0 CS1 VSS WRL VCC WRH WDTOVF RD VSS PB9/IRQ7/A21 PB8/IRQ6/A20/WAIT PB7/A19 P PB6/A18 B 5 / ~ I R Q 3 / R V D SW S R
/RSTDRV
LA6 LA7 LA8 LA9 LA10
LA6 LA7 LA8 LA9 LA10 LA11 LA12 LA13 LA14 LA11 LA12 LA13 LA14 LA15 LA16 LA15 LA16 LA17 LA[0:17] LA17
VCC LA[0:17] VCC
R121
10k
R72 10k
L L L L L L L L L L L L L A A A A A A A A A A A A A 0 1 2 3 4 5 6 7 8 9 1 1 1 0 1 2 /INTLAN /INTHR /INTHW R130 10k
L A 1 3 L A 1 4 L A 1 5 L A 1 6 L A 1 7
R141 470 1 C1 0.1uF 2 C2 10uF
D4 LED
WP#
VCC
Q1 KRC106S
PE12
SW1 /CSEPROM 3 6
R69 10k R129 10k
A
2 5 /CS0
/CSFLASH
C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 100pF*18 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 C21~38 2 2 2
/CS3
4 /CSFLASH
/CSLAN
2) LAN CONTROLLER
2/4
VCC
D
(D1) (D2) (D3) LED (R106) 1k LED (R105) 1k LED (R104) 1k
(R103) 10k
R91 (R92) (R93) (R94) (R95)
(R96) (R97) (R98) (R99) (R100) (R101) (R102) T1 VCC
TPOUT+
TX+
C54 1 TPOUT18pF CN3 C55 1 18pF TPIN+ RX+ 2 R147 1M X2 20MHz MA406 2 TX-
C
8 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 IC6 T P I N + T V R R C C GX P D X X D D N 2 I D + - + - D N -
VCC
1 2 3 4 5 53261-0590
(R82) (R83) R89 R90 270 270
B D 4 ( I R Q S 2 ) R115 200
L E D B N C
(R84) (R85) VCC
B D 5 ( I R Q S 1 ) ( E E S K )
B D 6 ( I R Q S 0 ) ( E E D I ) B E B B B B B V B B B B J A L L L D E C A A A A D A A A A P U E E E 7 C S 1 1 1 1 D 1 1 2 2 I D D D ( S B 4 5 6 7 8 9 0 1 2 1 0 ( ( ( ( ( ( ( ( ( ( P L P B B B B B P L L L 1 L S S S S S N E E E ) 0 4 3 2 1 0 P D D D ( ) ) ) ) ) ) ) E T R C E X X O D ) ) L O ( ) ) L ( E L D E D C R L S I ) N K ) 1 C56 0.01uF R142 10k IOCHRDY /CSLAN R88 10k 1 RSTDRV R86 R87 2 10k 10k C88 100pF 2
TPIN-
RX-
BR15
1 2 3 4
10K*4 8 7 6 5
LD15 LD14
78Z034C
1 1 C57 0.01uF 2 C59 0.01uF 2
1 C58 0.01uF 2
1 2 3 4
8 7 6 5
LD13 LD12 LD11 LD10 LD9 LD8
R81 RSTDRV
27k
BR16
10K*4
LAN CONT
LD7 LD6 LD5 LD4 LD3 LD2 LD1 LD0 IOCHRDY
VCC
(R125) (R126) (R127) (R128)
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 BD3(IOS0) BD2(IOS1) GND BD1(IOS2) BD0(IOS3) GND SD15 SD14 VDD SD13 SD12 SD11 SD10 SD9 SD8 IOCS16B(SLOT16) INT7(IRQ15) INT6(IRQ12) INT5(IRQ11) INT4(IRQ10) X1 TX+ TXVDD TPOUTTPOUT+ GND SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 IOCHRDY AEN RSTDRV SMEMWB SMEMRB
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
C53 10uF S A 1 2 S A 1 4 S A 1 8 S I I A GO O 1 N RW 9 D B B RTL8019AS S A 1 5 S A 1 6 S A 1 7 S A 1 3
C52 0.1uF
2 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0
I N T 3 ( I R Q 5 )
I N T 2 ( I R Q 4 )
I N T 1 ( I R Q 3 )
I N T 0 ( I R Q S S 2 / S V S S S S S S S GS S V A A 9 A D A A A A A A A N A A D 1 1 ) 0 D 1 2 3 4 5 6 7 D 8 9 D 0 1
VCC INT0 L A 0 L L L L L L L A A A A A A A 1 2 3 4 5 6 7 L L A A 8 9 L A 1 0 L A 1 1 L A 1 2 L A 1 3 L A 1 4 L A 1 5 L A 1 6 L A 1 7 L A 1 8 L A 1 9 /MWE /MRD LA[0:19] LA[0:19] (R123) R122 (R124)
A
LD[0:15] LD[0:15]
3) MEMORY 3/4
LA[0:18]
LA[0:18]
LD[0:7]
LD[0:7]
VCC SA[0..9] VCC 1 1 C51 10uF SW2 3 2 1 SA11 SA10 IC3 1 2 LA15 LA17 C95 0.1uF IC4 IC5 C50 0.1uF 2 C48 0.1uF 2 C46 0.1uF 2 VCC VCC
/WR
/CER
R143 10k /CSDPRAM C89 100pF C47 10uF 1 C49 10uF
VCC
/MWE
/MRD
/MRD
L A 0
L A 1 0
L A 1 1
5 5 5 4 4 4 7 6 5 4 3 2 1 2 1 0 9 8 7
IC2
A / A ANR / V / RN A A 0 O1 1 / / CCC / C 1 1 L E 0 1 CWE C EW 1 0 R R RR L L L L L /RD LA10 LD7 LD6 LD5 LD4
C
R140 10k
32 31 30 29 28 27 26 25
LA18 LA17 LA14 LA13 LA8 LA9 LA11 /MRD LA10 24 23 22 LD0 LD1 LD2 13 14 15 D0 D1 D2 16 GND D7 D6 D5 D4 D3 21 20 19 18 17
DUAL PORT RAM LD3 LD2 LD1 LD0 /MRD
LA16 LA15 LA14 LA13 LA12 LA11 LA9 LA8 /MWE /LRES
LA16 LA15 LA12 LA7 LA6 LA5 LA4 LA3 LA2 LA1 LA0
1 2 3 4 5 6 7 8 9 10 11 12
IDT7134JPLCC
LA1 LA2 LA3 LA4 LA5 LA6 LA7 LA8 LA9 LD0 LD1 LD2 LD3 46 45 44 43 42 41 40 39 38 37 36 35 34 HY628100BLLG 1M SRAM /CS1 /MRD /MWE 1 2 2 WP# /LRES 1 C93 100pF WP# LA18 LA7 LA6 LA5 LA4 LA3 LA2 LA1 LA0 /RD SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9
8 9 10 11 12 13 14 15 16 17 18 19 20
A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L I/O3L
/OER A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R N/C I/I7R
LA16 LA14 LA12 LA7 LA6 LA5 LA4 LA3 LA2 LA1 LA0 LD0 LD1 LD2 /MWE LA13 LA8 LA9 LA11 /MRD LA10 /CS1 LD7 LD6 LD5 LD4 LD3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS VCC A15 CS2 WE A13 A8 A9 A11 OE A10 CS1 I/O8 I/O7 I/O6 I/O5 I/O4
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VPP VCC A16 A18/PGM A15 A17 A12 A14 A7 A13 A6 A8 A5 A9 A4 A11 4M A3 A2 OE EPROM A1 A10 A0 CE
C
LD7 LD6 LD5 LD4 LD3 4M EPROM
VCC
I / O 4 L LH28F004BVT
I / O 5 L
I / O 6 L
I I / / ONGO 7 / N 0 L CDR
I / O 1 R
I / O 2 R
I I / / OO 3 4 RR
I / O 5 R
I / O 6 R
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A16 A15 A14 A13 A12 A11 A9 A8 WE# RP# VPP WP# A18 A7 A6 A5 A4 A3 A2 A1 A17 GND NC NC A10 DQ7 DQ6 DQ5 DQ4 VCC VCC NC DQ3 DQ2 DQ1 DQ0 OE# GND CE# A0
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
1 C90 100pF
C45 10uF S D 7
C44 0.1uF
2 2 2 2 2 2 2 2 2 3 3 3 3 1 2 3 4 5 6 7 8 9 0 1 2 3
4M FLASH ROM
L L L L DDDD 4 5 6 7
S S S S S S S D DDDDDD 0 1 2 3 4 5 6
1 2
VCC VCC
SD[0..7] SD[0:7]
C94 100pF
R144 10k /CSFLASH /CSEPROM 1 C91 100pF
R145 10k /CSEPROM 1 2 C92 100pF 2
8
VCC
4) LOGIC
SA[0..15] SA[0..15] IC13B SA15 SD[0..7] SA13 5 3 2 74HC32 74HC08 R D Q VCC PLLVCC /LRES 1 74HC74 CP 6 3 D S D Q 74HC00 2 5 SA13 5 1 6 4 6 4 IC9A IC11A SA15 4 IC12B SD[0..7] /INTSW1
4/4
VCC /LRES (R79) 0 IC12C IC12D 9 8 11 13 74HC32 74HC32 PLLVSS /LRES /INTSR1 /INTSW1 (R80) 0 10 11 /RD C87 10uF /RD 12 12
CN1
1 0 D CP R D 1 3 Q S D Q
IC9B 9
SA15 SA14 SA13
/DPCS /WR
SA11 SA10 /INTSR1 /INTSW1
SA7 SA8 SA9 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0
8 74HC74
/INTHR
/RD
/HRACK
C86 100pF
/SWREQ
SA0 SA1 SA2 SA3 SA4 SA5 SA6
C
1 C84 0.01uF IC14C /DPCS 8 1 3 2 74HC32 74HC32 /WR 10 /WR /DPCS 9 IC14A 2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
CON40P
C
4 2 3 D CP R D IC11B 4 6 5 74HC08 /HWACK 1 74HC74 Q 6 /INTHW S D Q IC10A 5
C83 100pF
C85 100pF
IC13C 9 8 SA14 SA14 10 5 74HC00 74HC32 4 6 11 IC14B 12 D CP
1 0 S D Q
IC10B 9
B
/INTSR1 RSTDRV
R D 1 3
8 74LV7HC
IC13A
/RSTDRV
/LRES
/SRREQ
74HC00 IC13D 12 INT0 13 74HC00 R146 4.7k 11 /INTLAN
[IC9]
VCC
[IC10]
VCC
[IC11]
VCC
[IC12]
VCC
[IC13]
VCC
[IC14]
VCC
IC12A /CER
/DPCS
SA13
74HC32
1 C76 0.1uF 2
1 C80 0.1uF 2
1 C78 0.1uF 2
1 C79 0.1uF 2
1 C82 0.1uF 2
1 C81 0.1uF 2
A
IC11D 12 11 13 13 12
IC14D 11
A
===NOTE===
74HC32
IC11C
10 74HC08
74HC08
*IC9,10,11,12,13,14 7Pin : GND 14Pin : VCC
CHAPTER 9. PWB LAYOUT
1. MAIN PWB 1) A side
R : VRD-RC2EY103J is added (IC1 94pin - R71)
Symbol/PartsCod) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
2) B side
2. CKDC PWB
3. DISPLY & MCR PWB 1) A side
2) B side
4. RS232 RELAY PWB 1) A side
2) B side
5. IPL ROM PWB 1) A side
2) B side
6. TCP/IP RELAY PWB
7. VR PWB
8. POP UP DISPLY
9. LCD I/F PWB
10. TCP/IP I/F PWB

A side
B side
Symbol/PartsCod) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
COPYRIGHT 2001 BY SHARP CORPORATION

All rights reserved. Printed in Japan. No part of this publication may be reproduced, stored in a retrieval system, or transmitted. In any form or by any means, electronic, mechanical, photocopying, recording, or otherwise, without prior written permission of the publisher.
SHARP CORPORATION Digital Document Systems Group Quality & Reliability Control Center Yamatokoriyama, Nara 639-1186, Japan
2001 July Printed in Japan

Sharp UP-700 Cash Register SM

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Sharp UP-700 Cash Register SM

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SERVICE MANUAL

2) KEY TOP NAME

PAGE UP PAGE DOWN CANCEL

Drawer Drawer lock

RFND SERV# RCPT TAX SHIFT VOID

Power switch Rear cover

PLU/SUB (D-PLU) 1 to 100 P.SHIFT# AUTO1, 2

Stand-by : 16 W Operating : 57 W (max.) 0 to 40 C

95 81 68 RCPT SERV # PAGE UP

RFND CANCEL LEVEL CONV # #

# PLU/ SUB CHK # CH # SBTL

TAX SHIFT GLU SRVC FINAL CA/AT

PAGE 27 DOWN ENTER

3) TEST PROGRAMMING KEY SHEET LAYOUT

4) BLANK KEY SHEET LAYOUT

Screen example 2 (PGM mode)

4. KEYS AND SWITCHES

OP X / Z OFF PGM1 PGM2

MGR X1 /Z1 X2/Z2

Manager key (MA)

Submanager key (SM)

Screen save mode

Operator key (OP)

2) DISPLAY ADJUSTMENT (OPERATION DISPLAY)

Service key (SRV)

3) CUSTOMER DISPLAY (Pop-up-type)

2) DRAWER LOCK KEY

4) PRINTER COVER LOCK KEY

360 dots 360 dots 0.125 mm 0.125 mm

Max. 30 characters Max. 30 characters At 10 x 24 dots 1.5 mm 3.75 mm

Item Printing format 12 x 24 font

1) PORT 1 (CH1) (CN402)

2) PORT2 (CH2) (CN403)

/CD RD SD /ER GND /DR /RS /CS VCC(+5V) S401 /CI

/RS /ER SD GND RD /DR /CS

S403 GND VCC (+5V)

3) OPTIONAL DEVICES THAT CAN BE CONNECTED

D-sub 9pin 7 4 3 1 5 2 6 8 9 /RS /ER SD /CD GND RD /RS /CS /CI

RS-232 Communication Master machine Std. 2/ Max.4 ports PC <Local purchase>

RS-232 Board ER-A5RS <Option>

Remote printer/Slip <Local purchase>

Pole Display <Option> UP-P16DP

Expansion memory board <Option> UP-S02MB UP-S04MB

Hand Scanner ER-A6HS1 Laser Scanner <Local purchase>

Remote Drawer <Option> ER-03DW/ 04DW

Coin Dispenser <Local purchase> MCR <Option> UP-E13MR

3. LOCAL PURCHASE OPTIONS

1: Please consult with your Sharp regional sales manager.

7. HOW TO USE SERVICE TOOLS

UP-700 Expansion PWB (CKOG-6708RCZZ) A ER-A5RS PWB

Loop back connectors UKOG-6705RCZZ

CHAPTER 3. SERVICE PRECAUTION

When IPL writing is required because of a change in the software.

IPL from PROM Version check Erase

IPL write start

3) IPL FROM P-ROM

2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F Verify Completed. IPL write completed

10. Perform one of the master reset procedures.

2. UP-700 UTILITY TOOLS

D-SUB 9pin - modular RJ-45 conversion cable

RS232 Cable Connecting:

D-sub 9pin /RS /ER SD /CD GND RD /DR /CS /CI

Service ROM Check PASS!!(or ERROR!!) APL: 27801R** 27801R IPL: