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VLSI hys|ca| Des|gn (8ackend, ASIC)


8r|ef Sy||abus

Module 1
lnLroducLlon Lo vLSl 8aslcs
1. lundamenLal concepLs of MCSlL1 and CMCS operaLlons
2. 8aslc dlglLal ClrculL and layouL
3. lnLroducLlon of labrlcaLlon 1echnologles
4. CMCS labrlcaLlon

Module 2
lnpuLs Lo hyslcal ueslgn
1. Llbrary flles
2. 1echnologlcal flles
3. neLllsL
4. lC consLralnLs
3. Synopsys ueslgn consLralnLs (SuC)
6. ulfferenL LuA Lools and lLs flle formaLs

Module 3
arLlLlonlng
1. Why parLlLlonlng
2. ueslgn arLlLlonlng and lLs advanLages
3. ulfferenL Lypes of parLlLlonlng
4. MeLhods of parLlLlonlng
3. arLlLlonlng based upon Loglcal Croups
6. arLlLlonlng based upon Clock Croups

Module 4
lloor plannlng
1. Why floor plannlng?
2. Coals of floor plannlng
3. lloor plannlng based on l/C ConsLralnL llle




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4. AspecL 8aLlo
3. l/C Core clearance
6. lllp, AbuL
7. uouble back
8. CongesLlon Analysls

Module 3
ower plannlng
1. Why power plannlng
2. varlous meLhods
3. ower mesh
4. Core power 8lngs
3. Macro ower 8lng
6. SLraps and Lrunks

Module 6
lacemenL
1. WhaL ls placemenL/ Coals & Cb[ecLlves
2. 8aslcs of lacemenL
3. lnpuLs / CuLpuLs
4. lacemenL llow/ lacemenL sLeps
3. lacemenL ConsLralnLs
6. re place opLlmlzaLlon,
7. Pln SynLhesls,
8. ln placemenL,
9. Search and reflne,
10. osL placemenL opLlmlzaLlon before C1S 8e synLhesls,
11. llx SeLup, llx hold
12. Scan chaln
13. lssue wlLh Lhe Scan chaln
14. SoluLlon Lo Lhe Scan chaln
13. lssues ln lacemenL
16. CpLlmlzaLlon 1echnlques
17. llnal checks







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Module 7
Clock Lree SynLhesls
1. WhaL ls C1S, Coals & Cb[ecLlves?
2. Cb[ecLlve of C1S
3. lnpuLs / CuLpuLs
4. CpLlmlzaLlon procedures
3. 8uffer slzlng
6. 8elocaLlon
7. llx hold
8. osL placemenL opLlmlzaLlon afLer C1S

Module 8
8ouLlng
1. WhaL ls 8ouLlng?
2. ulfferenL Lypes of 8ouLlng
3. 1lmlng drlven 8ouLlng
4. CongesLlon drlven 8ouLlng
3. neL consLralnLs
6. Clobal 8ouLe
7. 1rack asslgnmenL
8. ueLall 8ouLlng
9. Search and reflne
10. osL 8ouLe CpLlmlzaLlon

Module 9
Slgnal lnLegrlLy
1. Sl Analysls
2. Cross Lalk delay
3. CllLch analysls
4. l8 urop
3. LlecLro mlgraLlon
6. Cround 8ounce
7. AnLenna vlolaLlons








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Module 10
1lmlng
1. Why 1lmlng Analysls
2. WhaL ls S1A?
3. ros & cons of S1A
4. erformlng Analysls
3. 1lmlng verlflcaLlon & Corners
6. SeLup & Pold 1lmlng
7. LsLlmaLlng 8C values
8. Wlre load Models
9. neL and cell uelay CalculaLlon
10. Clock Skew
11. 1lmlng paLhs and arcs
12. ConsLralnLs
13. Source and neLwork LaLency
14. !lLLer
13. Pold check
16. l/C ConsLralnLs
17. lnpuL & CuLpuL delay

Module 11
hyslcal verlflcaLlon
1. osL layouL verlflcaLlon
2. u8C
3. L8C
4. LvS
3. LL/8L


re requlslLes
8ranch: LlecLronlcs and communlcaLlons/1elecommunlcaLlons/LlecLrlcals
CandldaLes are expecLed Lo know Lhe baslcs of Lhe Loglc deslgn and analysls, ClrculL
analysls.
L|nux: user level
ScrlpLlng (noL mandaLory)
Cood analyLlcal skllls