LECTURE 3

XNOR

XOR

Graphical approach to find the PMOS network

Implement the logic function

Each NMOS transistor is represented by an arc connecting the source and drain nodes of the transistors and is labeled with the logical input variable.

Graphical approach to find the PMOS network

Placing a new node inside of every enclosed path Two exterior nodes are needed: one representing the output and one representing VDD

Graphical approach to find the PMOS network

New arcs cut through the NMOS arcs and connect the pairs of nodes that are separated by the NMOS arcs has the same logic label as the NMOS arc that is intersected minimum PMOS logic network only one PMOS transistor per logic input.

Graphical approach to find the PMOS network

Final CMOS circuit

Whats the logic function ?

internal node capacitance of the pull-down stack

the case where both inputs transition go low (A = B = 10) results in a smaller delay

PASS TRANSISTOR LOGIC

NMOS Transistors in Series/Parallel

Primary inputs drive both gate and source/drain terminals NMOS switch closes when the gate input is high
A X A B X = Y if A or B Y B Y X = Y if A and B

Remember - NMOS transistors pass a strong 0 but a weak 1

PMOS Transistors in Series/Parallel

Primary inputs drive both gate and source/drain terminals PMOS switch closes when the gate input is low
A X A B X = Y if A or B = A B Y B Y X = Y if A and B = A + B

Remember - PMOS transistors pass a strong 1 but a weak 0

Pass Transistor (PT) Logic

B A 0 B F A B 0 F B

Gate is static a low-impedance path exists to both supply rails under all circumstances N transistors instead of 2N No static power consumption Ratioless Bidirectional (versus undirectional)

VTC of PT AND Gate

B
1.5/0.25 Vout, V 0.5/0.25
2

B=VDD, A=0VDD
1

0.5/0.25

B 0
0.5/0.25

F= AB
0 0 1

A=VDD, B=0VDD A=B=0VDD

2

Pure PT logic is not regenerative - the signal gradually degrades after passing through a number of PTs (can fix with static CMOS inverter insertion)

Differential PT Logic (CPL)

A A B B A A B B B A B A B AND/NAND B A

PT Network F

Inverse PT Network

B A

F=AB F=AB

B A B OR/NOR

F=A+B F=A+B

A A A

F=AB F=AB
XOR/XNOR

Why not do the same with all pfets??

CPL Properties
Differential so complementary data inputs and outputs are always available (so dont need extra inverters) Still static, since the output defining nodes are always tied to VDD or GND through a low resistance path Design is modular; all gates use the same topology, only the inputs are permuted. Simple XOR makes it attractive for structures like adders Fast (assuming number of transistors in series is small) Additional routing overhead for complementary signals Still have static power dissipation problems

Transient Level Restorer Circuit Response

3
W/Ln=0.50/0.25 W/L1=0.50/0.25 W/L2=1.50/0.25

2
Voltage, V W/Lr=1.75/0.25

node x never goes below VM of inverter so output never switches

W/Lr=1.50/0.25

W/Lr=1.25/0.25 W/Lr=1.0/0.25

0 0

100

200

Time, ps

300

400

500

Restorer has speed and power impacts: increases the capacitance at x, slowing down the gate; increases tr (but decreases tf)

 Technology solution: Use (near) zero VT devices for the NMOS PTs to eliminate most of the threshold drop (body effect still in force preventing full swing to VDD)
low VT transistors
In2 = 0V A = 2.5V

Solution 2: Multiple VT Transistors

on
Out

In1 = 2.5V

B = 0V

off but leaking

sneak path

Impacts static power consumption due to subthreshold currents flowing through the PTs (even if VGS is below VT)

Solution 3: Transmission Gates (TGs)

Most widely used solution

A

C
A

C B C

B C

C = GND A = VDD C = VDD B A = GND

C = GND B C = VDD

Full swing bidirectional switch controlled by the gate signal C, A = B if C = 1

Resistance of TG
30 25 20

W/Lp=0.50/0.25 0V Rn 2.5V Rp Rn 2.5V Req W/Ln=0.50/0.25 Rp Vout

Resistance, k

15 10 5 0 0 1 2

TG Multiplexer
S S F

S
VDD

In2 S In1 S F = !(In1 S + In2 S)

GND In1 S S In2

How does this compare to a static complementary multiplexer?

Transmission Gate XOR

weak 0 if !A on off A on off 0 B 1 A !B AB B !A weak 1 if A an inverter

TG Full Adder
Cin B

Sum

Cout

Differential TG Logic (DPL)

B A
GND

A A

F=AB

B A B A

F=AB

B
GND VDD

A
VDD

F=AB

B A B

F=AB

B AND/NAND

XOR/XNOR