BUS

Bus Clock Pulse

System Bus

Introduction
Data Transfer Rate Peripheral Devices

Components of the System Bus & Attached Devices

Operation of the Bus

1. Module send data (Transfer data via Bus) 2. Module request data ( Must wait for second module to send data)

Internal Bus

Bus located within CPU chip for communications

External Bus

Supported by third-party hardware and software and more likely to adhere to one of a number of industry standards for buses

System Bus consist common set of parallel wires 1. Address Buses (Frequently transfer address from program counter) 2. Data Buses (Carry data, instructions and addresses between main MEM and ALU) 3. Control Buses (Carry signals from control unit to other components of CPU and back to Control Unit)

Physical Realization of Bus Architecture

High Performance Bus

Main Memory
Processor Cache/Bridge

Local Bus

System Bus

SCSI

P139 4

Graphic

Video

LAN

High Speed Bus

FAX

Expansion bus interface

Modem

Serial

Expansion Bus

Bus Hierarchy
1) The Processor Bus (System Bus)
2) a) Highest level bus that chipset uses The Cache Bus (Backside Bus) a) High level architecture b) Conventional processors using 5th generation motherboards; cache connected to standard memory bus. The Memory Bus a) 2nd level bus that connects the memory subsystem to the chipset The Local I/O Bus (High-speed I/O Bus) a) High-speed input/output bus used for connecting b) Common is VLB & PCI The Standard I/O Bus a) Used for slower peripherals and older devices b) ISA (Industry Standard Architecture) bus

3) 4)

5)

Diagram of Various Buses that connects to the CPU

System Memory
Level 2 Cache
Memory Controller

CPU
Graphics Card ISA Devices

R A M

R A M

R A M

R A M Bus Bridge

Frontside (System) Bus

AGP Chipset

PCI BUS Bus Bridge PCI Devices

Characteristics of Bus
Data & Address Bus Data bus (Lines that carry data) Address bus (Set of lines that carry information about where memory the data is transferred) Control bus(How the bus functions) Bus Width Wider bus , more information flow Width of bus dictates No of memory locations that bus can transfer information to/from ISA - 16bits VLB/PCI - 32 bits

Bus Speed Speed of bus , Bits of information sent across AGP buses move 2 bits of data per clock cycle Older buses like ISA have two clock cycles to move 1 Bit

Bus Bandwidth Total amount of data can theoretically be transferred on a bus in given time Measured in bits per second / bytes per second Bandwidth= bus width X bus speed Slow bus bandwidth = (bus width X bus speed)

Performance of a Bus:1) Transfer Time a) Amount of time taken to be delivered b) Transfer time defines how long a processor will have to wait when it fetches an instruction from memory 2) Bandwidth a) Units bits per second measure the capacity of bus b) Can be transferred in parallel in one transaction c) 32 data lines deliver 1,000,000 packets per second , it has bandwidth of 32Mbps

System board of integrated technologies on it (ISA,PCI,AGP)

ISA slots are the black slots on lower portion of the board in the image

System Board

Micro Channel Architecture MCA(Micro Channel Bus) MCA(Micro Channel Architecture) Introduced in 1987 Extended Industry Standard Architecture (EISA) Bus Never became widely used and cannot be considered an industry standard. Industry Standard Architecture Common bus in PC world Industry Standard Architecture Standard = Actually fits Many devices for which ISAs speed is more than sufficient and will be standard modems

BUS STANDARDS
VESA Local Bus(VLB) 1st to gain popularity Introduced in 1992 To improve video performance in PCs Peripheral Component Interconnect (PCI) Local Bus Most popular local I/O bus By Intel in 1993 Geared to 5th and 6th generation systems

Accelerated Graphic Port Developed in response to the trend towards greater performance requirements for video. Increase bandwidth between main processor and video subsystem

PCI Bus Performance

BURST MODE(Transfer information in burst mode where after an intial address is provided in multiple sets of data

BUS MASTERING(PCI supports full bus mastering which leads to improved performance)

HIGH BANDWIDTH OPTIONS(Specification version 2.1 calls for expandability to 64bits and 66 MHz speed