Power Distribution in VLSI Systems

Madhav P. Desai February 2, 2011

The Problem

Consider the system schematic in Figure 1. An ideal voltage source is providing power to two subsystems (modules) G1, G2. The module G1 is charging a load capacitance C , and the charging current is approximated by a triangular pulse which takes the dotted path shown in the gure. Let Ipeak and (dI/dt)peak be the peak values of current and rate of change of current for the charging current. Further, assume that the charging is repeated with a frequency of fclk , so that dd the average current drawn by G1 is Iavge = fclk CV . 2 The ow of current in the loop implies that (V (A) V (P ))peak = Ipeak Rdd + (dI/dt)peak Ldd and (V (Q) V (B ))peak = Ipeak Rss + (dI/dt)peak Lss and (V (P ) V (Q))average = Vdd (Rdd + Rss )Iavge (3) so that during operation, the eective voltage seen across G1 and G2 is lowered (this lower eective voltage has a lower average value as well as transients). If G2 contains memory elements, then this lowering of voltage at G2 may lead to errors such as loss of stored data. Also, the perturbation seen at points P, Q may ow through to the output R of G2. Thus, the switching currents in the system during operation of G1 can aect the voltage seen by itself and by other modules (such as G2) which share a common supply network with it (this is termed common-rail coupling). The power distribution problem is then to ensure that during system operation, no module malfunctions due to these disturbances. The disturbance can be related to insucient voltage values across a module, or a violation of noise margins at a gate output. (2) (1)

Decoupling Capacitance, a partial solution

Suppose that we connect a capacitor of value CD = 100C across the terminals P and Q (assume that the wires used to connect the capacitor are short and have 1

negligible inductance and resistance). Then if we assume that CD supplies the entire charge for the charging of C , the maximum perturbation in V (P ) V (Q) will be limited to CVdd /(C + CD ) or about 0.01Vdd. Thus, the maximum drop across the wire resistance and inductances in the distribution network will be limited to 1% of the supply voltage Vdd . However, the average value of V (P ) V (Q) will still be as in Eq. 3. Thus, it appears that if Rdd , Rss are chosen to be small enough so that the average supply voltage seen at the modules is large enough, then the use of decoupling capacitance seems to sort out the noise problem due to common-rail coupling. Unfortunately, this is not quite true. Consider the circuit in Figure 2. Module G1 is driving a load capacitance in module G3. A decoupling capacitance has been placed across every module. However, the potential circular paths of the charging current (shown as dotted lines) are such that the transients are forced to ow through power supply wire inductances and resistances. Thus, decoupling capacitance is not a complete solution to the problem. This problem can be alleviated somewhat if you use suitable techniques for signaling.

Signaling techniques to make power distribution easier

Suppose that you wish to transfer data at a rate of 1Gbps between two parts of the system. Then there are several choices 1. Use a single wire to transmit the information at the required rate. The value of tR would be of the range of 250ps. In addition, provide a return path wire so that the you have a low-inductance path for the forward signal. 2. Use N+K wires to transmit the information, with each wire sending information at 1/N Gbps (the K additional wires are used to provide a low-inductance return path). The value of tR for each wire would be N 250ps. 3. Use low-swing dierential signaling using matched drivers, wires and receivers. 4. Use optical signaling. Of these, the rst choice is economical, but the second choice can substantially reduce power supply noise (because tR is increased). Dierential signaling1 can in principle eliminate the noise problem because the dierential pair itself provides a return path for the forward current without involving the supply network. Optical signaling has signicant cost issues and is used as an absolute last resort.
1 Needs

to be well matched to provide these benets. Also harder to design and implement

Power planning

In addition to the use of decoupling capacitance, a designer needs to ensure that the total noise injected into the system through common-rail coupling is within limits. Suppose that Gi and Gj are two modules (each of which is individually decoupled). Let Rij and Lij be the supply loop inductance and resistance for a current path taken by the charging of a capacitance in module Gj from Gi . Also, let Cij denote the amount of capacitance in Gj being charged from Gi . Then, the amount of noise injected into the supply network due to Gi driving Gj is 2Cij Vdd 4Cij Vdd Dij = Rij + Lij (4) tR t2 R The goal of the designer is to ensure that the peak noise in the system is within limits. The peak noise is calculated by using Eq. 4 together with an understanding of the worst-case scenario in which as many parts of the system as possible are active and communicating. With the use of decoupling capacitances, the general principle is to reduce the amount of active communication between parts of the system that are far apart.

Good strategies

Good design strategies tend to maximize the likelihood of the design goals being achieved. For power distribution networks, the goal is to ensure that the quality of the supply at every component is good enough. The following guiding requirements are fundamental Control the resistance of the supply network by using traces that are wide enough, well soldered connectors, and by providing an adequate number of vias wherever necessary. Control the inductance of the supply network by keeping the power and ground lines in close proximity (use twisted pairs if necessary). Using supply grids or planes usually achieves this goal. However, note that the package inductances contribute to the supply inductance (so use appropriate packages). Add decoupling capacitances across every chip in your system (as recommended by the manufacturer). Modules which communicate heavily should be in close proximity. Modules which are in close proximity should have small common-rail inductance and resistance. The use of ground and supply planes ensures this property. Return paths should be as close to the forward paths as possible. The return path can be provided explicitly by using an additional (grounded) 3

Rdd A

Ldd

+ Vdd Rss B Lss

G1

G2

Q
Figure 1: Power supply network

wire which runs close to the signal wire between the communicating modules. Dierential signaling (with a closely spaced pair of wires) also provides a good return path by default. In mixed signal designs, a single-point ground should be used to connect the ground nets of the analog and digital parts of the subsystem. This will prevent common source coupling between the digital and analog parts. Special care should be taken in signaling as indicated earlier. In order to achieve this goal the distribution network in Figure 3 is recommended. Two metal layers are used to construct two aligned grids, one for Vdd and one for Vss 2 The density of the grid can be adjusted to control the resistance and the inductance. If necessary, additional metal layers can be used to reduce the resistance and inductance further. The limiting case is to use two or more metal planes solely for power distribution. The use of such grids meets the requirements listed above in a straightforward fashion. Such grids are also relatively easy to model, so that a systematic design procedure to estimate the parameters of the grid needed is possible.

2 An alternative style is to use a pair of layers for the vertical wires and another pair of layers for the horizontal wires. This can be done when the VLSI technology oers four or more metal layers. The basic principle is to use more parallel paths to reduce resistance, and to align the forward and return paths to reduce inductance.

Rdd A

Ldd

Vdd + Rss B Lss

G1

G2

G3

Figure 2: Decoupling capacitance is not a total solution

Figure 3: Power distribution grid