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IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 26, NO.

2, APRIL 2011

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Performance of IEC 61850-9-2 Process Bus and Corrective Measure for Digital Relaying
Mitalkumar G. Kanabar, Student Member, IEEE, and Tarlochan S. Sidhu, Fellow, IEEE
AbstractInternational Electrotechnical Commission (IEC) standard 61850 proposes the Ethernet-based communication networks for protection and automation within the power substation. Major manufacturers are currently developing products for the process bus in compliance with IEC 61850 part 9-2. For the successful implementation of the IEC 61850-9-2 process bus, it is important to analyze the performance of time-critical messages for the substation protection and control functions. This paper presents the performance evaluation of the IEC 61850-9-2 process bus for a typical 345 kV/230 kV substation by studying the time-critical sampled value messages delay and loss by using the OPNET simulation tool in the rst part of this paper. In the second part, this paper presents a corrective measure to address the issues with the several sampled value messages lost and/or delayed by proposing the sampled value estimation algorithm for any digital substation relaying. Finally, the proposed sampled value estimation algorithm has been examined for various power system scenarios with the help of PSCAD/EMTDC and MATLAB simulation tools. Index TermsEthernet, generic object-oriented substation event (GOOSE), IEC 61850, IEC 61850-9-2, intelligent electronic device (IED), process bus, sampled values (SVs), substation automation system (SAS).

I. INTRODUCTION EC 61850 standard on Communication Networks and Systems in Substation provides the interoperability within the power substation by dening the communication protocol, data format, and the conguration language [1], [2]. To reduce the cost of complex and long copper wiring, as well as to achieve exibility in signal communications, IEC 61850 part 9-2 has proposed Ethernet based communication network between process level switchyard equipments, and bay level protection and control (P&C) intelligent electronic devices (IEDs), which is referred to as process bus [3]. According to IEC 61850-9-2, process bus Ethernet local-area network (LAN) should facilitate the communication of time-critical messages, such as, generic object-oriented substation event (GOOSE) and raw data sampled values (SVs), within the allowable time [3],

Manuscript received August 26, 2009; revised October 27, 2009. First published February 08, 2010; current version published March 25, 2011. Paper no. TPWRD-00646-2009. The authors are with the Department of Electrical and Computer Engineering, the University of Western Ontario, London, ON N6A 5B9, Canada (e-mail: mkanaba@uwo.ca; sidhu@eng.uwo.ca). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TPWRD.2009.2038702

[4]. Tremendous work is going on from various manufacturers to deploy Ethernet communication networks for the process bus [5][8]. For the successful implementation of the IEC 61850-9-2 process bus, rst of all, the implementation issues, such as performance of time-critical messages over the Ethernet communication network, reliability and availability of communication architectures, and cost need to be analyzed [9], [10]. Reliability and availability analysis of Ethernet switch-based substation communication architectures has been carried out in [11], [12]. However, there is no signicant work reported so far to analyze the performance of a process bus communication network for time-critical messages considering various network parameters. The performance of Ethernet switched communication network are inuenced by many factors, such as speed of the communication link, packet service rate, network background trafc, etc. [13], [14]. On the other hand, according to the IEC 61850 part-5, the message transmission time requirements for the substation automation network must be ensured under any operating conditions and contingencies inside the substation. Therefore, the communication delay for the time-critical messages on process bus, such as sampled value packets and GOOSE messages, are of considerable concern [9]. Especially, the analysis of packet delay and loss for the sampled value packets is more important, as the same sampled value packet is not being transmitted repeatedly, unlike the GOOSE. This paper evaluates the performance of sampled value packets over the IEC 61850-9-2 process bus designed for a typical 345 kV/230 kV substation with the help of a dynamic communication network simulation tool, OPNET [15]. The basic OPNET modeling approach for IEC 61850 substation has been discussed in [16]. However, detailed modeling need to be carried out to consider the various constraints of the practical Ethernet network, and therefore, the efforts have been put in this work to evolve the dynamic models for several communication mechanisms and protocols, e.g. bit error rate on the communication channel and bit error correction mechanism at communication port; Ethernet switch packet buffer and buffer overow mechanism; priority queuing mechanism for time critical packets, etc. In addition to that, dynamic models of Ethernet switch (ESW), Ethernet based ber cables and transceiver ports, and other less time critical le transfer trafcs, etc. have also been developed to analyze more realistic scenarios for the IEC 61850-9-2 process bus performance evaluation. Finally, the results for the sampled value packet loss and delay have been obtained by considering the impact of various process bus network parameters, such as, speed of the communication

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link, sampling frequency of the merging units (MUs), Ethernet switch buffer size and packet service rate, bit-error rate (BER) of the communication channel, and network background trafc. Furthermore, [17] has demonstrated the impact of sampled value lost on the performance of digital relaying protective functions. Reference [9] has also shown the need of smart algorithms for the treatment of lost sampled value data into the modern P&C IEDs, which should be compatible to any (time and/or frequency based) digital relaying algorithm. With these motivations, this paper also presents a corrective measure to compensate for the delayed or lost sampled values into the digital relaying algorithms. And, based on this corrective measure, this paper proposes the sampled value estimation algorithm which can be implemented to work with any digital protection functions. Finally, the proposed algorithm has been examined for various scenarios using PSCAD/EMTDC and MATLAB simulation tools. Section II introduces the major features and the challenges related to IEC 61850-9-2 process bus. Detailed dynamic modeling of process bus devices, protocols, and messages as well as the performance of sampled value messages over the process bus have been discussed using OPNET simulations in Section III. Section IV discusses the proposed sampled value estimation algorithm and its testing using PSCAD/EMTDC and MATLAB simulation tools. Section V concludes this paper. II. IEC 61850-9-2 PROCESS BUS The salient features of IEC 61850-9-2 process bus and the challenges related to the process bus performance have been discussed in this section. A. Features of IEC 61850-9-2 Process Bus As Fig. 1 shows, MU is the key element of the IEC 61850-9-2 process bus, which is installed in the switchyard near to the primary equipments. The merging unit gathers all the information, such as phase voltages and currents from instrument transformers, status information from transducers, etc. from switchyard equipment. All of the analog signals from CTs/CCVTs are converted to digital, merged into a standard sampled value packet format, and nally, synchronized using time stamp. This sampled value packet is published from the MU to the subscribed P&C IEDs over the standardized IEC 61850-9-2 process bus network. B. Challenges With the Performance of the IEC 61850-9-2 Process Bus Communication Network According to IEC 61850, the acceptable maximum communication delay for the time-critical messages is between 3 to 4 ms. This has to be achieved for all of the time-critical messages (e.g., GOOSE and sampled values), independent from the network trafc load on the process bus communication network. To reduce additional time delay caused by TCP/IP (Transmission Control Protocol/Internet Protocol) layers, GOOSE and sampled value messages are directly mapped on the Ethernet link layer. However, this elimination of TCP/IP layer reduces the reliability of packet communication [13], [14]. Therefore, to enhance the transmission reliability of GOOSE, the same GOOSE

Fig. 1. IEC 61850-9-2 process bus concept.

message is repeated several times according to IEC 61850-8-1. GOOSE is event triggered and generally sent few times in a second to the network; whereas, sampled value messages are time triggered and transmitted at the rate of sampling frequency. Thus, the same sampled value message is not repeated, which reduces transmission reliability of sampled value messages over the process bus. Although the priority tagging along with virtual local-area network (VLAN) will be provided to the sampled value packets, this does not ensure the determinism of communication delays and packet loss on the network during worst case conditions [18]. Therefore, this paper focuses on the performance of time critical IEC 61850-9-2 sampled value messages (or packets). III. PERFORMANCE EVALUATION OF IEC 61850-9-2 PROCESS BUS WITH DETAILED MODELING IN OPNET The performance analysis of the IEC 61850-9-2 process bus with dynamic modeling has been detailed in this section. A. Detailed Modeling of Process Bus Using OPNET This subsection describes the modeling of process bus devices, communication protocols, packet format, trafc ows, etc. in compliance with IEC 61850. 1) Packet Format for Sampled Values: The modeling of the standard sampled value packet using the OPNET packet editor has been illustrated in Fig. 2. The sampled values of three-phase-and-neutral voltages and currents (i.e., eight signals) are merged in the application protocol data unit (APDU) at the MUs. More details of the aforementioned sampled value Ethernet packet can be obtained in [3] and [4]. 2) VLANs and Priority Tagging: IEC 61850-9-2 recommends the implementation of VLAN and priority tagging based on IEEE 802.1Q to achieve the QoS for the time critical messages. Therefore, the tag protocol identier (TPID) and tag control information (TCI) packet elds, as shown in Fig. 2, have been incorporated in compliance with IEEE 802.1Q with the help of process editor of the OPNET. The user priority bits into

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Fig. 3. Ethernet switch node model in OPNET.

Fig. 2. Sampled value Ethernet packet format in OPNET.

the TCI packet eld are set such a way that time-critical messages (e.g., SVs and GOOSE) have highest priority; whereas less time-critical le transfer messages have lower priorities. 3) P&C IED and MU Models: The P&C IEDs as well as merging units are designed per the IEC 61850 proposed communication stack based on open systems interconnection (OSI)-7 layers [1]. The dynamic model of P&C IED is designed to receive the sampled value packets from the corresponding MUs for the protection; and also to send GOOSE messages to the corresponding MUs as well as other P&C IEDs. The developed model of MU in OPNET has the capability to communicate in bidirectional mode based on IEC 61850-9-2 [3]. Furthermore, the detailed programming has been carried out in order to incorporate IEC 61850 packet identication algorithm at the data link layers, and bit error correction mechanism at transceiver ports, for both the models (i.e., P&C IED and MU). 4) Ethernet Switch (ESW) Model: The dynamic model of a Ethernet switch with ten ber-optic ports has been developed for full duplex communication at the rates of 10 Mb/s and 100 Mb/s. Fig. 3 shows the simplied diagram of two port Ethernet switch to discuss the working of the modeled ESW. Each received packet is checked for data integrity (bit errors) at the receiving port, and then the packet is sent to the central processing module. Processor reads the destination address and sends the packet to the corresponding output port according to the packet service rate. Finally, at the output port, the packet is queued into the ESW buffer according to the priority tagged on the packet. Packets are transmitted to the network from the output port transmitter base on the priority level of the queue, i.e. highest priority queue emptied rst according to IEEE 802.1p priority (which is part of TCI eld of IEEE 802.1Q standard). 5) Communication Links and Ports: For the process bus, optical-ber-based communication is more preferable, due to its EMI immunity feature. Therefore, two full duplex ber-optic communication links with ports at the data rates of 10 Mb/s and 100 Mb/s have been considered for process bus communication. 6) Trafc Modeling for Process Bus: Three different types of trafc models have been congured in compliance with IEC 61850 for process bus application: 1) high priority event triggered GOOSE messages; 2) high priority periodic (time triggered according to sampling rate) raw data-sampled value mes-

Fig. 4. Typical 345 kV/230 kV transmission substation layout.

sages; and 3) low priority background trafcs (i.e., event triggered client-server applications among the IEDs). B. Simulation of IEC 61850-9-2 Process Bus Using OPNET Fig. 4 shows a typical 345/230 kV transmission substation considered for the analysis. This substation has total 20 CTs and 8 VTs for the protection and control of total eight substation bays. Furthermore, it has been considered that one merging unit can be congured with 8 analog signals from 2 three-phase instrument transformers (CTs/CCVTs), and also with one circuit breaker. Therefore, there will be need of total 14 MUs into the switchyard for this substation. The assignment of primary equipment signals to the particular MU is illustrated in Fig. 4. Fig. 5 shows a dynamic Ethernet switch based process bus communication network simulated for 345/230 kV substation

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Fig. 5. Process bus network for the sample substation simulated in OPNET.

depicted in Fig. 4. According to number of IEDs and MUs, total four 10-port Ethernet switches have been congured in ring architecture, which is one of the practical substation automation architecture [19]. The process bus conguration of total 8 bays with corresponding MUs has been tabulated in Fig. 5. To achieve the better trafc load distribution by separating the broadcast domains, A total of eight VLANs has been congured for this network (i.e., each protection bay has the separate VLAN including two P&C IEDs for protection-A and B, and corresponding MUs). C. Results and Discussion The performance of this process bus network has been analyzed using various parameters, and the impacts of all these parameters have been observed from the packet delay and loss of sampled value packets. To study the impact of each parameter separately, one of the parameter has been varied within the commercially available range, by keeping other parameters to its nominal values, as tabulated in Table I. The performance of sampled values has been analyzed for Line-3 P&C IEDs, which have corresponding MUs connected to the same Ethernet switch; and Bus-1 P&C IEDs, which require sampled values from remote MUs connected to other Ethernet switches. 1) Impact of Communication Link Data Rate and MU Sampling Rate: The most likely used data rates for substation communication links are 10 Mb/s and 100 Mb/s; and sampling frequencies are 1920 Hz and 4800 Hz. The remaining parameters

are considered the same as shown in Table I. It can be observed from Table II that sampled value packet delays are high for the 10 Mb/s network, whereas packet delays for the 100 Mb/s network are within the allowable range. Moreover, as the sampling rate increases from 1920 Hz to 4800 Hz, the sampled value packet trafc increases and hence it causes more sampled value packet delays and average consecutive packet loss per second. 2) Impact of BER of the Communication Channel: It can be perceived from Table III that the BER of the communication channel has more of an impact on the average number of consecutive sampled value packet loss per second and almost negligible impact on the packet delays. This is due to the fact that if the received sampled value packet has higher bit errors even after bit-error corrections, the received packet is rejected at the receiver itself; however, this process has a negligible impact on packet delays. 3) Impact of Process Bus Background Trafc: It can be discovered from Table IV that as background trafc (client/server application packets) increases from 250 kB/s (kilobytes per second) to 350 kB/s, the sampled value packet delay as well as average number of consecutive packet loss per second would increase, even though the sampled value packets have higher priorities compared to client/server applications. This is due to the fact that if the transmission of large client/server packet will start (in absence of higher priority packet in buffer); a higher priority packet has to wait in queue until this large packet is transmitted [18].

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TABLE I PARAMETERS FOR OPNET SIMULATION

TABLE IV IMPACT OF BACKGROUND TRAFFIC

TABLE V IMPACT OF ESW BUFFER SIZE

TABLE II IMPACT OF DATA AND SAMPLING RATES

not cause overow of any buffer, and hence it has little impact on sampled value packet loss, as shown in Table VI. It is also important to note that these results would change according to the size of a substation, and it may be even worse for a larger process bus communication network with the same communication parameters. Therefore, the possible corrective measures have to be taken in order to accommodate the sampled value packet delay and loss.
TABLE III IMPACT OF COMMUNICATION CHANNEL BER

D. Corrective Measures for Process Bus Digital Relaying Traditional digital relaying algorithms have been working satisfactorily using analog signals between bay level and process level over the copper wires. The performance of these robust digital relaying algorithms should not be affected by the implementation of IEC 61850-9-2 based digital process bus in any possible worst case scenarios. Hence, there is a need for some kind of corrective measures which can compensate the sampled value packets delay and loss, as demonstrated in this section. One of the methods is to use adaptive ltering, as discussed in [17]. However, the proposed adaptive ltering is based on phasor estimation using least error square (LES) and hence, it is limited to those digital relaying algorithms which use LES; and also only feasible for one sampled value loss. The major requirements for any corrective measure are as follows: 1) The algorithm should be able to work for almost all of the digital relaying algorithms, regardless of the type of technique (e.g., frequency based or time based). 2) It is simple and easy to implement into the P&C IEDs with fewer computations. 3) It is accurate even for a few consecutive sampled values packet loss. The SV estimation algorithm to enhance process bus performance by meeting almost all aforementioned requirements is explained in the following section.

4) Impact of Ethernet Switch Buffer Size and Packet Service Rate: Due to the store and forward mechanism, packets are always stored into the buffer rst, and then forwarded. Therefore, as buffer size reduces from 2 Mb to 0.5 Mb, the sampled value packet delay increases, however, it has negligible impact on sampled value packet loss as shown in Table V. Furthermore, as Ethernet switch packet service rate decreases from 0.5 Mp/s (mega packets per second) to 0.15 Mp/s, the sampled value packet delay is more affected because sampled value packets have to wait more, before they are forwarded to the corresponding output port. The slow rate of packet service rate does

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TABLE VI IMPACT OF ESW PACKET SERVICE RATE

is the estimated sampled value at th instant, where is the coefcient of n-order polynomial at the th instant, is the sampled value at the th instant, and is the time at the th instant. Using these equations, the second-order SV estimation technique has been explained as follows. The second-order polynomial (i.e., as shown in (4)) can be used to estimate the lost or delayed sampled value by selecting three appropriate known sampled values , , and for a given set of stored coef, , and cients (4) where

Fig. 6. Sampled values for the second-order SV estimation technique: Scenario (a): next samples are not available. Scenario (b): only one next sample is available. Scenario (c): two next samples are available.

IV. SAMPLED VALUE (SV) ESTIMATION ALGORITHM FOR DIGITAL PROCESS BUS BASED PROTECTION FUNCTIONS This section explains the sampled value estimation techniques, and SV estimation algorithm as a one of the corrective measures for sampled value lost or delay. A. Sampled Value Estimation Technique There are several numerical methods available for the estimation (e.g., polynomial approximation, spline techniques, curve tting, etc. [20]). However, implementations of any of these complex numerical methods require additional computational capability. This paper provides the coefcients for estimation techniques using the Lagrange polynomial method, which is easy to implement compared to other available methods, and is applicable to any digital relaying algorithm. According to Lagrange polynomial method, a unique polynomial of degree can be obtained from the given distinct sampled values. SV estimation techniques utilize this polynomial function to estimate the lost or delayed sampled values at a given time , as shown

The set of second-order SV estimation technique coefcients needs to be derived by considering all of the appropriate scenarios. As demonstrated in Fig. 6, there are a total of three possible scenarios for the second-order SV estimation technique: 1) next samples have not been arrived (set-1); 2) next has been arrived (set-2); and 3) following one sample at two samples at and have been arrived (set-3). Three sets of coefcients corresponding to each scenario of Fig. 6 can be obtained for second-order SV estimation, as tabulated in Table VII. A sample procedure to derive these coefcients is demonstrated in the Appendix. All different sets of coefcients for rstand third-order SV estimation techniques have been tabulated in the Appendix. The sets of coefcients for the desired order of SV estimation techniques can be derived by following the same procedure. B. Proposed Sampled Value Estimation Algorithm Fig. 7 shows the ow diagram of the second-order SV estimation algorithmit starts with the loop when the processor of P&C IED is expecting the sampled value packet for the corresponding MU at the th instant. If the sampled value packet arrives, it will be stored into the buffer and traditional digital relaying algorithms will use it from the buffer. However, if the sampled value packet does not arrive, IED supposed to wait for short duration (i.e., ). The value of can be set around two to three sampling intervals (i.e., 0.417 ms to 0.625 ms for 4800 Hz sampling frequency). Even after waiting, if sampled value packet does not arrive, SV estimation will be initiated, and check for the conditions whether next samples have been arrived or not. According to the availability of next samples, the , , and ) will be selected from set of coefcients ( Table VII, and the assignment of corresponding sampled values to the will be done accordingly. The selection of these values in the algorithm has been carried out in order to minimize , , , , the estimation error. These selected values ( and , ) will be used in (4) to solve for . The counter

(1) (2) (3)

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TABLE VII SETS OF COEFFICIENTS FOR THE SECOND-ORDER SV ESTIMATION METHOD

count calculates the total number of consecutive sampled value packets lost or delayed. The utilization of the estimated sampled value for the consecutive packet loss should be within some limit (max. count). Therefore, if the number of consecutive packet lost is higher than max. count, IED should ALARM the condition, as this may be due to failure of communication link, Ethernet switch, merging unit, or any damage in process bus LAN network. Furthermore, the value of max. count is also depend upon the required estimation accuracy, which is explained in following subsection. Finally, if the consecutive SV estimation is less than the max. count, it will store the estimated value into the sampled value buffer, so that traditional digital relaying algorithm can utilize this value. If delayed sample value packets arrive at any time, the estimated sampled value should be replaced with the arrived actual value into the buffer. Moreover, if protection is executed at every few sets of sampling interval, this estimation procedure should also be carried out with same set of sampling interval in order to achieve higher estimation accuracy by utilizing the latest sampled values. It can be noticed that SV estimation algorithm can be implemented to work with any traditional digital relaying algorithm from any IED manufacturer. Furthermore, it is comparatively easy to implement into the IEDs and requires very less computations and memory space. Fig. 7 shows SV estimation using second order estimation technique, however, the same concept of SV estimation algorithm can be applied to any order SV estimation techniques by including the corresponding sets of coefcients and known sampled values. C. Results and Discussion To analyze the overall performance of SV estimation algorithm, a typical 345 kV/230 kV substation (as shown in Fig. 4) has been simulated using PSCAD/EMTDC simulation tool. The proposed SV estimation algorithms for the substation P&C IEDs have been developed using MATLAB simulation tool. The COMTRADE recorder in PSCAD/EMTDC resembles the function of MU at process level, as it samples the analog signal collected from the secondary of CTs/CCVTs. The MATLAB extracts the sampled value streams of each signal from corresponding COMTRADE le. The MATLAB code has also been developed to incorporate various sampled value lost and delayed scenarios obtained from the OPNET. It can be observed from Tables IIVI that the maximum number of SV packet loss occurred is 6 and sampled value packet delay varies between 16

Fig. 7. Flow diagram of the proposed secondorder SV estimation algorithm.

ms to 26 ms. Therefore, in order to analyze the worst case scenario, up to 10 simultaneous sampled values packet loss have been examined coinciding with the time of fault inception (A-G fault created at in line-3 of the Fig. 4). This worst case scenario (up to 10 simultaneous SV packets lost coinciding with the time of fault inception) has been examined on A-phase CT secondary current by considering various source impedance ratios (SIRs), point-on-wave (POW) for faults, noise level in the signal, sampling frequency, and different instances on the wave. For all these different scenarios, the maximum absolute errors in estimating simultaneous SV lost from rst, second, and third order SV estimation algorithms have been compared with the actual values, which is the maximum absolute error incurred without SV estimation algorithm. 1) Effect of SIR of the System and POW of the Fault: Table VIII shows the comparison of maximum absolute error in

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TABLE VIII EFFECT OF VARIOUS SIRS AND POW

Fig. 8. Effect of different noise levels (SNR). TABLE IX EFFECT OF VARIOUS SAMPLING FREQUENCIES

CT secondary current with different SV estimation algorithms and the actual values of the lost samples (or the maximum absolute error incurred without SV estimation algorithms) for various system SIR and fault POW by considering different number of sampled values lost at the fault inception. The POW at zero, mid and peak refers to the points at 0 , 45 , and 90 , respectively, on the A-phase voltage. It can be observed from the table that for the overall maximum absolute error of 14.806 A, the second order SV estimation technique estimates the sampled values with maximum absolute error of 0.9541A (6.5%), whereas, rst order and third order techniques have error of 2.179A (14.71%) and 3.617 A (24.43%), respectively. Although the maximum absolute error for rst-, second-, and third-order techniques varies with SIRs and POW, these maximum sampled value estimation errors are considerably less compared to the error incurred without estimating the sampled values (i.e. actual value of the lost sample). 2) Effect of Noise Into the Power Signal: It is also important to examine the effect of possible noise levels present into the received sampled values. Fig. 8 presents the maximum estimation error incurred from the SV estimation algorithms and compares with the maximum absolute error without estimating SVs. for different signal-to-noise ratios (SNRs) in dB. It can be seen from the gure that even for 10 consecutive sampled values lost with 40 dB SNR, the maximum absolute error without sampled value estimation is 9.466 A; whereas, the maximum percentage errors from rst-, second-, and third-order estimation techniques are 16.11%, 6%, and 0.7%, respectively.

If further higher levels of noise are expected, using a specic lter to attenuate the noise before the SV estimation is recommended. 3) Effect of Sampling Frequency: The effect of different sampling rate of the MUs on the proposed estimation algorithm for 1920 Hz and 4800 Hz has been tabulated in Table IX. The tabulated result shows that for 1920 Hz sampling frequency with 10 consecutive sampled value lost, the rst, second and third order estimation techniques have maximum estimation error as high as 27%, 21%, and 8%, respectively. Whereas, for the 4800 Hz sampling frequency, the maximum absolute error using rst-, second-, and third-order estimation techniques are 15%, 2.5%, and 9%, respectively. Therefore, it is recommended that the allowable maximum number of sampled values for the estimation should be selected based on sampling frequency too. 4) Effect of Sampled Lost Instance on the Wave: Fig. 9 shows the different instances considered to calculate maximum absolute error incurred by using the SV estimation technique. Fig. 10 shows that maximum absolute error incurred due to sampled values lost also depends upon the actual value of the signal at a particular instant. The estimated sampled values using second- and third-order SV estimation techniques have low maximum absolute error compared to the rst order for 10 consecutive sampled value loss.

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Fig. 9. Sampled value lost at different instances during the fault.

Fig. 10. Effect of different instances on the wave.

The aforementioned tabulated results from various scenarios show that the accuracy of the estimated sampled value does not always improve with the higher order of the SV estimation techniques in all cases. This is due to the nonlinear characteristic of voltage and current signals with decaying dc component and/or noise at the time of fault inception. If more accuracy is required or a large number of consequent sampled value packet loss is expected, the higher order or other more complex estimation techniques, such as spline, curve tting, etc. have to be used by adding more processing power. V. CONCLUSION The performance of IEC 61850-9-2 process bus has been evaluated for Ethernet switched ring architecture of a typical 345 kV/230 kV substation. Using the OPNET simulation tool, the dynamic models of IEC 61850-based process bus devices and communication protocols have been developed to analyze the delay and packet loss for the sampled value packets by considering various communication parameters, such as speed of the communication data link, sampling frequency of the merging units, network background trafc, Ethernet switch buffer size, packet services rate, and the communication channel bit error rate. It has been demonstrated that these process bus parameters have inuence on the sampled value

packet loss and maximum delays. For this particular process bus network, the observed maximum sampled value delay is up to 26 ms; whereas, the average number of consecutive sampled value lost per second are 6. In order to alleviate the impact of lost and delayed sampled values on digital relay algorithms, the corrective measure, i.e. sampled value estimation techniques have also been presented in this paper. Using these SV estimation techniques, this paper proposes the SV estimation algorithm with the sets of coefcients. To examine the accuracy of the proposed SV estimation algorithm, same 345 kV/230 kV substation has been simulated in PSCAD/EMTDC and the sampled value estimation algorithm has been programmed in MATLAB, for the various scenarios, such as system SIRs, fault POW, noise levels in the received signal, and instances on the wave. Moreover, the rare worst case scenarios have been presented by considering up to 10 consecutive sampled values lost, coinciding with the fault inception. For various SIRs and POW scenario, the maximum estimation errors are 8.5%, 7.6%, and 3.2% incurred to estimate up to 5 consecutive sampled values lost or delayed of the maximum actual value using rst, second, and third order SV estimation techniques respectively. In case of different noise levels, the maximum absolute errors from rst, second and third order SV estimation are 7%, 5%, and 1.1%, respectively, up to 5 consecutive samples lost. Moreover, if the sampling frequency reduces from 4800 Hz to 1920 Hz, the maximum absolute error would increase up to 17% for 5 consecutive sampled values lost. For the same scenarios with 10 consecutive sampled values lost, the maximum estimation errors are 25% or more. However, up to 5 consecutive sampled values loss at 4800 Hz sampling frequency, the proposed sampled value estimation algorithm not only offers the reasonable accuracy, but also less computational requirements, and compatibility with any traditional digital relaying algorithm. If even more estimation accuracy is needed, higher order SV estimation techniques or more complex numerical methods can be implemented using the same concept of SV estimation algorithm presented here. It is recommended that the corrective measure techniques (rst order, second order, third order, or any other techniques) should be selected considering required estimation accuracy (selectivity constraints) and available processing capability (speed constraint) for a particular protection IED. APPENDIX COEFFICIENTS OF SV ESTIMATION Sample procedure to obtain coefcients for second order SV estimation technique as well as coefcients for rst and third order SV estimation techniques have been explained in this Appendix. The calculations to derive set-3 coefcients have been explained here by referring the Fig. 6(c). For a constant sam, the time difference between any consecupling frequency tive samples will remain same as follows:

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TABLE X SETS OF COEFFICIENTS FOR THE FIRST-ORDER SV ESTIMATION METHOD

Furthermore, there will be a total of four possibilities for sampled value lost, and accordingly, when a total of four sets of coefcients has been derived, as tabulated in Table XI.

REFERENCES
TABLE XI SETS OF COEFFICIENTS FOR THIRD-ORDER SV ESTIMATION METHOD [1] IEC Standard for Communication Network and Systems in Substations, IEC Std. 61850, 200304, 1st ed. [2] K. P. Brand, V. Lohmann, and W. Wimmer, Substation Automation Handbook, 1st ed. Switzerland: Utility Automation Consulting Lohmann, 2003, pp. 301312. [3] IEC Standard for Communication Network and Systems in Substations Part-9-2: Specic Communication Service Mapping (SCSM)-Sampled Values over ISO/IEC 8802-3, IEC 61850-9-2, 2004, 1st ed. [4] UCA international users group, Implementation Guidelines for Digital Interface to Instrument Transformers Using IEC 61850-9-2. Tech. Rep. IEC 61850-9-2LE. [Online]. Available: http://www.tc57wg10.info/ downloads/digifspec92ler21040707cb.pdf [5] B. Kasztenny, D. Mcginn, S. Hodder, D. Ma, J. Mazereeuw, and M. Goraj, Practical IEC61850-9-2 process bus architecture driven by topology of the primary equipment, presented at the CIGRE Session Paris, France, Aug. 2008, paper B5-105. [6] L. Andersson, K. P. Brand, and D. Fuechsle, Optimized architectures for process bus with IEC 61850-9-2, presented at the CIGRE Session Paris, France, Aug. 2008, paper B5-101. [7] L. Hossenlopp, D. Tholomier, D. P. Bui, and D. Chartrefou, Process bus: Experience and impact on future system architectures, presented at the CIGRE Session, Paris, France, Aug. 2008, paper B5-104. [8] T. Schaefer, H. Bauer, W. Fischer, D. Gebhardt, J. Glock, C. Hoga, R. Kutzner, U. Nolte, W. Steingraeber, F. Steinhauser, T. Stirl, and K. Viereck, Process communication in switchgear according to IEC 61850-architectures and application examples, presented at the CIGRE Session Paris, France, Aug. 2008, paper B5-106. [9] B. Kasztenny, J. Whatley, E. A. Udren, J. Burger, D. Finney, and M. Adamiak, Unanswered questions about IEC 61850What needs to happen to realize the vision?, presented at the 32nd Annual Western Protective Relay Conf. Spokane, WA, Oct. 2005. [10] T. S. Sidhu, M. G. Kanabar, and P. P. Parikh, Implementation issues with IEC 61850 based substation automation systems, presented at the National Power System Conf Mumbai, India, Dec. 2008. [11] M. G. Kanabar and T. S. Sidhu, Reliability and availability analysis of IEC 61850 based substation communication architectures, presented at the IEEE Power Eng. Soc. General Meeting Calgary, AB, Canada, Jul. 2009. [12] L. Andersson, K. P. Brand, C. Brunner, and W. Wimmer, Reliability investigations for SA communication architectures based on IEC 61850, presented at the IEEE Power Tech. St. Petersburg, Russia, Aug. 2005. [13] C. E. Spurgeon, Ethernet: The Denitive Guide. Sebastopol, CA: OReilly, 2000. [14] W. Stallings, Local and Metropolitan Area Networks, 5th ed. Englewood Cliffs, NJ: Prentice-Hall, 1997. [15] OPNET ModelerOPNET Technologies Inc. [Online]. Available: http://www.OPNET.com [16] T. S. Sidhu and Y. Yin, Modelling and simulation for performance evaluation of IEC 61850 based substation communication systems, IEEE Trans. Power Del., vol. 22, no. 3, pp. 14821489, Jul. 2007. [17] E. Demeter, T. S. Sidhu, and S. O. Faried, An open system approach to power system protection and control integration, IEEE Trans. Power Del., vol. 21, no. 1, pp. 3037, Jan. 2006. [18] J.-D. Decotignie, Ethernet-based real-time and industrial communications, Proc. IEEE, vol. 93, no. 6, pp. 11021117, Jun. 2005. [19] IEEE PSRC H6 Working Group, Application consideration of IEC 61850/UCA2 for substation ethernet local area network communication for protection and control May 2005, Tech. Rep. [20] M. J. Maron and R. J. Lopez, Numerical Analysis: A Practical Approach, 3rd ed. Belmont, CA: Wadsworth, 1991.

According to second order SV estimation algorithm, the co[from efcients for SV estimations can be wrote in terms of the Fig. 6(c)], as follows:

The aforementioned obtained coefcients are used for the condition when two next sampled values are available, as explained in Section IV. The coefcients for rst order SV estimation technique using (2) can be written as follows:

With respect to rst order SV estimation, there are two possible conditions for the SV lost or delayed: a) next sample at has not been arrived (set-1); b) next sample at has been arrived (set-2). According to these two scenarios, both coand ) can be obtained as shown in Table X. efcients ( The coefcients for third-order SV estimation using (2) can be derived as follows:

KANABAR AND SIDHU: IEC 61850-9-2 PROCESS BUS AND CORRECTIVE MEASURE

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Mitalkumar G. Kanabar (S05) received the B.E. degree from Sardar Patel University, Gujarat, India, in 2003, the M.Tech. degree from the Indian Institute of Technology (IIT) Bombay, Mumbai, India, in 2007, and is currently pursuing the Ph.D. degree in electrical and computer engineering at the University of Western Ontario, London, ON, Canada. His research areas include power system protection, control and automation, implementation of the IEC 61850 standard, and communication applications for smart grid; and grid integration issues with distributed energy resources.

Tarlochan S. Sidhu (M90SM94F04) received the B.E. (Hons.) degree from the Punjabi University, Patiala, India, in 1979 and the M.Sc. and Ph.D. degrees from the University of Saskatchewan, Saskatoon, SK, Canada, in 1985 and 1989, respectively. He was with the Regional Computer Center, Chandigarh, India; Punjab State Electricity Board, India; and Bell-Northern Research Ltd., Ottawa, ON, Canada. From 1990 to 2002, he was with the Department of Electrical Engineering, University of Saskatchewan, where he was Professor and Graduate Chairman of the Department. Currently, he is Professor and Chair of the Electrical and Computer Engineering Department at the University of Western Ontario, London. He is also the Hydro One Chair in Power Systems Engineering. His research interests are power system protection, monitoring, control, and automation. Dr. Sidhu is a Fellow of the Institution of Engineers (India) and a Fellow of the Institution of Electrical Engineer (U.K.). He is also a Registered Professional Engineer in the Province of Ontario and a Chartered Engineer in the U.K.