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we used the analog multiplier MC1494. At this point the chain of wavelets similar to the one displayed in Fig. 1 has been generated. Notice that by changing the frequency of the master clock the shape of the wavelet is scaled proportionally. If this happens, the amplitude of the wavelet and the lters cut off frequency need to be readjusted in order to have a scaled version of the same wavelet. The wavelet signals are then applied to a convolution section. The wavelets are multiplied by the signal to be analyzed and then integrated. The integrating block was implemented using Operational . The Transconductance Ampliers (OTA) [9] and a capacitor OTA was chosen because it has the advantage of being electronically programmable, i.e., its transconductance is a function of the current . The integrator is resetted right after the end of each wavelet. Using transistor resets the capacitor . Many applications a pulse require interfacing the circuit to a digital system, therefore, a sample , and capacitor and hold circuit is needed. The buffer, transistor perform this function. The signals that reset the capacitors ( and ) are two pulses, their duration must be sufciently long to fully is used to trigger discharge the capacitors. Observe that the pulse , i.e., the output is sampled rst, and then the integrator is resetted. is triggered by a timed signal produced by a comparator Pulse circuit. A delayed version of the envelope signal is compared with a threshold voltage producing a square wave. The threshold for the comparator is adjusted to produce a positive ank just before the wavelet ends. This ank triggers an astable multivibrator that produces , i.e., the sampling pulse. V. EXPERIMENTAL RESULTS The rst test consists of applying different signals to nd their wavelet coefcients. The wavelet used for this case-study has an Hz, modulated by an envelope that analyzing frequency has a frequency which is 1/16 of the inner frequency, i.e., Hz/16 218.75 Hz. Recall that the analyzing frequency must be an integer multiple of the envelope for short wavelets. Fig. 4 shows the results of analyzing a pure sinusoidal signal at the exact same phase shift with frequency (3500 Hz) of the wavelet but with respect to the real part. Fig. 4(a) shows the product of the real part of the wavelet and the input signal, and the result of the integration. Fig. 4(b) shows the same results but for the imaginary part. As expected, the result of integrating the signal in Fig. 4(a) is zero, and the result of integrating Fig. 4(b) is 1.0 V which corresponds to the imaginary part of the wavelet coefcient. Since the real part is zero, the magnitude of this wavelet coefcient is 1.0 V and the . This voltage is the result of applying a signal at the phase is same frequency as the analysis signal, therefore, it can be used as a normalization parameter. If other signals with different frequencies but the same amplitude are applied, the magnitude of the coefcients will be smaller as Fig. 5 shows. The plot in Fig. 5 was obtained by applying a set of sinusoidal signals with an amplitude of 1 V, covering the frequency range where the magnitude of the coefcient was higher than zero. This is the frequency resolution characteristic of the wavelet employed. VI. CONCLUSION A systematic approach to generate wavelets in time-domain was developed. In particular, we showed the time-domain implementation of Amplitude Modulated Wavelets. Each wavelet transform coefcient is being computed simultaneously as the wavelet is

generated and the output is available right after the wavelet is completed. This constitutes a system with minimum delay. The results are suitable for those applications that require fast computation of wavelet coefcients. By using a bank of these circuits a spectral decomposition can be achieved with small computation time. REFERENCES
[1] H. H. Szu, C. C. Hsu, P. A. Thaker, and M. E. Zaghloul, Image wavelet transforms implemented by discrete wavelet chips, Opt. Eng., vol. 33, no. 7, pp. 23102325, July 1994. [2] T. R. Edwards and M. D. Godfrey, An analog wavelet transform chip, in ICNN Proc., 1993, pp. 12471251. [3] J. Lin, W. Ki, T. Edwards, and S. Shamma, Analog VLSI implementations of auditory wavelet transforms using switch-capacitor circuits, IEEE Trans. Circuits Syst. I, vol. 41, Sept. 1994. [4] C. K. Chui, An Introduction to Wavelets. New York: Academic, 1992. [5] M. Vetterli and J. Kovacevic, Wavelets and Subbband Coding. Englewood Cliffs, NJ: Prentice-Hall, 1995, sec. 2.6. [6] A. V. Oppenheim and R. W. Schafer, Discrete-Time Signal Processing. Englewood Cliffs, NJ: Prentice-Hall, 1989, pp. 447448. [7] I. Daubechies, The wavelet transform, time-frequency localization, and signal analysis, IEEE Trans. Inform. Theory, pp. 9611005, 1990. [8] P. P. Vaidyanathan, Multirate Systems and Filter Banks. Englewood Cliffs, NJ: Prentice-Hall, 1993, ch. 11. [9] E. S anchez-Sinencio, R. L. Geiger, and H. Nevarez-Lozano, Generation of continuous-time two integrator loop OTA lter structures, IEEE Trans. Circuits Syst., vol. 35, Aug. 1988.

Re-examination of Pole Splitting of a Generic Single Stage Amplier

Wing-Hung Ki, Lawrence Der, and Steve Lam
Abstract Pole splitting on the frequency response of a generic single stage amplier due to the insertion of a compensation capacitor is re-examined. The Millers Theorem is discussed in detail and it is shown that the initial dominant pole of an uncompensated amplier remains dominant after compensation. Input and output impedances are computed to reveal the root loci and bandwidth of these quantities. Simulation results are presented in conrming the analysis Index Terms Amplier design, Frequency compensation.

I. INTRODUCTION Stability is an important issue in the design of a feedback amplier. Designers rely heavily on the gain and phase margins in determining the transient performance of an amplier. Dominant pole compensation with pole splitting is a traditional technique used to obtain adequate phase margin. Fig. 1(a) shows the schematic of a generic connected single-stage amplier with a compensation capacitor across its input and output ports. Textbook discussions [1][4] usually assume that the initial dominant pole is at the input side of the
Manuscript received October 31, 1994. This paper was recommended by Associate Editor S. Mori. W.-H. Ki is with the Electrical and Electronic Engineering Department, Hong Kong University of Science and Technology, Clear Water Bay, Hong Kong. L. Der is with Hyundai Electronics America, San Jose, CA 95134 USA. S. Lam is with Philips Semiconductors, Sunnyvale, CA 94088 USA. Publisher Item Identier S 1057-7122(97)00811-8.

00577122/97$10.00 1997 IEEE

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(a) (a) Fig. 2. Derivation of the Miller effect. (b)

(b) Fig. 1. (a) A generic single-stage amplier. (b) Miller effect modeling of the amplier.

amplier. With the addition of , the dominant pole of the modied gain transfer function and the input impedance can be predicted quite accurately by using the Millers Theorem [1]. Yet many ampliers are required to drive large capacitance, e.g., off-chip loads, and the initial dominant pole may be at the output side instead. Under this condition, a brute force application of the Miller effect would give wrong results. This paradox has been observed in [5], and simplied small signal models were developed to account for both cases when the initial dominant pole is either at the input or output sides of the amplier. Yet the complete small signal model is a four-pole system, which poses conceptual difculties. In this brief, we re-examine pole splitting of a generic single-stage amplier in detail in emphasizing the correct condition in applying the Millers Theorem (Section II). In identifying the actual movement , it will be shown that no of the poles due to the addition of crossover of root loci could happen (Section III). In deriving the input and output impedances, it is concluded that the application of the Miller effect has to be used with precaution, otherwise, wrong results would be obtained (Section IV). Section V presents simulation results, which conrms the analysis in the previous sections. II. MILLERS THEOREM REVISITED In calculating the input impedance of a vacuum tube, Miller observed that the contribution to the apparent capacity [6] of a connected between the grid and the plate was equal capacitor (in the limit that the ratio of a resistor divider was to unity), where is the amplication constant of the tube [6, eq. (20)]. Fifty years later, Cherry and Hooper formalized the derivation, and named this increase in capacitance the Miller effect [7], which was later relabeled as the Millers Theorem [1]. The Miller effect was also applied to the output port in calculating the output impedance as seen by the amplier [7]. The classical derivation is demonstrated next (cf., [1]). The objective is to match the input impedance of a connected across the two-port network having an admittance as shown ports [Fig. 2(a)] with an equivalent input admittance in Fig. 2(b). The input admittances of Fig. 2(a) and (b) are given by

. Hence, the input capacitance is increased by a factor , provided that is not modied by the presence of [1], [2], [6]. This capacitance amplication is known as of is referred as the Miller capacitor [7]. The the Miller effect, and above derivation is usually applied to calculate the dominant pole of a single-stage generic amplier with a Miller capacitor across the gain , the system stage, as shown in Fig. 1(a). Before the addition of and . With the insertion of has two real poles at , if the dc gain is large, then the dominant pole is approximately given by [Fig. 1(b)] [4] (2) We also know that pole splitting occurs, so that the pole associated , moves to a lower frequency with the input time constant moves while the pole associated with the output time constant to a higher frequency. It is quite tempting to use the reected at the output side to calculate the capacitor nondominant pole, i.e., we might expect the following to hold:

(3) If the above assumption is true, then from Fig. 1(b), it is obvious that the pole associated with can only move to a lower frequency , which is in variance with with the addition of the concept of pole splitting, and the following questions have to be addressed. 1) How to evaluate the validity of (1) and (3)? If they are true, why it is wrong to compute the nondominant pole using (3)? 2) Assume the dominant pole is at the output side before the , i.e., , then the Miller effect addition of predicts that the input pole will eventually become dominant with a large . Does this imply that the root loci for the two (cf., [5])? poles cross each other at a particular value of 3) With the ambiguity in calculating the (output) nondominant pole, what can be said about the output impedance of Fig. 1(a)? 4) Conventionally, we associate the input impedance with the (modied) input time constant [cf., (2)]. This concept appeals to our intuition, but is it true? The rst question can easily be answered with reference to and be zero rst. Then the gain is given by Fig. 1(a). Let both . With nonzero and , the gain , then changes to which is a function of . This calculated gain violates the condition to be for the Miller Theorem to be valid, which requires [1], [2], and it is thus clear that a careless independent of application of the Miller effect may give inaccurate results.

(1) where generating is the gain of the network [circuit not shown]. If the admittance is a capacitance, then

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(a)

(a) (b)

(c) as dominant pole. (b) Pole splitting Fig. 3. (a) Pole splitting with with as dominant pole. (c) Pole movement with zero between poles. (b)

III. ROOT LOCUS OF THE GAIN TRANSFER FUNCTION The second question is best answered by computing the exact locations of the two poles of Fig. 1(a). The transfer function can easily be computed as (4a) and (4b) [4] shown at the bottom of the page where

Fig. 4. (a) Input impedance with .

. (b) Input impedance with

with (6b) (also shown at the bottom of the page) where is the in (6b) is written as discriminant. Note that the rst term of to reect the condition . In most , applications, , which implies , , and , (6a) can be approximated by for a small

(4c) Clearly, if , then (4) reduces to (5) It is easily seen that (4) and (5) are completely symmetrical w.r.t. and , and and . Without loss of generality, let . The two poles, with the insertion of , can be computed as (6a) (6c) , the Equation (6) shows a very important fact: for any discriminant is always positive (6b), which means that two real poles , and a very small , the poles are obtained. With can be approximated by (7a) (7b)

(4a)

(4b)

(6b)

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POLES

AND

ZEROS

OF

TABLE I VARIOUS TRANSFER FUNCTIONS

Therefore, the dominant pole remains dominant with the , while the nondominant pole moves to insertion of higher frequency. , (6b) can be rewritten as For a large

(8a) The dominant term of given by is , and the two poles of (6) are then

One simple way is to apply the method of root locus. Regrouping the denominator of (4a) gives (9) (see the bottom of the page). Hence, has two poles at , and ; , and the other at one zero at the origin, i.e., . Usually, will be at a higher frequency than the two poles, and the pole splitting predicted by (7) and (8) occurs. But in some cases, e.g., when the single-stage amplier is formed by an NMOS or PMOS transistor operating , then would be between the in the linear region, two poles. To obtain the condition for such a case, again, assume . For smaller than , it is required that (10) . Analogous This condition can be satised easily when . For both relation can be obtained for the case with cases, the two poles move in the same direction, i.e., toward the origin (Fig. 3(c)). IV. COMPUTATION OF INPUT AND OUTPUT IMPEDANCES

(8b)

(8c) These results are the same as obtained in [4]. The argument applies equally well for , where all s have to be replaced by s, and vice versa. The root loci for both cases are shown in Fig. 3(a) and (b). From (6), it is concluded that the two poles move apart, if . But do they necessarily move in opposite directions, as shown in Fig. 3(a) and (b)? For the case when (or ) is comparable to or even smaller than 1, solving (6) in tracing the movement of the poles will be exceedingly complicated.

To answer the third question of Section II, we compute the input and output impedances of the single-stage generic amplier. The input impedance is given by (11) (see the bottom of the page). When , (11) reduces to (12a) (12b) From Fig. 1(a), we learn that (12b) is necessarily true. Yet in order , it is to account for the pole splitting that occurs when more benecial to use (12a) for discussion. Hence, the initial input

(9)

(11)

(13)

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impedance consists of one zero and two poles, with a perfect polezero cancellation. Two cases can then be distinguished. The rst , as shown in Fig. 4(a). With the one being that introduction of the Miller capacitor, pole splitting occurs according to (6), while the zero moves to a lower frequency, as shown in (11). , the pole associated with Since in general, moves to a lower frequency faster than the zero. The modied input impedance is as shown in Fig. 4(a). The 3 dB frequency is , approximately given by which is the same as that obtained in (2), and the application of the Miller effect works perfectly. For the second case, the initial dominant pole is at the output . The initial locations of the zero and poles side, i.e., , the pole associated are as shown in Fig. 4(b). With a nonzero moves to a lower frequency, while the pole associated with moves to a higher frequency. The zero still moves to with a lower frequency. A typical frequency response of the modied input impedance is shown in Fig. 4(b). The 3 dB frequency is . Although approximately given by , this frequency can further be approximated by which is the same as that obtained in the rst case, this frequency is , rather than the actually associated with the output pole , which is different from the prediction obtained input pole by a straightforward application of the Miller effect. For the output impedance, simple computation gives (13) shown at the bottom of the previous page. The symmetry between (11) and (13) is immediately obvious, and similar argument can be applied to obtain the corresponding Bode plots of the output impedance, with . 2) the following modications. 1) At dc, the output resistance is . 3) The zero after The initial pole/zero cancellation is at is at . the addition of The above computation leads to a very important observation. For both the input and output impedances, the dominant poles after the , are approximately the same, namely, addition of which means that both the input and output equivalent capacitances increases. A paradox of the conventional view on pole splitting arises. Since one pole moves to higher frequency, the impedance associated with that pole should have a wider 3 dB bandwidth. This paradox is resolved if we treated the system as a whole, rather than isolating the input and output port by a naive argument of pole splitting, which associates the input and output time constants with the respective ports. Hence, the impedance at a particular port is affected by elements in the other parts through circuit dynamics, which may not be obvious. This dissociation answers the fourth question of Section II. V. SIMULATION RESULTS
AND

VI. CONCLUSION The following conclusions can be drawn from our investigation. 1) With the insertion of the Miller capacitor, pole splitting occurs. Under certain conditions, as discussed in Section II, both poles could move to lower frequencies together. 2) For the gain transfer function, the initially dominant pole . remains dominant with the insertion of 3) Associating the poles with the input and output ports have to be done carefully, especially when input and output impedances are to be computed. It has been shown that the 3 dB frequencies and are both the same for a large , contrary for to the predicted results by applying the pole splitting argument indiscriminately. ACKNOWLEDGMENT The authors would like to thank Prof. G. Temes of the Oregon State University, Corvallis, for technical suggestions. Thanks are also due to Dr. J. Lau of HKUST, who provided the authors with [6]. REFERENCES
[1] J. Millman, Microelectronics: Digital and Analog Circuits and Systems. New York: McGraw-Hill, 1979. [2] A. Grebene, Bipolar and MOS Analog Integrated Circuits Design. New York: Wiley Interscience, 1984. [3] A. Sedra and K. Smith, Microelectronics Circuits, 2nd ed. Orlando, FL: HRW, 1987. [4] P. Gray and R. Meyer, Analysis and Design of Analog Integrated Circuits, 3rd ed. New York: Wiley, 1993. [5] H. Yang and D. Allstot, Considerations for fast settling operational ampliers, IEEE Trans. Circuits Syst., vol. 37, pp. 326334, Mar. 1990. [6] J. M. Miller, Dependence of the input impedance of a three-electrode vacuum tube upon the load in the plate circuit, Nat. Bureau Stand. Sci. Papers, vol. 15, no. 351, pp. 367385, June 1919. [7] E. M. Cherry and D. E. Hooper, Amplifying Devices and Low-Pass Amplier Design. New York: Wiley, 1968.

DISCUSSIONS

In order to conrm the analysis mentioned in the preceding sections, the circuit shown in Fig. 1(a) is simulated using Hspice. be the initial Two cases are considered. For the rst case, let F, dominant pole. The components are chosen as follows: , F, , and k . , Hence, the initial poles and dc gains are rad/s (i.e., Hz), rad/s (i.e., Hz). Then is increased from 0 to 1 F. For the gain transfer function, Table I shows that pole splitting occurs according to (7) and (8), and the RHP zero moves in from innity according to (4). For the input impedance, the ( zero associated with the pole-zero cancellation at Hz) moves to a lower frequency, as predicted by (11). Similarly, for the output impedance, the zero associated with the pole-zero ( Hz) also moves to lower frequency cancellation at as predicted. Corresponding results can be obtained by interchanging and , to make the output pole dominant.