Quartus Tutorial 2 Simulation

A step-by-step tutorial using Quartus II v9.x

by Gregory L. Moss
Example 4-1 Tutorial*
Design a combinational circuit that will indicate the majority result of 3 individuals voting. First, define the problem in a truth table (see Table 4-1) and then write the SOP expression for the truth table. We will enter this design using schematic capture in Quartus (see Fig. 4-3).
A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 V 0 0 0 1 0 1 1 1

_ _ _ A B C + A B C + A B C + A B C

Table 4-1 Truth table and SOP expression for Example 4-1

Fig. 4-3 Quartus II schematic for SOP solution to Example 4-1

* This is the second tutorial in the series and assumes that you have already reviewed Tutorial 1 and have some experience with using Quartus. This example is from Unit 4 Design & Simulation of Combinational Circuits in Digital Systems Lab Manual: A Design Approach, 11th edition by Gregory L. Moss.
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Quartus II procedures for Example 4-1

Start a New Design Project
1. Start Quartus II. The main screen will open. Start the New Project Wizard by clicking the Create a New Project button on the Getting Started window. You can also start the New Project Wizard by double-clicking Open New Project Wizard in the expanded Start Project task folder in the Full Design Flow Tasks Pane. The New Project Wizard: Introduction window will open. Click the Next button. The Directory, Name, Top-Level Entity dialog box opens. Use the computer drive specified by your lab instructor for project storage. Type the name of the working directory, example4_1, for this project in the dialog box. The project name, majority, should also be typed in the dialog box. The Wizard will automatically copy the project name as the top-level design entity name for this project. Each project will have one top-level design entity. A new directory (folder) should be created for each separate design project. There will be many files associated with a project and they should all be placed in the same folder. Do not use duplicate design file names in a project. Click the Next button. You will be asked if the directory should be created. Click the Yes button. The Add Files dialog box will open. This simple logic circuit does not have any additional design files to add to the project, so click the Next button. The Family & Device Settings dialog box opens. Use the correct device information for your specific hardware in this dialog box. Select the appropriate Family in the drop-down box. Under Target device, choose Specific device selected in Available devices list. Select the target device from the list of Available devices. Click Next. The EDA Tool Settings dialog box opens. There are no additional tools to use, so click Next. The Summary window opens. Click Finish if the information looks correct. This is the final New Project Wizard screen. Note: Project settings may be changed in the Settings dialog box, which can be opened from the Assignments menu or by clicking the Settings button in the tool bar.

2. 3.

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7. 8.

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Create a Block Diagram/Schematic File

9. Open the Create Design task folder in the Tasks Pane (click the expand button). Double-click Create New Design File to open the New file dialog box. Select Block Diagram/Schematic File under Design Files and then click OK.

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A blank worksheet on which we will draw our schematic appears. Open the File menu and choose Save As. The Save As dialog box opens. Schematic files have a .bdf file extension. Make sure the Add file to current project is checked and click Save.

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Use the Quartus II Block Editor to draw the schematic for our project. Click the Symbol Tool button (gate symbol) on the left side of the Block Editor window (or double-click the left mouse button anywhere in the drawing area or right-click the mouse, choose Insert and then Symbol) and the Symbol dialog box will appear. Open the set of folders for Libraries, Primitives, and Logic and select a logic gate. Multiple copies of symbols can be quickly inserted using Repeat-insert mode. Click OK. Repeat for all gates needed.

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Place input and output symbols in the schematic so that you can connect logic signals to the circuit. Open the Symbol dialog box, close the logic library, open the pin library, and select input or output. Click OK. Label the input and output node names by double-clicking on the default pin_name with the left mouse button and then typing the appropriate input or output name in the Pin Properties dialog box. Click OK when completed with each label. Repeat to label all input and output ports. Draw the wires to make the necessary circuit connections. Point the mouse cursor at a device connection and the pointer will turn into a cross-hair, hold down the left mouse button, move the cursor towards the desired connection point, and release the mouse button. If you need more than one right-angle turn in the wire, you will need to end the wire (by releasing the button) and then continue drawing the wire from that point (by pressing the mouse button again). When you create a T-intersection, connection dots are automatically inserted. Components or wires can be moved by selecting them (point and click on it once with the left mouse button) and dragging them to the desired location. To delete any part of the drawing, select the desired part and press the delete key. Save the file.

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Analysis & Synthesis

15. Expand the Compile Design Task to view the compilers sub-tasks. Double-click the Analysis & Synthesis task. This will check our design to make sure it is a complete circuit and convert it into a format that the compiler can use to interpret our design. A message box will indicate if this task is successful and the task will receive a green check. Remember that a successful Analysis & Synthesis task does not imply that the logic circuit is drawn correctly or will produce the desired output for an application. This only means that the circuit schematic is synthesizable (i.e., it will produce a logic circuit). Click OK.

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If you have errors, the Analysis & Synthesis was NOT successful message will appear. Click OK and point the cursor to a red error message in the message window at the bottom of the screen and open the message menu by clicking the right mouse button. Context-sensitive help is available if you choose Help from the menu. If you choose Locate in the message menu and then choose Locate in Design File (or double-click the left mouse button on the error message), the location of the error in the design file will be highlighted. You can also return to the design file by clicking the majority.bdf tab or using the Window menu or double-clicking the left mouse button on majority in the Project Navigator. Make the necessary corrections to the schematic and Start Compilation again. You cannot continue unless this step is successful!

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Simulate the Design

17. Quartus II has a simulator tool that can be used to simulate the behavior of a circuit design. Simulation inputs (called test vectors) are drawn in a Vector Waveform File (.vwf). Output signals and other circuit nodes to be observed are also specified in the Vector Waveform File. Create a Vector Waveform File to verify the correct operation of this design by double-clicking Create New Design File in the Task Pane. Select Vector Waveform File listed under Verification/Debugging Files in the New dialog box and click OK.

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The Waveform Editor window will open. Click the Save button on the toolbar (or in the File menu). The Save As dialog box indicates that the file will be saved as a Vector Waveform File type with the same file name as the design entry file of the current project. This *.vwf file should be added (see check box) to the current project in this directory (folder).

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Specify an End Time of 8 s (an arbitrary time that we selected) for the simulation file. Open the Edit menu and choose End Time. Enter 8 and select s in the End Time dialog box. Click OK.

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Specify a Grid Size of 1 s (another arbitrary time period) for the simulation file. Note that the Grid Size cannot be larger than the End Time. Select a Grid Size that will provide a sufficient number of grid units in the End Time period to be able to adequately simulate this project. Open the Edit menu and choose Grid Size. Enter 1.0 and select s in the Grid Size dialog box for Time period. Click OK.

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Open the View menu and choose Fit in Window (or press Ctrl+W on the keyboard).

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Next insert the circuit nodes that are to be simulated. Open the Edit menu, choose Insert, and then select Insert Node or Bus in the submenu (or double-click in the Name field of the Waveform editor). The Insert Node or Bus dialog box will open. Open the drop-down box for Radix and change it to Binary. To search for nodes that can be added to the Vector Waveform File, click the Node Finder button.

Radix selection

Node Finder button

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The Node Finder window opens. To locate the input and output pins for this design, open the drop down list for the Filter and select Pins: all. Click the List button to display a list of input and output pins in the Nodes Found window. Filter set for Pins: all List button

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Next you will need to select nodes from the Nodes Found list to be entered into the vwf file. There are two ways to do this. You can select the entire list by clicking the >> button or you can highlight one or more of the nodes in the Nodes Found list and click the > button.

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The selected nodes should be listed in the Selected Nodes box. Click OK to return to Insert Node or Bus dialog box.

Click OK again to return to Waveform Editor window.

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The input and output nodes for the design are now inserted into the Waveform Editor window. To change the order in which the signal nodes will be displayed, first select the node to be moved by clicking on the node name (in the Name column) and then releasing the button. Next click again on the node name and drag it up or down while holding the mouse button down. Release the mouse button when the waveform indicator line is in the desired position.

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Create the desired input test vectors for the project simulation. We will be applying all eight possible combinations for the circuit inputs a b c using a binary count sequence (just like in the truth table). Edit the input waveforms by selecting a time segment on the input to be changed. Point the mouse cursor at the beginning of a time segment to be changed, hold down the left mouse button, and drag to the end of the desired time. The time segment selected will be highlighted. Multiple time segments can be selected by holding down the CTRL key while dragging through a time segment with the left mouse button pressed. Clicking the waveform editing buttons on the left of the Waveform Editor window can change the logic levels for the selected time segments. Create the high pulses for the selected time segments by clicking on the 1 (Forcing High) button.

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Continue editing the input vectors by selecting appropriate time segments and clicking the 1 button. Note: If you make a mistake, select the time segment that needs to be changed back and click the 0 button.

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Save the vwf file.

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We are going to perform a functional simulation on the project to determine if our design is correct. Note: We can also do a timing simulation, which will take into account all propagation delays for our device. To perform a functional simulation, open Verify Design and then Simulate Design tasks. Double-click Edit Settings in the Tasks Pane. In the Simulator Settings dialog, open the drop down menu for Simulation Mode and select Functional. Click OK. The simulator task should then specify Functional.

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Perform the simulation. Start the simulator by double-clicking Quartus II Simulator (Functional) in the Tasks Pane. The Simulation Report will be generated by Quartus.

Click OK when the Simulator was successful message appears.

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If necessary, open the View menu and choose Fit in Window to view the entire Simulation Waveforms results.

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Verify that the functional simulation of the project matches the desired truth table. If the simulation results are incorrect, you have an error in the design and it will be necessary to correct the bdf schematic and repeat the Analysis & Synthesis task and then re-simulate to check again.

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You may also wish to toggle the display to Full Screen to maximize the Simulation Waveforms pane (open View menu and choose Full Screen or press Ctrl+Alt+Space on the keyboard). Another click on Full Screen will return to the standard multi-pane display.

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Manually Assign Pin Numbers

35. To make manual pin assignments, open the Assign Constraints task folder in the Tasks Pane and double-click the Edit Pin Assignments (Open Pin Planner) Task (or click the Pin Planner button on the toolbar). The Pin Planner window will open. Since the design has already been compiled, the input and output nodes for this logic circuit are listed in the table at the bottom of the Pin Planner window.

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In the Pin Planner window, double-click the Location field for one of the circuit nodes. Type the desired pin number in the Location field (or scroll through the drop-down list of pin assignment choices until you come to the desired pin number and click the mouse button while pointing to that number). Then press Enter. Continue assigning appropriate pins for all inputs and outputs. Close the Pin Planner window when all pin assignments have been entered.

The pin choices are dependent upon the specific FPGA/CPLD device and IC package that was assigned as a target device so it is critical that you have specified the correct device.

Example pin assignments for a Terasic DE1

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Compile the Project

37. After entering the desired pin numbers for all signals in the Pin Planner, you must compile the design. The design will be compiled from the top-level of the project as defined by the current project name. The current project name is always given in the banner at the top of the screen. There is only one design file for this project since it is a flat design. With the Compile Design sub-tasks open in the Task Pane, double-click the Compile Design task (or click the Start Compilation button on the toolbar). When each sub-task is finished, it will receive a green check in the Tasks Pane.

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Program a PLD 38. Attach the FPGA/CPLD development board to the PC using the appropriate interface cable (USB-Blaster or ByteBlaster). Also attach the proper power supply to the board. Be sure to follow any special instructions for your specific FPGA/CPLD development board. Open the Programmer window by double-clicking Program Device in the Tasks Pane.

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Check the programmer window to verify that the correct type of hardware interface (USB-Blaster or ByteBlaster) is identified. Only one of these interface types will be correct for the FPGA/CPLD development board used in your lab. The Program/Configure function for the programmer should be selected.

If the programmer window reports either No Hardware or the wrong type of interface, click the Hardware Setup button. Open the drop-down box labeled Currently selected hardware: and select the appropriate interface hardware (USB-Blaster or ByteBlaster) for your development board. Click Close on the Hardware Setup dialog box to return to the Programmer window. 41. To prevent damage to the FPGA/CPLD, make sure that output pins have not been connected to input sources (such as logic switches). Turn on the power to the board & click the Start button in the Programmer window. 42. When the Progress bar shows 100%, the programming is complete and the FPGA/CPLD is ready for testing. Connect lights and switches to the chips pins, if necessary. Test your circuit by applying all possible input combinations using the logic switches and monitor the resulting output on the lights. Compare your circuits operation with the theoretical truth table (Table 4-1). Does it match? If your circuit works correctly, demo your project to your lab instructor. Record your results in a truth table.

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