Analysis, design, and prototyping of a narrow-band radio for application in wireless sensor networks

by

Fred S. Lee
Submitted to the Department of Electrical Engineering and Computer Science in partial fulllment of the requirements for the degree of Master of Engineering in Electrical Engineering at the MASSACHUSETTS INSTITUTE OF TECHNOLOGY May 2002 c Massachusetts Institute of Technology 2002. All rights reserved.

Author . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Department of Electrical Engineering and Computer Science May 24, 2002

Certied by . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Anantha P. Chandrakasan Associate Professor Thesis Supervisor

Accepted by . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Arthur C. Smith Chairman, Department Committee on Graduate Students

Analysis, design, and prototyping of a narrow-band radio for application in wireless sensor networks by Fred S. Lee
Submitted to the Department of Electrical Engineering and Computer Science on May 24, 2002, in partial fulllment of the requirements for the degree of Master of Engineering in Electrical Engineering

Abstract
In the past few years, system-level exploration of wireless data-harvesting techniques have driven circuit designers to consider power-aware radio nodes as a key component of wireless sensor networks. In this work, a discrete implementation of a narrow-band radio in the ISM band will be described. The constructed narrow-band radio achieves a bit-rate of 1M bit/sec, and features a 0dBm to 20dBm adjustable power amplier. A discussion of circuits, systems, and implementation will be presented. High frequency analog design will also be discussed in detail. Finally, an analysis of the power-states and power hooks in the narrow-band radio will be explored to demonstrate a exible, power-aware radio system design. Thesis Supervisor: Anantha P. Chandrakasan Title: Associate Professor

Acknowledgments
I would like to thank Prof. Anantha Chandrakasan for allowing me this great opportunity to research wireless radios, build transceivers, and have a much better understanding of RF circuits than I rst did (which was close to zero knowledge) when I rst joined the group. His patience, guidance, and encouragements have been integral in seeing this project to the end. I am also grateful for his encouragements and guidance to me to make the paradigm shift from an undergraduate status/lifestyle of grades and classes to the graduate student mindset of research, papers, and creativity. I would also like acknowledge the AMPS team for their support and patience from those many late nights of debugging, debugging, and debugging. Did I mention debugging? Especially Piyada Phanaphat, for her great perspective on life when things are getting down, and Nathan Ickes, for his sarcastic humor. Two great things to make late nights at lab more interesting. Speaking of making lab a great place to be, I am thankful for the friendships of Raul Blazquez Fernandez, Ben Calhoun, Travis Simpkins, Rex Min, Alice Wang, Seonghwan Cho, Manish Bhardwaj, Puneet Newaskar, Theodoros Konstantakopoulos, Sam Leifan, and Margaret Flagherty. They are all role models to me in many ways, professionally and personally. I am so glad that I am able to know them and that we are in the same group together. My parents, Ken and Connie Lee, and brother, Ray Lee. Wow wow wow. Thanks for always being there; your love and patience; and all the great food. Yum. My apartment-mates, nori, richmoy, and jl79, for being who they are, and keeping me sane this year, with impromptu grilled-cheese sandwiches at night, late night Tekken Tag Tournament beat downs, and those times when we almost quit school and move back to Taiwan to start a band, singing Boyz II Men and Enrique Iglesias. Maybe one day... Watch for our recording. My brothers and sisters in Christ. wooo hooo.

Finally, Jesus Christ, who my life belongs to and to whom I am the fathers child. These are some of my favorite scriptures. if we claim to be without sin, we deceive ourselves and the truth is not in us. if we confess our sins, He is faithful and just and will forgive us our sins and purify us from all unrighteousness. if we claim we have not sinned, we make him out to be a lair and his word has no place in our lives. - 1 john 1:8-10 i aint perfect. and its ok. then i saw in the right hand of him who sat on the throne a scroll with writing on both sides and sealed with seven seals. and i saw a mighty angel proclaiming in a loud voice, who is worthy to break the seals and open the scroll? but no one in heaven or on earth or under the sun could open the scroll or even look inside it. i wept and wept because no one was found who was worthy to open the scroll or look inside. then one of the elders said to me, do not weep! see, the Lion of the tribe of Judah, the Root of David, has triumphed. He is able to open the scroll and its seven seals. Then I saw a Lamb, looking as if it had been slain, standing in the center of the throne, encircled by the four living creatures and the elders... he came and took the scroll from the right hand of him who sat on the throne. and when he had taken it, the four living creatures and the 24 elders fell down before the Lamb... and they sang a new song: You are worthy to take the scroll and to open its seals, because you were slain, and with your blood you purchased men for God from every tribe and language and people and nation. You have made them to be a kingdom and priests to serve our God, and they will reign on the earth. then i looked and heard the voice of many angels, number thousands upon thousands, and ten thousand times ten thousand... in a loud voice they sang: worthy is the Lamb, who was slain, to receive power and wealth and wisdom and strength and honor and glory and praise! then i heard every creature in heaven and on earth and under the earth and on the sea and all that is in them, singing: to him who sits on the throne and to the Lamb be praise and honor and glory and power, for ever and ever! the four living creatures said, Amen, and the elders fell down and worshiped. - revelation 5 glory glory glory. and hallelujah. one day, itll be party time. yeeeah. And now, enjoy the circuits.

Contents
1 Introduction 1.1 1.2 Wireless Sensor Networks . . . . . . . . . . . . . . . . . . . . . . . . AMPS Node Architecture . . . . . . . . . . . . . . . . . . . . . . . . 17 17 19 23 23 24 25 26 27 28 30 32 32 33 36 52 52 60 60 60 61

2 AMPS Radio Power-Aware Architecture 2.1 2.2 Wireless Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Aware Radio Transmitter Architecture . . . . . . . . . . . . . 2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 2.3 Manchester Encoding and DC Osets . . . . . . . . . . . . . . Gaussian Filter . . . . . . . . . . . . . . . . . . . . . . . . . . Direct-Modulation of VCO . . . . . . . . . . . . . . . . . . . . Power Amplier . . . . . . . . . . . . . . . . . . . . . . . . . . Antenna . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TX Power-Aware Design Summary . . . . . . . . . . . . . . .

Power-Aware Radio Receiver Architecture . . . . . . . . . . . . . . . 2.3.1 2.3.2 2.3.3 Low Noise Amplier . . . . . . . . . . . . . . . . . . . . . . . Demodulation Architecture . . . . . . . . . . . . . . . . . . . RX Power-Aware Design Summary . . . . . . . . . . . . . . .

2.4

Phase-Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.1 Power-Aware Design for PLL . . . . . . . . . . . . . . . . . .

2.5

Power States for Radio Transceiver . . . . . . . . . . . . . . . . . . . 2.5.1 2.5.2 Control Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . Power States Analysis . . . . . . . . . . . . . . . . . . . . . . 7

3 Impedance Matching Circuits and Practical Implementation 3.1 3.2 3.3 Impedance Matching Circuits . . . . . . . . . . . . . . . . . . . . . . Practical Impedance Matching . . . . . . . . . . . . . . . . . . . . . . Transmission Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 3.4 3.5 3.6 Microstrip Lines . . . . . . . . . . . . . . . . . . . . . . . . . .

63 63 67 67 71 74 76 76 77 77 78 79 79 79 80 81 82 83 83 84 89 91 97 98 99 99

Power Amplier Impedance Matching . . . . . . . . . . . . . . . . . . Low Noise Amplier Impedance Matching . . . . . . . . . . . . . . . Antenna Impedance Matching . . . . . . . . . . . . . . . . . . . . . .

4 Other Circuits and Layout Approach 4.1 4.2 4.3 4.4 Power-Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . 10MHz Squarewave Generator . . . . . . . . . . . . . . . . . . . . . . Oscillator Choice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Layout Approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.1 4.4.2 4.4.3 4.4.4 Ground Plane . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Plane . . . . . . . . . . . . . . . . . . . . . . . . . . . . Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trace Sizes, Via Sizes, and Substrate Selection . . . . . . . . .

5 Experiments on Range and Power of Radio Board 5.1 5.2 Bit-Error Rate and Range Tests . . . . . . . . . . . . . . . . . . . . . Power Analysis on one Node to Node Link Using AMPS Radio . . .

6 Conclusions A Homodyne and Heterodyne Receivers:Trados and Advantages B Matlab Files for Impedance Matching Calculations B.1 ustrip.m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.2 Chamcalc.m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.3 Eecalc.m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B.4 Eefcalc.m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 8

B.5 Fcutcalc.m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 B.6 Kcalc.m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 B.7 Lecalc.m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 B.8 Lgcalc.m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 B.9 Losscalc.m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 B.10 Skincalc.m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 B.11 Veldelcalc.m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 B.12 Wecalc.m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 B.13 Zccalc.m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 B.14 impedance.m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 B.15 quickrun.m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 B.16 microstep.m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 B.17 ustep.m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 C Schematics and Layout for Radio Board 111

10

List of Figures
1-1 Wireless sensor network [1] . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Node architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Node stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Top and bottom of radio board . . . . . . . . . . . . . . . . . . . . . 2-1 Transmitter architecture . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Circuit to remove DC oset inherent in single-supply design. . . . . . 2-3 3rd -order Gaussian low-pass lter . . . . . . . . . . . . . . . . . . . . 2-4 Power control pins for power amplier . . . . . . . . . . . . . . . . . 2-5 Power amplier power consumption vs. output power . . . . . . . . . 2-6 Antenna . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Horizontally-aligned dipole antenna: elevation plane . . . . . . . . . . 2-8 Vertically-aligned dipole antenna: elevation plane . . . . . . . . . . . 2-9 Receiver Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 Schematic for the LNA . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 SNR vs. BER plot for binary shift-keying in multiple diversity L [21] 2-12 Heterodyne receiver architecture with high IF frequency choice (top) and low IF frequency choice (bottom) . . . . . . . . . . . . . . . . . . 2-13 Freq vs. magnitude rejection plot [22] . . . . . . . . . . . . . . . . . . 2-14 Typical SAW lter implementation [24] . . . . . . . . . . . . . . . . . 2-15 Discriminator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 Bode plot of equation 2.4 . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 Time domain plot of discriminator response to two frequencies . . . . 11 37 38 39 40 41 42 18 20 21 21 24 25 27 28 29 30 31 31 32 33 35

2-18 Key signals in tx-rx wireless link . . . . . . . . . . . . . . . . . . . . . 2-19 Varactor diode characteristics [25] . . . . . . . . . . . . . . . . . . . . 2-20 LM6152 Frequency response [26] . . . . . . . . . . . . . . . . . . . . . 2-21 Plot of AC voltage applied to varactor (C2) and AC voltage produced at discriminator output (C1) . . . . . . . . . . . . . . . . . . . . . . . 2-22 Plot of AC voltage applied to varactor (C3), AC voltage produced at discriminator output (C2), and VDC (C1) . . . . . . . . . . . . . . . . 2-23 Plot of transient step response from varactor (C2) to discriminator output (C1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 Plot of varactor input (C2) to discriminator output (C1) . . . . . . . 2-25 Root-Locus and Bode plots of feedback system . . . . . . . . . . . . . 2-26 Frequency synthesizer circuitry . . . . . . . . . . . . . . . . . . . . . 2-27 PLL block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28 Open loop response to PLL given dierent charge pump gains . . . .

43 44 46

48

48

49 50 51 53 54 57

2-29 Transient responses of VCO control voltage for given charge pump gains 59 2-30 Ideal power consumption in each node state . . . . . . . . . . . . . . 3-1 Two common types of impedance matching circuits [10] . . . . . . . . 3-2 Types of circles in ZY Smith Chart . . . . . . . . . . . . . . . . . . . 3-3 Transmission line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 Loaded transmission line . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 Microstrip line example . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 Mitered corner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Matching network for LMX2242 power amplier . . . . . . . . . . . . 3-8 Matching network for Gigaant antenna . . . . . . . . . . . . . . . . . 4-1 Power supply lters on PCB . . . . . . . . . . . . . . . . . . . . . . . 4-2 Squarewave generator from sinusoid input . . . . . . . . . . . . . . . 5-1 Bit Error rate test results . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Energy/bit plots for table 5.1 . . . . . . . . . . . . . . . . . . . . . . 12 61 63 65 68 69 72 73 75 76 77 78 84 86

A-1 DC oset illustration [9] . . . . . . . . . . . . . . . . . . . . . . . . . A-2 Even order distortion illustration [9] . . . . . . . . . . . . . . . . . . . A-3 Image frequency in a heterodyne reciever architecture [9] . . . . . . . A-4 IF frequency: high IF (top) and low IF(bottom) [9] . . . . . . . . . .

92 93 94 95

C-1 Schematic of analog circuits for the radio board . . . . . . . . . . . . 116 C-2 Schematic of digital circuits for the radio board . . . . . . . . . . . . 117 C-3 PCB layout of top metal . . . . . . . . . . . . . . . . . . . . . . . . . 118 C-4 PCB layout of gnd plane (negative mask) . . . . . . . . . . . . . . . . 119 C-5 PCB layout of intermediate metal layer . . . . . . . . . . . . . . . . . 120 C-6 PCB layout of power plane (negative mask) . . . . . . . . . . . . . . 121 C-7 PCB layout of bottom metal . . . . . . . . . . . . . . . . . . . . . . . 122 C-8 PCB layout of all metal layers . . . . . . . . . . . . . . . . . . . . . . 123

13

14

List of Tables
5.1 Values used for variables in equation 5.1 . . . . . . . . . . . . . . . . 85

C.1 Bill of Materials for ICs . . . . . . . . . . . . . . . . . . . . . . . . . 112 C.2 Bill of Materials for Inductors . . . . . . . . . . . . . . . . . . . . . . 113 C.3 Bill of Materials for Capacitors . . . . . . . . . . . . . . . . . . . . . 114 C.4 Bill of Materials for Resistors . . . . . . . . . . . . . . . . . . . . . . 115

15

16

Chapter 1 Introduction
1.1 Wireless Sensor Networks

In the recent past, wireless sensor networks have been inspired by the onset of transistor miniaturization and single-chip mixed-signal integrated circuits. Public and private sectors such as the military have gained interest in the research of wireless sensor networks for the purposes of battleeld monitoring, biological/chemical detection, and/or reconnaissance [1]. The MIT micro-Adaptive Multi-domain Power aware Sensors (AMPS) group was formed to research the design and prototyping of a wireless network, and to develop energy-aware techniques for such systems. The AMPS team is composed of people with expertise in RF, digital, software, signal processing, and information theory. A microsensor network is made up of many identical wireless nodes. These nodes are scattered in an environment to be monitored with high node densities for fault tolerance, and system robustness. The network is set up in such a way that the radius of communication of each node at least intersects with one other node. Usually, these nodes are immobile and homogenous. Each node contains a processor, radio transceiver, link manager interface, sensors, and power supply. The processor is responsible for the intelligence of each node, and will contain the algorithms and MAC software designed to control the entire network, allowing the network to operate together. The radio transceiver should meet FCC regulations in its band of operation, 17

and is required to only transmit/receive short distances, due to the energy-ecient advantages of multi-hop routing in wireless networks. Multi-hop access transfers data from one node to another, until the data eventually arrives at the base-station. The base-station has the advantage of being attached to an innite power supply. This innite power supply allows the burden of high energy processing to be done at the base-station. Because the batteries of each node are not replaceable once they are deployed, battery regeneration techniques as well as initial battery energy densities are of great importance. Among the many types of sensors that can be placed on each node are acoustic, image, or seismic sensors [2].

Figure 1-1: Wireless sensor network [1]

Figure 1-1 is an example of a wireless sensor network. Each open circle in the gure represents a dead node (due to exhausting its power supply or other faults), and each gray circle represents a node that is functional. The solid line represents the direction of travel for the source the network is tracking. The dotted lines represent the direction of data hopping; the base-station, marked with B, is where the data hopping lines terminate. The concentric circles represent the sensor range. As the source moves within the network, the network dynamically recongures itself to 18

continue tracking motion, seismic changes, and/or acoustic changes. The dotted lines represent the multiple paths that the data traverses towards the basestation, so that power is conserved across the network [1]. Figure 1-1 shows how multi-hop and multi-path techniques can be used to maximize the lifetime of a network. Since the energy it takes to transmit a certain distance r goes as rn , where n is anywhere from two to four depending on the environment, multi-hop data transmission allows for lower overall network power consumption if the eciencies for power ampliers are high, and energy-startup costs for each node is minimal. From observing the complexity of multi-hopping networks as compared to direct transmssion, it is apparent that the lifetime of a network is less dependent on the power usage of a single node, but much more dependent on the uniform power usage of all the nodes. The more uniformly a network consumes power, the longer the lifetime of the network [1]. Furthermore, the gure shows fault tolerance, which is somewhat similar to the independence of a networks lifetime from the lifetime of a single node. Since there are many paths that data can travel to and from the basestation, there are few critical paths where if a node dies, then many other nodes can no longer communicate with the base-station. In eect, the more interconnected the nodes are, the more fault-tolerant the network is. More information on network lifetime can be found in [1].

1.2

AMPS Node Architecture

Figure 1-2 is a block diagram of the nodes architecture. In actual implementation, the hardware for the nodes are divided up as such: the processor board contains the DC/DC converter and processor; the sensor board contains the battery and sensors; and the radio board contains the radio transceiver, PA, LNA, antenna, and Link Manager Interface (LMI). The radio transceiver board is the focus of this work. The key dierence of this radio from others is the addition of power-aware circuits, in addition to the traditional RF circuitry. This allows for minimal power consumption from an intelligent management of energy. The specications for the uAMPS node 19

Figure 1-2: Node architecture

are as follows: (55mm)2 board space for each stack low power operation, with power hooks ability to accommodate spatial density of 10nodes/m2 tx/rx distances from 10m to 100m The power hooks are power controls for the radio states, output power levels, and dierent states including idle and o. In a combined eort of numerous graduate students [3] [4], the node is implemented in the MTL laboratories, meeting the above specications, as AMPS node 1. A picture of the actual implementation is in gure 1-3. The focus of this thesis is the design of a power aware narrow-band transceiver. Figure 1-4 is the radio board that was constructed.

20

Figure 1-3: Node stack

Figure 1-4: Top and bottom of radio board

21

22

Chapter 2 AMPS Radio Power-Aware Architecture

This chapter outlines the system-level considerations for the narrow-band radio that is implemented in the AMPS node. Dierent from most radio transceivers, this radio has high compartamentalization and many power-aware hooks to turn on and o dierent sections and states of the radio, to allow for power-aware operation. The radio core is National Semiconductor s LMX3162 radio transceiver chip. Many blocks are a hybrid of on-chip (LMX3162) and o-chip discrete components. This chapter serves to outline the basics of the wireless standard, radio architecture, and power control hooks.

2.1

Wireless Standard

As with most commercial transceivers, this radio is built in the Instrumentation, Scientic, and Medical (ISM) band. First of all, there are no restrictions on who may operate in this band. Secondly, the ISM band is in the 2.4GHz to 2.48GHz range,and requires power emissions below 20dBm. This limitation in power output does not aect the specications for wireless sensor nodes, because wireless sensor nodes do not need to transmit very far distances. It is possible to calculate the necessary receiver sensitivity from the power limit in order to transmit the maximum 23

desired distance of 100m between two nodes. The minimum sensitivity of a wireless receiver in this network can be calculated using the Friis Transmission Equation [5]: Pr = Pt 4R
2

G0t G0r

(2.1)

In equation 2.1, Pr represents the power received at the receiver (also the receiver sensitivity, if expressed in dBm), Pt is power transmitted at the transmitter, is wavelength of the RF signal, and R is the distance between the transmitter and receiver. Finally, G0t and G0r are the gains of the transmit and receive antennas. It is important to keep in mind that this equation does not take into account possible impedance mismatches from the PA/LNA to the antenna. If the antennas are assumed to be isotropic, then G0t and G0r are equal to 1. Using the equation and setting the frequency to 2.45GHz , a receiver sensitivity of 60.225dBm is required to receive the 20dBm signal at 100m from the transmitter. For the uAMPS radio, a Bluetoothcompatible transceiver chip from National Semiconductor was chosen to serve as the core of the radio transceiver [6]. The architecture of this chip, the LMX3162, and surrounding circuitry to construct a radio, will be discussed. next section.

2.2

Power-Aware Radio Transmitter Architecture

Figure 2-1: Transmitter architecture

24

Figure 2-1 is a block diagram of the uAMPS radio architecture. Starting from the TX Data in gure 2-1, the signal path for transmission can be traced.

2.2.1

Manchester Encoding and DC Osets

The binary data is fed through the 3rd -order Gaussian lter, from the Xilinx FPGA. It is important that the average DC voltage of the this data is immobile, with respect to time. If the data is encoded using Manchester encoding, then the data is guaranteed to have approximately equal numbers of upwards edges and downwards edges, at any given time. The importance of the DC voltage being immobile, lies in the fact that when the system is used in direct modulation, it is desired that only high frequency (the encoded data) be translated to the PLL. If DC components or low frequency components are also sent to the PLL, then the response of the loop to correct for this DC oset results in longer settling time. All of these add to reduce the probability of data recovery. So, this is why Manchester encoding is important. However, this does not solve the entire problem; because the data coming out of the radio is from a single-supply design, the 0V to 3V transitions hold a DC oset of 1.5V in steady state. To remove this DC oset, a simple circuit shown in gure 2-2 is used to remove this DC oset inherent in the single-supply design side-issue, before the Manchester encoded data is sent into the Gaussian lter. The way this circuit works, is that

Figure 2-2: Circuit to remove DC oset inherent in single-supply design.

when there is no data being transmitted, the voltage level of TXDATAHIGH is set to be 3V , and the voltage of TXDATALOW is set to be 0V . Through the 500 resistors, the impedance looking to the right of the voltage divider at DC is 6.2k , 25

since the input impedance of the VCO input is 4k . Since the impedance looking to the right of the voltage divider is more than a decade above the resistor divider leg that it is in parallel with, the DC voltage that can be approximated at the divider is 1.5V . At the input of the VCO, the voltage is attenuated by
4k , 2.2k+4k

giving a voltage

around 0.9V. When it is desired to transmit data, the voltages of TXDATAHIGH and TXDATALOW are tied together in the Xilinx, thus further reducing the impedance between the left of the 2.2k resistor to the input from the Xilinx. This impedance dierence allows for a rough estimate that voltage drop across the 500 resistors in parallel is zero. When 3V and 0V is applied to both of the Xilinx outputs, the voltage that appears at the VCO is +/-0.9V . Hence, the DC oset problem has been resolved. The 2.2k resistor also acts as a gain control resistor; if the bandwidth of transmission needs to be increased, all that needs to be done is to change the value of the resistor. The only caveat is that the smallest value for this resistor needs to be no less than 1k for the above approximations to hold true. But the good news is that since the f requency/voltage constant of the second VCO input is relatively high, to have a maximum +/-0.2V voltage swing at the VCO input will force an increase in this resistor size. in addtion, the 2.2k resistor sets one of the three poles that are associated with the 3rd -order Gaussian low-pass lter. Thus, at high frequencies, there could be some low frequency ltering/amplitude degradation due to a pole entering into the picture earlier than expected. Even though this may seem like a negative eect (our Gaussian lter is no longer a true Gaussian lter because one of the poles appear in a dierent place), this actually helps to solve inter-symbol interference problems. By experimentation (a potentiometer), the optimal value for this resistor was found to be 2.2k , as stated in this explanation.

2.2.2

Gaussian Filter

2-3 is the schematic for the Gaussian lter. The Gaussian lter is required for Gaussian frequency-shift keying (GFSK) data transmission to create Gaussian pulses. As shown in gure 2-3, the input impedance of the second control pin of the VCO to allow for a direct-modulation transmitter architecture has a resistance of 4k . This 26

Figure 2-3: 3rd -order Gaussian low-pass lter

resistor, along with C1 (which is valued at 50.6pF ), sets one of the three low frequency roll-o poles. The other two poles to cause severe 3rd -order low-pass ltering are caused by L and C2 . The voltage divider of
4k 4k+R

sets the DC attenuation of

the data from the input to output of the lter. The values L and C2 are 1mH and 390pF , respectively.

2.2.3

Direct-Modulation of VCO

After the Gaussian pulses are generated, These pulses of data are fed directly into the second modulation pin of the VCO, which is already serving as the VCO for a 1.2GHz phase-locked loop (PLL). This second input pin through the external VCO that directly modulates the output frequency in an additive manner to the main VCO output that is embedded in the PLL has a much lower f requency/volts constant than the portion of the VCO that serves the PLL. The second input pin has a f requency/volts constant of 1.25M Hz/V , while the portion of the VCO involved in the PLL has a f requency/volts constant of 60M Hz/V . This makes sense, because the VCO needs to span over 100MHz in frequency band, centered at 1.225GHz which the 60M Hz/V constant allows. On the other hand, for a direct-modulation scheme, the f requency/voltage constant needs to be small, to allow narrowband direct-modulation. The actual PLL and mechanics of direct-modulation will be described in detail in a later section of this chapter. By providing a Gaussian pulse that has an amplitude of 0.2V , to the second input pin, The data is frequency shifted +/-250kHz , centered about 1.225GHz . The frequency doubler within the LMX3162 27

radio chip shifts these frequencies up to +/-500kHz , centered about 2.45GHz .

2.2.4

Power Amplier

After a set of matching networks (detailed description in Chapter 3 ) external to the LMX3162 chip, the 2.45GHz signal is sent to the external power amplier. This external PA has a coarse power control embedded in its on-o switch. In the o-state, the PA draws only 0.5A, or 1.7W on a 3.3V power supply. When the PA is on, it is adjustable between six output levels: 0dBm, 3dBm, 5dBm, 10dBm, 15dBm, and 20dBm. These power control levels are easily interfaced to the Xilinx board; gure 2-4 shows how this is done with the Xilinx in an open-drain output conguration. In gure 2-4, the voltage Vpabias is set internally by the MAX2242 power amplier.

Figure 2-4: Power control pins for power amplier

Thus, when the control voltages for any of the transistors on the Xilinx FPGA are pulled high, the MOSFET becomes a short, and bias current is forced down the resistor. since Vpabias is xed, the bias current is sensed by the PA, and multiplied by a constant, accordingly. Due to non-zero source impedances of voltage sources, this bias current-to-output power relation is linear for only a small range. In the opposite case, when the voltages at the transistor gates are high, the MOSFETs are open-circuited, thereby disallowing any bias current to be drawn out of Vpabias . In this manner, shorting only one transistor at a time, it is possible to set six output power levels for the power amplier. The values for the resistors that were obtained by experimentation are as follows: R1 = 180K for 6dBm output power 28

R2 = 165K for 0dBm output power R3 = 140K for 5dBm output power R4 = 100K for 10dBm output power R5 = 40K for 15dBm output power R6 = 8K for 20dBm output power. The power consumed by the power amplier alone in each of these states is shown in gure 2-5. The percentages above the bars represent power amplier eciency1 .

Figure 2-5: Power amplier power consumption vs. output power

Finally, after another matching network for the antenna, the signal radiates into the air according to the characteristics of the antenna. A 3-d plot of the radiation pattern of the antenna is shown in gure 2-6(a). The impedance matching circuit for the antenna will be outlined in Chapter 3. 29

(a) Antenna 3-d radiation pattern [16]

(b) Antenna shape [16]

Figure 2-6: Antenna

2.2.5

Antenna
1 -wave, 2

The antenna that is used is a a

horizontally-aligned antenna designed by

GigaAnt [17]. The radiation pattern is theoretically omnidirectional, has a gain of 4dBi (betraying a hint of signal directivity despite omnidirectional claims), and has an eciency of 62% [16]. As can be seen in gure 2-6(a), the antenna actually has high directivity in the Z direction, which is unwanted if a high lateral transmission radius is desired. The elevation radiation pattern for a traditional antenna dipole that is horizontally-aligned is in gure 2-7. It is apparent that the gain at 90 o is already very small, compared to the gain at 0o . The solid line represents the radiation pattern due to a solid ground plane, and the dotted line represents the radiation pattern due to an earth ground [5].
1 A good candidate for a replacement antenna would be a normal 4 -wave vertically-

aligned hertzian dipole antenna on a ground plane. The radiation pattern of such an antenna shown accordingly in gure 2-8. The solid line represents the radiation pattern due to a solid ground plane, and the dotted line represents the radiation pattern due to an earth ground. The drawback to a vertically-aligned antenna is that the radio board prole is no longer low-prole. Loop antennas (square or circular) are
1

PA eciency is radiatedpower/powerconsumed

30

Figure 2-7: Horizontally-aligned dipole antenna: elevation plane

good candidates for horizontally-aligned antennas that have good lateral radiation. The downside is that the output coupling of the antenna to the circuit needs to be fully-dierential. However, by using a balun, the single-ended signal would be able to couple with fully-dierental circuits [5].
1 -wave antenna, the radiation pattern has In real life tests, it is found that for a 4

great dependency on ground plane location. It is found that it is necessary for the node to be a foot or more above the ground plane for proper radiation; otherwise, at 3dBm of output power, the receiver is unable to receive when the nodes are more than a few feet apart, ush against the ground. It is dicult to measure and model such radiation patterns and strengths, so it is by trial and error, experience, and time that antennas are properly designed.

Figure 2-8: Vertically-aligned dipole antenna: elevation plane

31

2.2.6

TX Power-Aware Design Summary

The LMX3162 also has a TX PD switch that switches on and o the internal circuitry needed for the TX path. This power hook, in addition to the ones previously mentioned on the power amplier, constitute the power management control pins for the transmitter, and allow the transmitter to be oered as a black-box with these simple control lines so that the system and network designer may have easy access to these power-aware features.

2.3

Power-Aware Radio Receiver Architecture

Figure 2-9: Receiver Architecture

Figure 2-9 is a block diagram of the uAMPS radio receiver architecture. After electromagnetic waves are received onto the antenna, the antenna feeds to the matching network of the low noise amplier (LNA). 32

2.3.1

Low Noise Amplier

The key characteristics of the LNA are low noise and high linearity. For discrete LNA design, much like the PA design, care has to be taken for power supply ltering and ground layout. The matching networks will be described in Chapter 3. The circuit for the LNA is shown in gure 2-10. The LNA is implemented using Siemen s BFP420

Figure 2-10: Schematic for the LNA

RF silicon transistor. This transistor runs o of a regulated supply coming from the LMX3162. This regulated supply was designed to be used by an external LNA. In addition to being o-chip, the advantage of having the LNA power supply controlled by the LMX3162, is that a free power hook is available for use. mirroring the TX PD pin, There is a pin on the LMX3162 called RX PD that turns on and o the internal circuitry related to receiver circuits, as well. Looking at the schematic in gure 2-10, a walk-through of how this circuit works is as follows. Rb is chosen to provide proper collector-emitter biasing at 2V from a 3V power supply. The base current is set by Rbias to be Ic /beta, where Ic is desired to be 20mA and beta of the transistor is typically 80. The matching network to the left of the circuit contains a AC coupling capacitor to prevent bias current owing into the antenna. The resistor Rb can be tweaked, depending on the actual Vcc value, to obtain correct current values. The power supply for the LNA comes 33

from an internal regulator inside the LM X 3162; this regulator provides 2.7V . By reducing Rb , better performance for the LNA is obtained. A measured gain of 1012dB can be obtained in this fashion. With more complicated test equipment and setup, the actual S-parameters could be measured, and exact optimization of the LNA could be obtained; however, since this particular component has reliable specication sheet data and pre-measured data, it is possible to rely on this pre-measured data to optimize the circuit to a desirable quality. Another advantage of reducing R b , is that it minimizes the negative feedback eects that the output incurs at the input. When large currents are drawn in the transistor, the transient response of I c becomes large in magnitude. This causes a larger voltage drop across Rb , thereby reducing the voltage across Rbias . With the reduction in voltage drop, Ic is reduced through the reduction if Ib . Eectively, reducing Rb reduces the gain of this unwanted minor loop feedback eect [7] [20]. The noise factor of the amplier is at a minimal 1.5dB . The receiver sensitivity can be calculated using equation 2.2 [20].

Pin,min = 174dBm/Hz + N F + 10 log B + SN Rmin

(2.2)

174dBm/Hz is the amount of noise power per unit bandwidth that the source resistor delivers to the input. SN Rmin is related to a desired specication for biterror rate. This correlation is shown in gure 2-11. The bandwidth B is expressed in Hz , and is set from the beginning. Noise factor is the equivalent noise factor of the entire receiver chain. The noise factor of a cascade system is generally most highly impacted by the rst circuit block [9]. Thus, for a given desired BER, a SNR can be determined. Noise gure is constrained by and a sensitivity can be calculated from equation 2.2. Using the path fading equation (eq. 2.1), it is possible to obtain the approximate distances the wireless link can transmit. Linearity is determined by input matching over a frequency range, and minimal phase changes in the frequency on interest. Linearity is also aected by the non-linear Ic = Is eVbe /Vth equation. Emitter degeneration is a good negative-feedback technique 34

Figure 2-11: SNR vs. BER plot for binary shift-keying in multiple diversity L [21]

35

that increases linearity of the amplier over a larger signal swing. Large signal swings also change the values of junction and diusion capacitances of the transistor. IIP 3 is a good method that benchmarks the linearity of the circuit, while also allowing dierent ampliers to be normalized by their own 3rd -order intermodulation products so that their linearity performance may be compared to another amplier. IIP 3 is the amplitude of the input when the output fundamental component intersects the 3rd order intermodulation product of a two-tone input test. Usually a good approximation for IIP 3 can also be obtained if the 1dB compression point is known. Equation 2.3 shows this relation [9]. AIIP 3 = A1dB 10dB (2.3)

The 1dB compression point is the input at which the output gain drops 1dB below the ideal gain across all amplitudes of input. For this LNA, the 1dB compression point occurs at 12dB and IIP 3 at 8dB [20]. It is interesting to note in passing that this LNA can also be used as a power amplier, with maximum output gain of 12dB . Following that analysis, a more practical use would be to use it as a pre-amplier for the MAX2242 power amplier.

2.3.2

Demodulation Architecture

The LMX3162 is built to support heterodyne demodulation, with IF frequency selected at 110.6M Hz . Heterodyne systems are much easier to implement than homodyne (or direct-conversion) systems, because homodyne receivers have the following three problems, which by adopting a heterdyne architecture, can be avoided: [9]: DC osets in analog demodulated signal Even-order distortion Flicker noise. Figure 2-12 shows the heterodyne receiver architecture with corresponding frequencydomain plots to show image rejection, channel selection, and interferer rejection abilities of the receiver depending on the choice of a low or high IF frequency. For further 36

information on the tradeos and benets of a heterodyne architecture, see Appendix A for a systems-level explanation of the IF frequency, associated lters and circuits, and a comparison to direct modulation architectures.

Figure 2-12: Heterodyne receiver architecture with high IF frequency choice (top) and low IF frequency choice (bottom)

Image-Reject Filter The image reject lter is built by Murata, using high dielectric constant ceramics to provide ultra-high Q. The input and output impedances of this circuit are already matched to 50, so there is only the need for coupling capacitors and matched transmission lines. The bandwidth of this circuit is 84M Hz centered at 2.442GHz , giving a Q of 29. The bandwidth of the image-reject lter also helps determine the IF frequency that should be chosen. Since the IF frequency that is chosen is 110.6M Hz , it is easy to tell from gure 2-13 that the largest possible image magnitude that will be folded back onto the wanted signal by the mixer is more than 20dB below the 37

Figure 2-13: Freq vs. magnitude rejection plot [22]

magnitude of interest.

Mixer, PLL, SAW lter, and IF Amplier Since most of these components are on chip, their discussion will be brief. The mixer has two inputs, one of which takes as input from the received signal, and the second input takes the generated frequency from the PLL as input. The PLL frequency does the channel selection; basically, it generates a frequency that is 110.6M Hz less than the desired band to receive and demodulate. The output of this mixer will have sum and dierence frequencies; the sum would send the amplitude peak in the frequency domain to 5GHz, which will probably be attenuated anyway, since the world is lowpass in nature. The dierence will be at the IF frequency: 110.6M Hz . After this IF frequency is generated, it is desirable to put the signal through a very high-Q lter. High-Q lters can easily be generated by Surface Acoustic Wave (SAW) lters. This type of lter converts electromagnetic waves into acoustic waves by activating a piezo-electric structure. In gure 2-14, the grill-like objects are called inter-digital transducers (IDT) that are on a piezo-electric substrate, which transforms electromagnetic waves into acoustic waves, and vice-versa. The geometries are of key im38

Figure 2-14: Typical SAW lter implementation [24]

portance to determine frequency selectivity, delay, and fundamental frequency. The key advantage of SAW lters is their ability to produce an ultra-high Q and frequency selectivity. However, losses are usually associated with saw lters, due to the lack of directivity for acoustic waves exiting the IDTs. SAW lters also exhibit linear phase modeled as a pure delay. Sometimes SAW lters are also used to create delays. Because of this delay feature, the impedances of SAW lters cannot be measured by a traditional ohmmeter. However, since S-parameter analyses are based upon ratios of voltages, it is possible to measure S11 and S22 of a SAW lter and back-calculate the input and output impedances, respectively [24]. The SAW lter that is used for the IF frequency is centered at 110.6MHz, and has a 3dB bandwidth of 1M Hz . At +/-1.150M Hz of the center frequency, the attenuation is already 10dB . At +/-3.456M Hz of the center frequency, an attenuation of 40dB is achieved. The Q of this device is above 100. After the channel select lter processes the signal, it is sent to an on-chip IF amplier that gives 70dB of gain, and then fed into the discriminator circuit [23].

Discriminator and Demodulation Circuitry The discriminator circuit works as follows. From the IF amp, the signal is sent into the multiplier shown in gure 2-15. At one input to the multiplier is the original signal. The second input passes through a lter, which has the following transfer 39

Figure 2-15: Discriminator circuit

function: s2 RLCC s2 RL(CC + C )sL + R (2.4)

Figure 2-16 is the plot of the transfer function of equation 2.4. A description of the circuit follows. CC is internal to the LMX3162, and is set to be 1pF . The other passive components are all external. The capacitor that is above the varactor in gure 2-15 is set to be in the nF range, so that the eective impedance of that series capacitor connection is dominated by the varactor. The varactor is used to ne tune the resonant peak that the larger capacitor to the right of the series capacitor network and inductor form. The resonant peak is desired to be at 110.6M Hz so that the phases at 110.6M Hz -/+500kHz are at 180o and 0o respectively. This phase dierence can be seen on gure 2-16. The resistor R is not explicitly placed in the circuit, but comes from the Q of the inductor (i.e. - series resistance). Typically, an inductor has an associated series resistance. For narrowband analysis, the series R-L network can be broken into a parallel R-L network. The associated equations to do such a 40

Figure 2-16: Bode plot of equation 2.4

transformation are described below [10]. Qseries = wLseries Rseries (2.5) (2.6) (2.7)

Rparallel = Rseries (1 + Q2 series ) Lparallel = Lseries (1 + 1 Q2 series )

Thus, R is the same as the Rparallel calculated in equation 2.6. The tradeo is as follows. The higher the Q (smaller the series resistance), the more peaky gure 2-16 becomes. This peakiness translates to greater SNR, but also creates harmonic distortion, due to the 40dB /decade rollup and peaking of the circuit. Lower Qs decrease the SNR, but create less harmonic distortion, since the magnitudes at +/500kHz of the center frequency are likely to be more matched. The way the discriminator circuit works to recover the baseband signal is as follows. When the discriminator is tuned at 110.6M Hz , the phase sits at 90o at that frequency. The mixer takes two inputs. If the frequency that is generated from the IF amplier is at 110.1M Hz , the discriminator phase shifts the signal by 180o . This 41

means that the mixer inputs are directly opposite of each other in sign. When opposite sinusoids are mixed together, the result is a lower DC-average value at the output. If the frequency that is generated from the IF amplier is at 111.1M Hz , the discriminator essentially does nothing dramatic to the phase and frequency of the signal, so the two inputs to the mixer are the same. When two sinusoids of same sign are multiplied, then the average DC value of the output is high. Thus, by ltering out the carrier frequency between 110.1M Hz and 111.1M Hz , the baseband at 500kHz can be recovered, represented by the average DC value of the output of the mixer. Figure 2-17 shows the results of input frequencies at 110.1M Hz and 111.1M Hz [7].

Figure 2-17: Time domain plot of discriminator response to two frequencies

Figure 2-18 is a plot of the transmitted bits from a radio that is congured to transmit, the Gaussian-ltered Tx data, the recovered analog signal from the discriminator of the receiver radio board, and nally the recovered bits back into the digital domain. The digital bits are delivered to the Gaussian lter input via the Xilinx FPGA. The Gaussian lter feeds directly into the VCO, via a second control input that has a much lower f requency/voltage ratio. The Gaussian lter changes the square wave into a Gaussian symbol, which is more band-limited than the frequen42

cies produced by square waves. This reduces inter-symbol interference, and limits the bandwidth of transmission to the desired 1M Hz . The demodulated signal on the third channel is read at the output of the discriminator mixer. The recovered data can be compared to the signal on channel two. Finally, the digital bits are generated from a bit slicer circuit, employing a properly damped comparator. If the duty cycle of the recovered digital data is not 50%, it is possible to change the resistor value of Rslicer in gure 2-15 such that the comparator is given correctly-balanced voltages so that the slicer is able to recover bits correctly. The 2nd -order lter that is connected to Rslicer removes unwanted high frequency harmonics, so that the slicer does not decode wrong edges. The requirement for the DC-shift of the emitter-follower on the DC reference signal is necessary, because the demodulated data is also shifted by a Vbe drop of a transistor. The DC reference signal, as seen in gure 2-15, is generated by a low-pass lter. This low-pass lter aects the settling-time of the recovery circuitry, as it takes approximately 4 of the time constant of the low-pass lter to settle to the correct DC-average value. The other surrounding circuitry is the analog feedback loop to control the varactor and automatically tune the circuit to 110.6M Hz .

Figure 2-18: Key signals in tx-rx wireless link

Going back to gure 2-15, the varactor can be implemented in two ways: a physical hand-tuneable variable capacitor, or the series connection of the two capacitors with a 43

varactor diode. The reverse-bias voltage drop of the varactor changes the capacitance of the diode. The graph in gure 2-19 shows the typical capacitance vs. voltage characteristics of the varactor.

Figure 2-19: Varactor diode characteristics [25]

Because the curve in gure 2-19 is not constant, and there are inconsistencies in reference oscillators, etc., it is of great advantage to remove the hand-tuning capacitor and replace it with a diode varactor embedded in a feedback loop to automatically tune the circuit. The feedback circuit follows from gure 2-15. The values for the circuit are as follows: Rbias1 = 5.86k Rbias2 = 3.470k Ccl = 10uF Ri = 1k Rf = 10k Rf ilt = 0 Ctopof diode = 4.7nF Cdiode = 2 9pF Ctank = 18pF 44

L = 68nH Rdc = 5k Cdc = 2.7nF RDCshif t = 1k Rslicer = 1k

A brief intuition on how the feedback loop works is as follows. Beginning with the discriminator output, there will be some baseband Gaussian- modulated signal centered around 500kHz . there is also a DC oset associated with this signal. The low pass lter formed by RDC and CDC is set at 11kHz (the plots that reveal this will be described in the detailed analysis to follow). This eectively lters out the high frequency component of the discriminator output, and captures the DC oset value, but still containing low frequency (below 11kHz) noise. The interesting problem to note about this lter is that if the lter pole is set to be very low to lter out more of this unwanted noise, the transient settling time increases, since setting time is the
1 . If the pole of the lter is increased to decrease settling time, it same as 4 P oleLocation

is obvious that this would allow more ripple to appear at the ideally DC voltage level. This problem will be dealt with later. Continuing down the signal path, the transistor that performs the DC shift is important, because the LPF transistor introduces a V be drop to the DC value of the recovered Gaussian pulses. In order for the comparator to slice the discriminator output at the midpoint, the DC osets for Vdc and the ltered discriminator output must be the same. As said before, if the DC osets are not exactly the same and the output of the comparator is not 50% duty-cycled for a 1-0-1-0-1-0 data transmission, then Rslicer can be changed slightly, to twiddle the bias current through the transistor so that the Vbe drop will be the correct value to produce good results. The reason the resistor at the base of the DC shift transistor is not adjusted is because that transistor and those circuits are embedded in a feedback loop, which would cancel the very changes that need to be made. The opamps that are used are fromNational Semiconductor, and are their high performance JFET-input, ultra-high gain-bandwidth product LM6152 opamp [26]. The frequency response for 45

the op-amp is shown in gure 2-20. If the opamp is put into unity feedback to act as

Figure 2-20: LM6152 Frequency response [26]

a buer, it is easy to tell from gure 2-20 that the circuit is able to operate well up to 20M Hz . Thus, it is possible to assume that the follower, or even a gain of 10 stage that is built with this opamp, is reliable. No other dynamics need to be included from this opamp, due to its high-bandwidth response relative to the unity-gain frequency of the entire loop, which will be discussed in the detailed description [26]. Opamp A1 is put into a unity gain conguration. The voltage that is produced by Rbias1 and Rbias2 is the DC oset voltage that the discriminator and VDC should be at. It is possible to use this DC voltage as a reference, instead of trying to correct the frequency error that the tank generates. The reasons to use this voltage are: the voltage is already here to analyze analyzing absolute frequency oset does no good to actual performance/ability to demodulate the IF to baseband, because dierence in oscillator frequencies may cause a shift in the IF frequency analyzing the DC oset is the farthest variable before entering the slicer that we can embed into a feedback loop to gain noise immunity characteristics of feedback loops. 46

Next, it is interesting to note that what is generated at the input into opamp A 1 are two-fold. Firstly, it is to generate and buer a solid reference for what V DC should be. Secondly, it is to include the low frequency components of the real VDC , so that when the comparision (error generation) of VDC to this reference is made in A2 , the low frequency ripples will not cause the output of the subtractor to oscillate and/or saturate. Opamp A2 is set at a gain of 10, using resistors Rf and Ri . Finally, Rf ilt is set to be 0. The idea of Rf ilt is to allow for dominant pole compensation, if further compensation is needed. A2 , as stated before, also does the subtraction/error generation, and amplies the signal. This subtraction is positive so that is why the positive terminal of the opamp is not to ground. The reason the subtraction must be positive, is that the sign of the gain for the diode voltage to the discriminator output is negative. When the signal is changed from the varactor voltage to the discriminator output, the feedback loop is closed, a negative sign is inserted into the loop, and there is a control circuit that exists to set the DC value of VDC , and reected back to the discriminator output, to a useful value so that the data can be correctly sliced and regenerated into the digital domain by the comparator that feeds to the Xilinx FPGA. The most interesting part of the feedback loop is guring out the transfer function between the discriminator output and the varactor voltage. An experiment is set up to analyze this transfer function. In this experiment, one radio node is set to constantly transmit at a set frequency, and the LO of the receiver is set to be 110.6M Hz lower than the transmitter frequency. No data is transmitted; just the fundamental frequency. Secondly, a function generator is connected to the varactor voltage. The correct DC value is generated to the varactor so that the discriminator output sits at 1.5V , the sweet spot for maximum output demodulation amplitude and phase discrimination. Then, a sinusoidal signal is added onto the DC voltage of the varactor. At low frequencies, when analyzing the AC signal at the discriminator output compared to the AC signal at the the discriminator output, a gain of -8 is observed. Figure 2-21 shows a measurement made at low frequency. The input frequency is

swept at the diode until around 700kHz , when a noticeable drop in gain begins to creep into the circuit. Figure 2-22 shows this pole location in phase and magnitude. 47

Figure 2-21: Plot of AC voltage applied to varactor (C2) and AC voltage produced at discriminator output (C1)

Figure 2-22: Plot of AC voltage applied to varactor (C3), AC voltage produced at discriminator output (C2), and VDC (C1)

48

Apparently, there is also some delay in response of discriminator output, which translates to an est time delay in the frequency, which basically adds a linearly decaying phase term, which may be deleterious at high frequencies, reducing phase margin unnecessarily. A plot of this phenomenon is in gure 2-23. It can be seen

Figure 2-23: Plot of transient step response from varactor (C2) to discriminator output (C1)

that the time delay is approximately 100nS for a worst case estimate. However, at 1M Hz , the negative phase shift produced by such a delay is only 15o . As long as the phase margin of our system is greater than 20 without the delay element taken into account, this feedback loop will function properly. Understandably, this leaves the system with a phase margin of 5 if the delay factor is introduced; however this assumes that the crossover frequency is at 1M Hz for this to be true. Keep in mind that crossover will likely be at a lower frequency, due to higher-order eects. When crossover is at lower frequencies, the phase from delay is correspondingly reduced. The higher-order eects that were spoken of include poles at higher frequencies, which are dicult to see. The system is denitely nonlinear at higher frequencies, as can be seen by the following plot of varactor input and discriminator output at 1M Hz . It can be somewhat made out that there is another phase shift beginning to 49

start at 3M Hz . Thus, it is prudent to model another parasitic pole at 1M Hz , to help with calculations and estimations. The reasons for going to a lower frequency to estimate the pole are two-fold. Firstly, it is because non-linear eects are beginning to show up already at 1M Hz , and secondly, it gives a conservative estimate for stability. Figure 2-24 is a plot that shows the nonlinear eects. The best guess for the source of these nonlinearities is the slew-rate of the mixer output is showing dominating eects on the signal.

Figure 2-24: Plot of varactor input (C2) to discriminator output (C1)

Using root locus analysis, it is possible to see how much gain can be added to the system to improve the reduction in error, while staying below a certain point so that the closed-loop poles wander into the RHP. Figure 2-25(a) is a plot that helps to determine the correct gain value so that the closed-loop poles (same as the open-loop poles) will be at the gain that is set. By looking at the shape of the root locus plot and where the designer desires the poles, it is possible to estimate phase margin from this plot, using , and equations 2.10 and 2.11. Finally, in gure 2-25(b), the plot of the open-loop transfer function with the gain of 10 is shown. The gain of 10 is chosen from analyzing gure 2-25(a), because it oers fast response time (poles around 500kHz), and oers enough phase margin so that the 50

(a) Root-locus of open-loop transfer function

(b) Bode plot of open-loop transfer function w/gain of 10, as chosen from analysis of 2-25(a)

Figure 2-25: Root-Locus and Bode plots of feedback system

51

system will still be stable. The approximate settling time of a circuit with poles at 500kHz can be estimated using well-known equations. In lab, the correct value of gain was found by putting a potentiometer in the feedback path, and adjusting it until the system became stable so that the DC voltage could be automatically set. The gain at which the system became unstable was close to 15. The drawback of such low gain in the loop gain of the system results in an error supression of only 1/gain. however, since our variable of interest embeds so many intermediate voltages and stages, a 1/gain in resolution accuracy is denitely tolerable. The only drawback that this varactor circuit has is that the changing signals that are at the cathode end of the diode aect the diode voltage drop. These changes in diode voltage drop work in such a way that reduces the magnitude of the recovered Gaussian symbols when compared to the recovery shapes of a hand-tuned varactor. Bit Recovery As mentioned before, the comparator takes the VDC voltage and the low-pass ltered discriminator output and generates the digital demodulated signal.

2.3.3

RX Power-Aware Design Summary

As with the TX PD pin in the transmit path, the LMX3162 also has an RX PD pin for the on-chip receiver circuits to powerdown the receiver. For the external circuitry related to the receiver, an external 3V regulator supplies power to the opamps, comparators, transistors, and bias legs. The regulator has an on/o switch, which is used as the power-hook to the o-chip receiver components.

2.4

Phase-Locked Loop

Discussion regarding the design of the phase-locked loop was deferred until both the transmit and receiver paths were discussed, since it is common to both circuits. An internal switch allows both the RX and TX paths to share the same PLL. 52

The National Semiconductor design produces a frequency that is half of the nal transmit frequency. This is benecial, primarily to avoid load pulling. Load pulling occurs when the radio is placed in transmit mode, and the PLL frequency is pulled and shifted due to the power amplier radiating energy onto the bandwidth of interest of the PLL, which leaks RF energy into the loop, thereby corrupting the signal of interest. By making the PLL frequency a factor of two lower than the RF frequency, load pulling is avoided. Secondly, this architecture fosters lower power consumption, due to the lower operating frequency of a large portion of RF circuitry. The actual architecture for the PLL is in gure 2-26 [7]. The 3rd-order Gaussian lter is shown

Figure 2-26: Frequency synthesizer circuitry

here for purposes of accurately portraying the VCO. The VCO is involved in the PLL, but also allows data to be modulated into the PLL, similar to intentional noise injection, through an intentional second input for the VCO. The phase-locked loop, outlined in dotted-orange in gure 2-26 is not contained in one integrated circuit. The vertical dotted line shows the division of circuits that are on-chip and o-chip. The loop lter is o-chip because of the low cuto frequency of the PLL, which requires large capacitor values that are costly to build in integrated circuits. The phase-locked loop begins at the 10M Hz reference clock. A reference clock is 53

generated, and the frequency error, i.e. phase error, is detected by the phase detector, from a signal that is fed-back from the output. The phase error is sent to the charge pump to amplify this error. The loop lter is used to capture the low frequency average of the phase error and then sends the average error signal to the VCO. The output of the VCO is the actual frequency that is used to transmit RF, after multiplying the VCO output frequency by two. The divide-by N counter divides the frequency of the VCO, and feeds it back so that the phase detector can produce an error signal regarding phase of the reference clock as compared to the phase of the feedback frequency. The divide-by M counter in front of the 10M Hz clock sets the resolution at which the frequency can be multiplied by, when it hits the divide-by N counter. The divide-by N counter provides the frequency multiplication-by N because the error signal is forced to be zero, as is with all summing junction outputs for negative feedback loops [7].

Figure 2-27: PLL block diagram

Figure 2-27 is a block diagram of the PLL feedback loop. When there is a feedback loop, stability is always an issue. One of the many ways to analyze stability is to observe the open-loop characteristics (otherwise known as the loop gain) of the system. When analyzing the loop gain of the system, the phase detector and charge 54

pump gains are absorbed into K . K has units of volts/phase. A capacitor is at the output of the charge pump, as seen in gure 2-26, and noted by the 1/s in gure 2-27. This eectively dierentiates the phase. For clarity, equation 2.8 is the transfer function of the loop lter in gure 2-27 is computed. H (s) is equation 2.8 2 multiplied by s. 1 R 2 R 3 C 2 C 3 s 2 + (R 2 C 2 + R 3 C 3 )s + 1 s (R3 C3 s + 1)(C1 C2 C3 R2 R3 s2 + (R2 C2 (C1 + C3 ) + R3 C3 (C1 + C2 ))s + (C1 + C2 + C3 )) (2.8) Since frequency is the dierentiation of phase, the units of the signal that is after the integrator are volts/f requency . Since the VCO can be characterized as a gain block that is Kvco /s which has units of f requency/volts, the entire forward path is a unitless gain. However, it is important to note that the variable of interest is phase. It is possible to treat phase as the new variable (replacing voltage in most traditional feedback loops), and thereby apply feedback principles, such as phase margin3 and monotonically decreasing magnitude4 characteristics to ensure stability of this feedback loop. The radio chip handles the counters, phase detector, and charge pump gains for the PLL. There are two current settings for the charge pump output: 1mA and 6mA. The extra 5mA oers an extra 35.8dB of gain to the loop gain. When designing for a unity gain bandwidth of 6KHz and a phase margin of 30o , using an 3rd order lter with a low charge pump current of (1mA), the open-loop characteristics of the PLL still maintain stable closed-loop operation, even if the 6mA, high charge pump current is chosen. The graphs in gure 2-28(a) and 2-28(b) show the open-loop frequency response, in magnitude and phase margin, of the low and high charge pump currents, respectively. The graphs are taken from National Semiconductor s Calc
This equation is daunting, but in the implementation of the loop lter, National Semiconductor has provided a program called Calc Filter that calculates the correct capacitor and resistor values for given loop lter specications. 3 Crossover frequency is the frequency at which the magnitude of the open-loop transfer function is 1. Phase margin is the amount of negative phase that the system lacks at this frequency, until the phase reaches -180o . 4 Monotonically decreasing basically means: the derivative of the magnitude plot, after a certain frequency, is non-positive.
2

55

Filter program, which helps expedite the design of the phase-locked loop. Figures 2-28(a) and 2-28(b) are the open-loop frequency plots (L(s)) of the phase-locked loop, in magnitude and phase margin [7]. From analyzing these plots, it is apparent that the gain margin5 for both of these plots is quite large, and denitely above 3. The importance that the gain margin be above 3 will be explicit from the below discussion. It is also notable that the loop lter capacitors and resistors were not changed in generating these two plots; only the charge pump gain is changed. In both plots, the values of the resistors and capacitors correspond to the loop lter topology in gure 2-27. The phase margin and crossover frequency of gure 2-28(a) is 30o and 5.7kHz , and for gure 2-28(b), the same specications are 56o and 20kHz , respectively. Again, the change in charge pump current basically shifts the magnitude plot up by 35.8dB [7]. Equation 2.9 is the closed-loop transfer function of the PLL. L(s) in equation 2.9 is the same as the plotted L(s) in gures 2-28(a) and 2-28(b), and N is the same N that appears in gures 2-27, 2-28(a), and 2-28(b). L(s)N 1 + L(s)

(2.9)

The lock time of the PLL is the same as the settling time of the closed-loop transfer function. The closed-loop 3dB bandwidth can be estimated from the open-loop transfer function. Using the gure 2-28(a) as the L(s) characteristics, it is obvious that for frequencies below 6kHz , the denominator in equation 2.9 is dominated by L(s). Therefore, the 1 can be approximated away, leaving the closed-loop transfer function to be a constant gain N from 0Hz to 6kHz . The frequency at which L(s) = 1 is the 3dB bandwidth (wh ) of the closed-loop system. Since the phase margin (p.m.) is also known to be 30o , it is possible to use equations 2.10, 2.11, 2.12, and nally 2.13 to obtain the 2% settling time [8]. 1 sin p.m.

Mp =

(2.10)

5 Gain margin is the amount of additional gain one can add to the loop gain until the phase margin is zero.

56

(a) L(s) for low charge pump gain: 1mA

(b) L(s) for high charge pump gain: 6mA

Figure 2-28: Open loop response to PLL given dierent charge pump gains 57

Mp =

1 2 1 2 2 4 2 + 4 4 4 wn
1/2

(2.11) (2.12) (2.13)

wh = wn 1 2 2 + ts =

Before using equation 2.10, it is important to make sure that the gain margin is above 3. In the present case, it is; therefore, the approximation of phase margin to the degree of stability parameter (Mp ) is accurate. wh is the 3dB bandwidth, which was reasoned to be equivalent to the open-loop unity gain frequency. and wn are the damping coecient and natural frequency for the closed-loop system, respectively. The expression for ts gives the time it takes for resonances to die down to 2% of nal value. When using all of these equations, the nal settling time for low charge pump gain, is 386S . If the charge pump is congured to be high gain, then the settling time can be reduced to 90.6S . Figures 2-29(a) and 2-29(b) are the transient plots of the PLL with low charge pump gain and high charge pump gain, respectively. As seen from gures 2-29(a) and 2-29(b), the settling time estimates from feedback techniques match quite well with the actual responses. It is also curious to note in gure 2-29(b), the high frequency oscillations superimposed upon the low frequency transient that eventually dies out. The high frequency comes from exciting nondominant, lightly damped complex conjugate poles that probably are closer to the jw axis, due to the increased loop gain. Generally speaking, the lower the frequency that the loop lter is set, the longer the locktime, but the less the PLL will suer from phase noise due to unsuppressed high frequency uctuations that may be coming out of the loop lter that will then modulate the VCO. The locktime is usually around four time constants of the closedloop time constant of the loop, to achieve 98% settling to nal value. Theoretically, this frequency synthesizer can be improved just by changing the charge pump gain to provide fast lock time, and switching to the low gain to provide frequency stability. As of now, this experiment could not be nished in time, but is something that could 58

(a) low charge pump gain

(b) high charge pump gain

Figure 2-29: Transient responses of VCO control voltage for given charge pump gains

59

be explored in the near future.

2.4.1

Power-Aware Design for PLL

The only power control that is to the PLL comes from a regulator that supplies the 3V power source to the chip. The control to this regulator is also tied to the powerdown pin of the LMX3162. Therefore, whenever the LMX3162 is on, the PLL will also be operational. This is a time-saving feature as well, since as long as power is supplied to the LMX3162, even when the chip is not enabled and put into sleep mode, the chip still holds the previous program bit values.

2.5

Power States for Radio Transceiver

The Xilinx FPGA serves as the Link Manager Interface (LMI) for the radio to the processor board, and also the core digital component that controls all of the power states of the radio. The coding for the Xilinx FPGA was done by [3]. Because of the LMI, the radio can appear like a block box to the processor board [4].

2.5.1

Control Hierarchy

The LMI is powered up by the processor board with one control pin. This control pin is connected to the 1.8V power source that power the core of the Xilinx. The I/O pins of the Xilinx constantly receive 3.3V from the processor board; however, as long as the 1.8V is on or o, dictates whether the entire Xilinx FPGA consumes power or not. The same control pin to the 1.8V DC/DC converter also is connected to the power supply of the analog clock generator and corresponding comparator to generate square pulses. From there, all of the control pins to the rest of the radio, including power hooks, external switches, program lines for the LMX3162, are all connected to the Xilinx FPGA. 60

2.5.2

Power States Analysis

The following gure is a bar graph of power, according to the useful states that the radio can be placed in. The last six power states which are in dBm represent

Figure 2-30: Ideal power consumption in each node state

the states for the dierent transmit power output levels of the radio. The state labeled T x is the power consumption of the transmitter without the power amplier. The usefulness of this state in practical use is debatable, but it does well to show the relative power consumption of the nominal transmit path with out the power amplier as compared to transmission with the dierent output power levels of the PA. It reveals the potential impacts of a scalable, highly ecient power amplier can have on wireless sensor networks, and power-aware radio design. It is important to note that the of f state should ideally draw zero power so that unnecessary power loss is avoided. During the idle state, only the PLL and radio chip are on; the T x and Rx paths are shut down, though. During this state, the PLL can be programmed via the LMI. During the settling time of the PLL, this state is 61

the lowest power state that exists to give the PLL time to lock. When the 100S or 400S are over, the radio can then be immediately placed into the Rx or T x modes. Finally, the receive state is used only when the radio is receiving.

62

Chapter 3 Impedance Matching Circuits and Practical Implementation

3.1 Impedance Matching Circuits

(a) Upwards impedance matching

(b) Downwards impedance matching

Figure 3-1: Two common types of impedance matching circuits [10]

Impedance matching is highly important in RF design. The idea of impedance matching relies on narrowband operation, and the (ideally) lossless properties of capacitors and inductors. Impedance matching techniques take the impedance of a given network and transform that impedance through a capacitor and/or inductor network such that the impedance of the load to the network and the impedance of the transformed network are conjugately matched, for maximum power (not voltage) 63

transfer [11]. Examples of impedance matching are in gures 3-1(a) and 3-1(b). The circuit in gure 3-1(a) is an upwards impedance transformer, and the circuit in gure 3-1(b) downwards impedance transformer. The L C network will transform the impedance looking to the left of both loads be matched to RL , at a given frequency. Likewise, the impedance looking to the right of RS is the conjugate of RS as well. When the impedances are matched, the power dissipated in the source resistance and load resistance are the same (whereas the conjugate matching makes the imaginary part of the impedance go away). It so happens that when circuits are conjugately matched, the circuit is transferring the maximum amount of power to the load from the source. For gures 3-1(a) and 3-1(b), the values for L and C impedance matching at 100M Hz are 79.57nH and 15.91pF respectively [10]. There are a variety of ways to calculate the correct matching component values and create the correct matching circuits (as there are many paths to matching and each having dierent broadband frequency responses and quality factors), but the most simple way is to use a Smith Chart. The Smith Chart was conceived in the 1930s by Philip Smith, while he was at Bell Labs. The Smith Chart takes advantage of conformal mapping and geometry of conformally-mapped graphs to allow an RF designer a quick tool to perform a variety of RF circuit calculations, including impedance matching. The following page is a copy of a Smith Chart, courtesy of the Univeristy of Florida EE department. Chris Bowicks RF Circuit Design book oers a detailed overview of the origins, other usages, and more examples of the Smith Chart in use [11]. Smith Charts that have both the impedance ane reactance circles are called ZY Smith Chart. See reference [11] for a ZY Smith Chart. This type of Smith Chart is of great use to the circuit designer, as it allows quick switching between impedance and admittance. Figures 3-2(a), 3-2(b), 3-2(c), and 3-2(d) outline the dierent circles that are on the ZY Smith Chart. A practical way to look at and use the ZY Smith Chart for impedance matching is described as follows [11].

64

(a) Constant resistance

(b) Constant conductance

(c) Constant tance

reac-

(d) Constant susceptance

Figure 3-2: Types of circles in ZY Smith Chart

To plot an impedance, normalize the impedance by factor N (usually 50). Locate the circle of constant resistance (g. 3-2(a)) and conductance (g. 3-2(b)) on the ZY Smith Chart. Plot the point. To plot an admittance, multiply admittance by normalization factor N (usually 50). Locate the circles of constant conductance 3-2(b) and susceptance 3-2(d). Plot the point. To extract an impedance from the ZY Smith Chart, nd which circles of constant resistance and reactance it is on. Multiply the complex expression by the normalization factor N. To extract an admittance from the ZY Smith Chart, nd which circles of constant conductance and susceptance it is on. Divide the complex expression by the normalization factor N. 65

If a non-dissipative element (inductor or capacitor) is placed in series from the output port of an impedance Z , the impedance that the element adds will be reactance. If the value of reactance is R, then the impedance looking into the element towards the port will be Z + Ri. Notice that the element causes the impedance of the network to travel upwards (inductive) on the ZY Smith Chart, along a circle of constant resistance, so that it covers R/N reactance on the chart. If a non-dissipative element (inductor or capacitor) is placed in parallel with the output port of an admittance Y , the admittance that the element adds will be susceptance. If the value of susceptance is S , then the new admittance looking into the parallel structure will be Y + Si. Notice that the element causes the admittance of the network to travel down (capacitive) on the ZY Smith Chart, along a circle of constant conductance, so that it covers SN susceptance on the chart. As a summary, the following equations show how to extract real capacitor and inductor values from traveling on the constant resistance/conductance curves [11]. A series-C component travels counterclockwise on a constant resistance circle: C= 1 wXN (3.1)

A series-L component travels clockwise on a constant resistance circle: L= XN w (3.2)

A shunt-C component travels clockwise on a constant conductance circle: C= B wN (3.3)

A shunt-L component travels counterclocwise on a conductance circle: L= where w = 2f , 66 N wB (3.4)

X = the reactance read from the chart, B = the susceptance read from the chart, N = the number used for normalization of the original impedances.

3.2

Practical Impedance Matching

Some general rules for success in impedance matching are to remember that capacitors and inductors are limited in size, and have parasitic components (both other inductances, capacitances, and even series/parallel resistances). When planning a path for matching, it is important to not span much conductance/susceptance for series-C or shunt-L components, or span too little conductance/susceptance for series-L and shunt-C components, because the extracted inductor and capacitor sizes will be very small. Its important to check the self-resonant frequency of the components that are used for these circuits, and make sure that the frequency of interest for matching is a decade away in frequency, from the self-resonance. However, for the ambitious, it is possible to measure the parasitic resonance, and utilize the parasitics by absorbing them into the matching network. Most of the time, matching networks are composed of an inductor and capacitor in some conguration. However, if the Q of the matching network is of concern (if the engineer is designing for wideband systems, and a low Q is desired), 3 component matching networks are frequently used, so that matching frequency and Q can be determined independently [11].

3.3

Transmission Lines

It is to the frustration of RF designers that wires at high frequency are no longer ideal wires. Instead, the normally negligible amounts of parasitic capacitance, resistance, and inductance begin to aect the signal, as well as transmission line eects; currents take a nite amount of time to travel down a wire. Thus, attention must be paid to Maxwells equations once again, since the low-frequency approximations (KVL and KCL) no longer hold true. For practical purposes however, the results of solving 67

Maxwells equations will be presented. If further detail is required, [13] is a great resource. A basic transmission line is shown in gure 3-3.

Figure 3-3: Transmission line

The two key parameters of a transmission line are the characteristic impedance, and length of the transmission line. Of secondary importance is loss tangent, but it is prudent to assume the use of low-loss dielectrics in implementation. Actual real transmission lines will be analyzed in the next section. The characteristic impedance is calculated from equation 3.5. Zo = L C (3.5)

L and C are in H/m and F/m, respectively, and are dierent for each physical implementation of a transmission line (coax, coplanar waveguide, microstrip, etc.) From the length, the velocity of propogation can be calculated as shown in equation 3.6. v= 1 LC (3.6)

The units for the velocity of propogation are m/s. The velocity of propogation shows how fast a wavefront travels down a transmission line. This property of transmission lines can lead to interesting time-domain circuits and pulse generators. Also as a passing observation, this delay characteristic is crucial in the theory of designing high frequency, wideband travelling wave ampliers [13]. Transmission lines begin to be interesting when actual elements are attached to the ends, in series, or in parallel to the transmission lines. Figure 3-4 motivates discussion of an example. 68

Figure 3-4: Loaded transmission line

The voltage and current equations for sinusoidal excitation of this transmission line in equations 3.7 and 3.8, are actually the maximum voltage and current amplitudes given at displacement d, instead of actual voltage, with regard to time. V (d) = A1 ejd (1 + o e2jd ) I (d) = A1 jd e (1 o e2jd ) Zo (3.7) (3.8)

This envelope of voltages that we see across the transmission line is also known as the standing wave. The phase that comes from the sinusoidal time function is expressed in equations 3.9 and 3.10. It is convenient and easy to cast in time dependence into the space equation. V (d, t) = {V (d)ejwn t } I (d, t) = {I (d)ejwn t } (3.9) (3.10)

If the reader desires proof of these equations, J.A. Kongs book has detailed derivations. For equations 3.7 and 3.8, the variable o , the reection coecient (which is the ratio of how much the forward travelling wave is reected back to the source) can be found through equation 3.11. o = ZL Z o ZL + Z o 69 (3.11)

 is also 2/. This quantity has many names, some of which are wave vector, propogation vector, or simply the k vector. k can also be found by equation 3.12, k=w where w = is frequency of signal in rad/sec, = is permeability of substrate, = is permittivity of dielectric. Generally, all of the above values are given in a system, except for the variable A 1 . However, after a few calculations and knowledge of the input impedance looking into the transmission line from d = l, it is solvable. Since V = IR, it is possible to solve for R, and obtain the impedances at all d down the transmission line. When equation 3.7 is divided by equation 3.8, Z (d) is found to be equation 3.131 [13] Z (d) = Zo ZL + jZo tan d Zo + jZL tan d (3.13) (3.12)

Using equation 3.13, it is possible to nd Z (d = l), and in turn, use Z (d = l) to form a voltage divider with RS . In this way, V (d = l) is shown in equation 3.14. V (d = l ) = V S Z (d = l ) Z S + Z (d = l ) (3.14)

Following from gure 3-4, l = /4. The nal expression for V (d = /4) is shown in equation 3.15. V (d = /4) = VS
2 Zo 2 ZS ZL + Z o

(3.15)

Now, if attention is turned back to equation 3.7, it is possible to plug in the value of V (d = /4) in place of where V (d) is, and nd the value of A1 . The result is in

An interesting note is that since the transmission line is quarter-wave in length, the impedance looking into the transmission line at d will be open circuit, if ZL is a short, and short circuit if ZL is an open. This is why RF designers watch out for quarter-wave transmission lines.

70

equation 3.16. A1 = V S
2 Zo 2 )(1 ) j (Z S Z L + Z o o

(3.16)

Now, fully-dened equations characterizing the current and voltage standing waves on the transmission line are found. Another interesting measure to look at, is the voltage standing wave ratio (VSWR). The equation for VSWR is basically the same as the maximum magnitude of the standing wave along the transmission line over the smallest magnitude of the standing wave along the transmission line. This basically measures how well the circuit is matched. If the load and transmission line are matched well, then the VSWR is 1; even the horric quarter-wavelength line problems do not exist. If ZL is the same as Zo , the transmission line has no uctuations in standing wave ratio, and the transmission line looks like an innite length transmission line, since the load is terminated by the lines characteristic impedance, making the reection coecient at the load to be zero. Low VSWR (lowest being the value of 1) means the circuit is matched very well. High VSWR means there are impedance matching problems. The equation for VSWR can also be expressed as equation 3.17 [13]. V SW R = 1 + | o | 1 | o | (3.17)

All of these ideal characterizations of transmission line theory are brought into real life practice by people who have run rigorous experiments and come up with algebraic (non-Maxwellian based) equations that approximate known transmission structures. The next few sections will outline popular planar transmission lines that are used today [14].

3.3.1

Microstrip Lines

A diagram of a microstrip line is in gure 3-5. The substrate is a dielectric, with permittivity of . Usually, a substrate using a berglass material called Rogers 4000, or a cheaper, but more lossy FR4 is used. For frequencies around 1GHz, FR4 is a good candidate for a substrate, but for higher frequencies, the material becomes too lossy to use. M1 is the top conducting plate, which is where the signal is applied, 71

Figure 3-5: Microstrip line example

and M2 is the bottom conducting plate, which is the ground plane. The width of the line, W , is critical in determining the characteristic impedance, as well as the distance h that M1 is above M2 . The length of the transmission line, L, is used to calculate delay, loss, and impedance rotation that the load impedance goes through, after being attached to a transmission line for length L [14]. In the most ideal case, to solve for the critical values of a microstrip transmission line, a computer solving Maxwells equations at each corner and point would be used to obtain an exact solution. However, this method is too dicult to use each time. Instead, by making the quasi-transverse electromagnetic (quasi-TEM) wave approximation for the electric and magnetic elds around the transmission line, it is possible to measure test structures, and derive a best-t algebraic equation for parameters like Zo , k , and v [14] [15]. TEM propogation occurs when the electric and magnetic elds are transverse to the direction of the waveguide. In other words, the vectors of electric and magnetic elds do not radiate in the direction of L in gure 3-5. However, quasi-TEM transmission is due to the fact that the substrate below M1 is dierent from the substrate above M1 . This causes dierences in propogation constant (k ) for waves above and below M1 . The quasi-TEM approximation lumps these two propogation constants into one, and makes the necessary non-linearity adjustments by making to be frequency

dependent, thereby changing Zo and k . There is a bit of longitudinal propogation, but as the frequencies that are propagated down the microstrip are higher, more of 72

the energy that is propagated (in terms of electric and magnetic elds) become more and more concentrated within the dielectric. Therefore, at higher frequencies, the effective becomes closer to of the dielectric. However, as frequencies become higher, the higher-order modes of propogation (i.e. - longitudinal components of k ) also become signicant and the quasi-TEM approximation no longer holds. The equations for eective permittivity cuto frequency, and many other variables associated with microstrip lines are described in Appendix B [14] [15]. Laying out microstrip lines is of key importance as well. Printed-circuit board (PCB) manufacturers have many ways of constructing boards, dierent tolerances, and dierent substrates. It is important to communicate with the PCB manufacturer, and to ask about the prepreg process to be avoided when building the thickness stack for the layer of substrate between M1 and M2 . Also, when laying out PCBs, if the amount of space that is allotted for transmission lines is scarce and bends need to be made to t all of the circuits onto a single board, mitered bends are a good candidate for low loss corners. Figure 3.3.1 illustrates this method [14]. The loss generated from

Figure 3-6: Mitered corner

such a bend is at a minimum when equations 3.18, 3.19, and 3.20 are fullled. b 0.57w 73 (3.18)

2.5 0.5

15 2.0

(3.19) (3.20)

w h

3.4

Power Amplier Impedance Matching

Layout is of great importance in RF circuit design. Ground planes and ground connections should be properly and solidly built. If coplanar waveguide transmission lines are used, then vias should be scattered copiously throughout the board to provide a solid ground connection to the top-layer ground plane. Power delivery and management is also very important for RF amplier design. If the power lines are not properly isolated, crosstalk would dominate the circuit and cause oscillations. Well-placed and frequent ltering of the supply line does well to minimize oscillations. Bypass capacitors should be placed near the point where power is fed to the circuit, to avoid dangerous feedback loops that are formed by the power connections, especially in multi-stage ampliers that are on the same power supply line. Furthermore, by avoiding the use of a power plane for the radio circuits and instead using isolated traces to deliver power, the eects of feedback loops from the power connections will be further reduced [19]. As for the signal, impedance matching and microstrip lines are used to deliver the signal from the LMX chip, to the PA, and out into the antenna. Figure 3-7 shows the matching networks that are used. It is useful to say that the inductor match on the output of the PA is not entirely determined by the needs of the matching network; it also contributes greatly to the power gain of the PA via its Q and inductance value. Keeping the leads short is also of great importance. In the ideal case, once a line is matched to 50, theoretically it is possible to draw in innitely long transmission line with characteristic impedance of 50 and be perfectly matched wherever the chosen termination into a 50 load is desired. However, since microstrip lines and other transmission lines are made of non-ideal insulators and conductors, there is loss; when circuits are mismatched, there are reections, and possible problems dealing with high VSWR. Sometimes ampliers have a ceiling for the S22 parameter. If 74

Figure 3-7: Matching network for LMX2242 power amplier

the matching circuit sends back too much power to the amplier output, it is quite possible to destroy the PA chip. Secondly, it is important keep the leads short to minimize antenna eects of the transmission lines, especially when the output is out of phase by 180o from the input. When the output is out of phase in this way, the feedback loop that is created will be unstable [19].

Finally, when laying out microstrip transmission lines on limited area boards, the chamfered bends described in the transmission line section do well to minimize losses.

A nal caveat is that the inductor that is used in the matching network at the output of the power amplier is a xed inductor of 10nH . This inductor value is set by the reference design, and is part of the circuit; not like other matching networks, which have multiple paths to the solution and can be mostly arbitrarily chosen. Not only does it contribute to the matching network, but it also sets the gain and Q (tuneability) of the circuit. The matching network that is attached to the output should rst be a series component, so that the desired gain and Q of the circuit are not aected. A lengthy transmission line from the collector adds sucient inductance, which serves as a good series component, to allow matching circuits to continue after the trace. 75

3.5

Low Noise Amplier Impedance Matching

As from the manual and as previously stated in Chapter 2, the LNA is already internally matched to a good degree, according to the specication sheet. Therefore, 50 traces are used to route the signal, and larger coupling capacitors are used to AC couple the signal. For optimal impedance matching, a PCB must be sacriced so that connections can be made to the input and output ports of the LNA. A network analyzer must be employed, and S-parameters analyzed.

3.6

Antenna Impedance Matching

The antenna has an an associated matching network and layout suggestion from the specication sheets to achieve 50 matching. The gures for this network are shown below. The units for the lengths are in mils.

Figure 3-8: Matching network for Gigaant antenna

76

Chapter 4 Other Circuits and Layout Approach

4.1 Power-Supply Decoupling

Power supply decoupling was done copiously throughout the board. Two types of low-pass lters were used on the power supply. They are shown in gures 4-1(a) and 4-1(b).

(a) Power supply lter for power plane

(b) Power supply lter for isolated supplies

Figure 4-1: Power supply lters on PCB

Figure 4-1(a) represents the ltering network used to lter the power supply from the battery, onto the power plane. The inductor L must be a large value, and have very low series resistance, so that a maximum of 340mA may be drawn from the battery, but not suer a voltage drop at DC due to high resistivity supply ltering. 77

The capacitors likewise, should be the largest tolerable size for the largest value that can be obtained. Once the battery voltage is ltered, the voltage is then placed on the power plane to be distributed as needed. Figure 4-1(b) is the circuit that grabs the voltage from the power plane, and does individual ltering. This is useful for the LMX chip, the receiver power supplies, and inputs to the regulators. usually the values for C1 and C2 are 10F , and R is 5 to 10 ohms. C3 is 100pF ; the reason that a smaller capacitor is needed, is because sometimes the self-resonant frequencies of larger capacitors occur at a very low frequency; when this happens, the capacitor switches from having a 1/s rollo to something that looks like an inductive load. The smaller the capacitor values, the higher the self-resonant frequency.

4.2

10MHz Squarewave Generator

two clocks of the same frequency are needed on the radio board; one is to drive the LMX3162 and the other is to drive the Xilinx FPGA. The reference oscillator that is on chip generates a sinusoidal wave. Taking advantage of the attenuation factor of an inductor, a simple circuit shown in gure 4-2

Figure 4-2: Squarewave generator from sinusoid input

This circuit takes as input a sinusoid, and places the unattenuated sinusoid in the non-inverting input of the comparator. The capacitor serves to AC couple the sinusoid, as the source has a DC oset, and the resistor of 300k serves to DC bias the input to ground. The 1mH inductor that connects the positive and negative inputs of the comparator has two functions. First, at DC, it biases both of the nodes at the 78

same voltage. At AC, it lters out AC component via the capacitor/inductor divider, leaving only the DC component. This DC component serves as a good reference for the comparator to switch around. The output of the comparator is a squarewave from 0V to 3V , which is what is desired for the clock of the Xilinx.

4.3

Oscillator Choice

The current oscillator of choice is a temperature-compensated crystal oscillator, from ECS, inc. The important specication for this oscillator is the frequency stability: +/-2.5P P M . The reason this specication is important, especially for wireless applications, is that when jitter of inaccurate clocks get coupled through the PLL, injected onto the RF signal as frequency content, the received signal becomes unnecessarily corrupted and dicult to demodulate. Therefore, low-jitter clocks and reference oscillators are of key importance, especially in FM radio transceivers.

4.4

Layout Approach

For mixed-signal circuits done on Printed Circuit Boards (PCB), signal isolation and noise reduction can be minimized by proper layout techniques, correct choice of substrate, the above mentioned supply ltering, and shielding. Through experience, these intuitions will be gained. Here is a brief overview of what has been found by experience.

4.4.1

Ground Plane

A solid ground plane is very important for mixed-signal design. The purpose of a ground plane is to eliminate inductive loops and resistive terminations if the ground plane is routed like a signal path. Furthermore, a ground plane allows low-resistive and quick connections to ground from the circuit by the use of vias. Layout is a key component in determining the shape of the ground plane. If the circuit can be divided up into analog on one side, and digital on the other, than the ground 79

plane can be shared between the two layers if it is placed in an intermediate layer on the board. However, a better option would be to place the analog and digital components on the same side, but divide the board into two-halves. One half will contain the analog circuits and the other half will contain the digital. The beauty of this method is the option to isolate the ground planes. The way this is done is by drawing two rectangles of ground plane, one directly under each half of the board, and then connecting the grounds together with a single 18mil trace that has a short length. This eectively sets both planes at the same voltage, but allows for the current to collect in each plane, and be forced to travel through the same node connection formed by the 18mil trace. It is also possible to direct the ow of current in this way; if the ground connection to the battery is placed on the digital side of the board, then the analog currents will collect in their own plane, ow through the 18mil trace, ow past the digital grounds (which are very noisy), and then ow back into the battery to terminate. This eectively avoids a major problem of mixed-signal circuit design: the digital noise going in and attacking the analog signals. More research may also be done in this area to apply these concepts to integrated circuits, as well. Ground planes are also a necessity in RF circuits, due to their application in transmission lines. Because of this, the ground plane is always directly below the top layer of the board. This conguration also allows for signal shielding between the top layer and intermediate layers, if there are any. Finally, for circuits that have very high power consumption and rapidly heat up, a strong ground connection to the ground plane for this circuit will do good to use the ground plane as a heat sink for such a circuit. On the radio board, the power amplier exhibits these heating eects due to the 1W maximum power that it can draw in such a small area.

4.4.2

Power Plane

The power plane is also useful, not so much as a noise-immunity issue of mixed-signal circuits, but moreso for the ease of design that quick connections may be made to power, throughout the circuit. For PCBs that have multiple power supplies like this 80

radio board, dividing up the power plane is a useful tool to speed up the layout process for such circuits. The only caveat is that circuits with dierent supplies must be placed above their corresponding power plane. Usually, the power plane is directly above the bottom layer of the board, to provide shielding and isolation between the intermediate layers and the bottom layer, as well as shielding from the top to the bottom layer.

4.4.3

Isolation

There are many ways to isolate circuits and traces. One common way is the use of a faraday cage. To construct such an object (usually around sensitive high-frequency components), many large vias to ground are placed in a perimeter around the circuit to be isolated. When the board comes back and the components are placed, a metal cage made of copper can be soldered onto the unmasked vias. The vias should be placed close to one another, to provide lateral shielding within the PCB dielectric as well. Finally, the ground plane should extend the entire area underneath the circuit to be shielded. On the radio board PCB, the VCO and oscilliator both come with their own faraday cages for shielding and isolation. Isolation also occurs across layers, from top to bottom, and if signals need to be shielded, then intermediate layers can also serve to isolate such signals. For sensitive lines on board, it is also useful to do copper pours around the lines to have paths to ground for any radiating elements that may disturb the lines of interest if there were no readily available ground potential for those electric elds to terminate to. When laying out traces, it is also good practice to do a hatched 90-degree layout of multi-layered signal. This basically means that whenever a trace on one layer is able to traverse in such a way that cuts 90o into the traces on other layers, this reduces the amount of signal coupling. This is especially applicable and useful for digital circuits. 81

4.4.4

Trace Sizes, Via Sizes, and Substrate Selection

The common trace sizes for PCBs are 8-16mils. This allows for relatively lowresistivity connections. As for via sizes, the wider they are, the closer they are to an ideal short. Throughout the radio board, 10mil holes with 22mil via diameters are used. This is the smallest via that can be made, and is able to function well for the types of currents and power that the radio board draws (no greater than 400mA). Substrate selection is also of key importance. It has been seen in the past that some substrates are conductive, and will spill signals all over the place, due to its poor function as an insulator. The substrate also determines the losses that can occur in microstrip line design, and also determines the characteristic impedance of the lines, as well as propogation velocity and many other important transmission line characteristics. Traditionally, for frequencies below 3GHz, F R4 substrate is used. For higher frequencies, substrates such as Rogers4000 is a good candidate.

82

Chapter 5 Experiments on Range and Power of Radio Board

5.1 Bit-Error Rate and Range Tests

In a eld test, two nodes were taken out to MITs Kresge Oval for testing. Range, biterror-rate, and power tests were done on the node. The results are as follows in gure 5-1. The percentages next to the data points represent the probability of receiving an uncorrupted packet, if a packet is received. Data points that are at 107 actually represent zero bit errors when the data was collected for that point. Upon rst pass at the data, it seems contrary to the mind that 3dBm would yield better results at farther distances; 50m is quite far for just 3dBm of output power. The reason for this anomaly is because the orientation of the radio nodes for 10dBm and 15dBm are dierent from the orientation of the radio nodes for the 3dBm test case. Looking back to Chapter 2, it can be seen from gure 2-6(a) that the antenna radiation pattern of the radio node has a very strong upwards Z-component, because the antenna is horizontally-aligned with the ground plane. If the antenna were oriented in a vertical direction, there would not be as much radiation in the Z-direction; the radiation would instead be omnidirectional, radiating the maximum power in the Z = 0, X -Y plane. Following the suggestion in section 2.2.5, a 83
1 -wave 4

antenna was quickly built

Figure 5-1: Bit Error rate test results

1 -wave antenna, the radiation pattern has great and tested. It is found that for a 4

dependency on ground plane location. It is found that it is necessary for the node to be a foot or more above the ground plane for proper radiation; otherwise, at 3dBm of output power, the receiver is unable to receive when the nodes are more than a few feet apart, ush against the ground. It is dicult to measure and model such radiation patterns and strengths, so it is by trial and error, experience, and time that antennas are properly designed.

5.2

Power Analysis on one Node to Node Link Using AMPS Radio

To elicit the impact of the AMPS node in all of its specications, features, design motivations, and power-aware hooks with regard to wireless networks, a node-to-node link is taken and analyzed with respect to the Energy/bit system-level performance metric. For a wireless node-to-node link, equation 5.1 shows how Energy/bit can be calculated for such a connection. 84

bits + 2Pidle tpll,lock + (Ptx + Prx )( B BP S Eenergy /bit = Bbits

Bsync ) BP S

(5.1)

Using the values in table 5.1, the plots in gures 5-2(a) and 5-2(b) are made. Table 5.1: Values used for variables in equation 5.1 Variable Pidle Prx Ptx tpll,lock Bbits Bsync BP S Value 80mW 300mW 250mW , 270mW , 310mW , 390mW , 530mW , and 1.1W 400S A range from 2 to 220 (1M bit) 80 1M bit/sec

What can be gathered from the data in the gures is that there comes a point where the Energy/bit metric can no longer be reduced, because the active portion of the equation dominates over the xed-cost component. The active portion of the equation lies in the number of bits transmitted. The xed-cost portion lies in the xed-cost that the radio has to pay, each time it begins to send the packet when it pays for the startup time of the PLL and the time it takes to send an 80 bit header/sync in the preamble of the transmit data. It is also important to note that the corner bits/transmit-cycle is key in designing packetlengths. For optimal operation, it is desirable to operate at the lowest Energy/bit section on the graph to squeeze the maximum lifetime and data-gathering a network can deliver. Equation 5.1 can be rewritten much like a transfer function is written, with the frequency variable s replaced by Bbits . In this way, it is possible to extract the 1/bit constant, or zero of the system. It is at this zero location that the optimal choice for bits/transmissioncycle resides. It is true that the Energy/bit decreases asymptotically to some value, but it is important that the decay beyond the zero location is asymptotic, and thereby nominal. Secondly, it would cost too much energy to transmit a million bits, or even wait long enough to gather enough information to construct and transmit a packet of that length. With that said, it becomes obvious that packet length should be 85

(a) Energy/bit plot

(b) Zoom in on Energy/bit plot zero

Figure 5-2: Energy/bit plots for table 5.1

86

dependent on application as well, but in this case, it is in the interest of intelligently optimizing the Energy/bit ratio, only. (Ptx + Prx )Bsync Bbits ( 2BP SPidle tpll,lock +(Ptx +Prx )Bsync ) + 1 (2Pidle tpll,lock + BP S Bbits
Ptx +Prx

(5.2)

From this equation, it is possible to see that if the 1/bit constant in front of the Bbits of the numerator is reduced, then the bits/transmit-cycle can become smaller for the optimization of the Energy/bit ratio. The lower this zero occurs, the more adaptable, recongurable, and power aware the radio becomes. It is apparent that changing Ptx or Prx has little impact on the zero location, since they both appear in the numerator and denominator of the 1/bit constant. AdjustingBsync and making it as small as possible is a viable option, but has its limitations and required minimum size. The best option is to tackle the Pidle and tpll,lock variables (BP S is usually xed). However, if it is desired to shift the graph in gure 5-2(a) vertically downwards, then a reduction Ptx and Prx are greatly eective.

87

88

Chapter 6 Conclusions
The most dicult domain of RF transceiver design is what cannot be measured: the wireless link through two antennas. A better understanding and modeling of such dynamics will benet any RF engineer greatly. The most surprising result was the ability for an Rx-Tx pair to communicate 49m at a mere 3dB of output power when the alignment of the boards were placed perpendicular to earth ground, pointing at -wave vertically aligned antenna was briey tested as well, and it each other. The 1 4 was found that this antenna allows omnidirectional transmssion in a radius of 10m at 3dB of output power; however, when the node is placed directly on earth ground, the transmission radius is cut to one foot. There are denitely interesting areas of research in this electromagnetic domain regarding antenna radiation patterns, and how to predict and model these issues. Regarding wireless sensor nodes, it is clear that this eld is still in the rst stages of research. Low power methods are still being discovered in the digital, RF, and analog domains; single-chip integration is coming closer to reality; transistor scaling is still moving forward for at least a few more years; extensive research in MEMs-based energy harvesting and RF switching is being done; and numerous other advancements in the areas of computer science and signal coding are being made. The entry-barrier to building a robust and usable network is that each person in the chain of engineer experts must be able to deliver their part. The type of engineer that should help usher in wireless sensor nodes is one who has deep understanding in their own eld, 89

but also has a broad and workable knowledge of all the other components that go into a wireless network node. When the details of power awareness, low power design, and interface issues are solved, the truly robust nodes and networks allows for system engineers to bring about new domains in information processing, data gathering, and parallel computing.

90

Appendix A Homodyne and Heterodyne Receivers:Trados and Advantages

Here, an understanding of the tradeos and advantages of using heterodyne receivers over homodyne receivers is explained. Some of this information may be useful in understanding reciever architectures as outlined in Chapter 2. Heterodyne systems are much easier to implement than homodyne (or directconversion) systems, because homodyne receivers have the following three problems, which by adopting a heterdyne architecture, can be avoided [9]: DC osets in analog demodulated signal Even-order distortion Flicker noise The DC osets are caused by directly downconverting the RF signal to baseband. Because this technique includes zero frequency, there could be some oset voltages that cause baseband ampliers to be saturated, while also corrupting the original baseband signal. Some causes of DC osets come from local oscillator (LO) leakage from one mixer input to the mixer input for the LNA. This is called self-mixing. Another way that DC osets occur is if the LNA output leaks into the LO input of the mixer, and is mixed down to baseband to cause DC oset voltage. There are 91

ways to overcome these diculties on homodyne receivers, but an alternative is to go to a heterodyne architecture, and avoid DC oset problem altogether, because the intermediate frequency (IF) is not at DC, where the self-mixing problems of the LO and LNA to itself are avoided. Figure A-1 illustrates DC oset problem [9].

Figure A-1: DC oset illustration [9]

Even-order distortion arises from second-order distortion in the LNA, when two interferers with a small frequency dierence are in the vicinity of the RF signal intermodulated down to baseband. If the non-ideal output of mixers, expressed in equation A.1, causes this baseband signal to be fedforward to the baseband processing circuitry, then even-order distortion occurs [9]. vM IXER = vRF (t)(a + A cos wLO t) (A.1)

The constant a in equation A.1 represents a feedthrough term of the mixer. Figure A2 shows a graphical representation of even-order distortion. Even-order distortion can be avoided in homodyne recievers by the usage of dierential-mode LNAs, because in the dierential mode, the even-order modulation products are supressed. However, for heterodyne receivers, even order distortion/mixer feed-forward characteristics are avoided altogether because of the non-DC IF frequency [9]. 92

Figure A-2: Even order distortion illustration [9]

Flicker noise is the same as 1/f noise. The magnitude of the noise is proportional to 1/f of the frequency. Thus, at high frequencies, the magnitude of 1/f noise goes below the noise oor. The source of this noise is due to drift current. Since the current in CMOS transistors are mainly drift currents, icker noise is highly present in CMOS LNAs. Thus, if CMOS LNAs and mixers are incorporated into the reciever chain, and the receiver architecture is homodyne, then the baseband is directly in the frequency range of noticable contributions of icker noise. A good solution for icker noise in homodyne architectures is to go to BJT-based LNAs and mixers. But another good solution that is common to the previous two problems is to just go to the heterodyne architecture, where the IF frequency is not at low frequencies where 1/f noise is prevalent [9]. The benet of having a heterodyne architecture over a homodyne architecture for the reciever is that it is easier to design, because the simple solutions inherent in the architecture overcome many circuit diculties. The drawbacks of heterodyne design are simply the extra components which may cause an increased power consumption, 93

dealing with images, reduced gain in the receive channel due to multiple lters trying to supress images, and costly o-chip lters and components. However, the concept of images must be discussed before the heterodyne reciever is discussed further. Images arise from the eects of mixing and lack of ltering. Figure A-3 illustrates the problem of images in heterodyne recievers.

Figure A-3: Image frequency in a heterodyne reciever architecture [9]

From gure A-3, the IF frequency is determined as the dierence in frequency between the LO frequency and RF frequency (labeled w1 in the gure). However, at the output of a multiplier, cos((wLO w1 )t) and cos((w2 wLO )t) both occur at the same place: wIF . If there is an image frequency present at wLO + wIF , then an image is generated exactly where the channel selelction should be done in the IF frequency. A good solution to this problem is to add an image-reject lter after the LNA to reject all images that are above this critical frequency of wlowest
RF f req

+ 2wIF [9].

In a heterodyne architecture, shown in the top of gure A-4, the selection of IF frequency is of upmost importance, and requires consultation of the image-reject and channel-select lters, an estimation of the environment for where interferers are likely to fall, and the a consideration of components that are available to construct the receiver. A general rule to follow, is that as the image-reject lter is relaxed, the IF frequency must increase. As the IF frequency increases, the channel-select lter if forced to be higher-Q, to reject nearby interferers. An illustration of this tradeo is illustrated in gure A-4 [9]. From the high IF frequency choice, the Q of the lter is higher, and thus is harder 94

Figure A-4: IF frequency: high IF (top) and low IF(bottom) [9]

95

to build. Because of the inability to build high-Q lters at higher frequencies, high IF frequency systems have a harder time supressing nearby interferers. However, for the low IF frequency architecture, since high-Q lters are easier to build at lower frequencies, nearby interferers are able to be supressed. The drawback for low IF frequencies is that the Q of the image reject lter needs to be very large in order to reject images. There are other architectures, such as dual IF frequency systems, which supress images and nearby interferers well. But for the purposes of design ease and practicality, single-IF systems are a popular choice for RF designers [9].

96

Appendix B Matlab Files for Impedance Matching Calculations

This chapter outlines the MATLAB scripts that are used to calculate transmission line parameters. Descriptions of what each le does are as follows. ustrip.m is the master program that runs and uses all of the *calc.m les. *calc.m are programs that support ustrip.m. They calculate the parameters of a microstrip line. impedance.m takes the values from ustrip.m and calculates the impedance looking into a certain length microstrip line with a load ZL . quickrun.m is the program that incorporates impedance.m and ustrip.m together. microstep.m is the program used to run ustep.m. Microstep calculates the eect of steps in ustrip lines. ustep.m is a special program that calculates steps in microstrip, and gives the resulting input impedance looking into the line, after the step. It also uses bits and pieces of the *calc.m programs. example.m is an example of how to use all of these programs to calculate the impedance of a long line of transmission lines and loads, etc.

97

B.1

ustrip.m

% DATA INPUT for microstrip. All parameters are in Hz, m, etc. 1 mil is the % same as 25.4001 microns. so, 1 mil is the same as 25.4001e-6 meters. w=ww25.4001e6 l=ll25.4001e6 h=hh25.4001e6 t=tt25.4001e6 SurfRu=0.055 Eo=8.85e12 Er=4.5 MUo=4pi1e7 MUr=1 SIGMA=5.8e7 f=2.45e9 c=299792458 ; % WIDTH OF METAL ; % LENGTH OF METAL ; % THICKNESS OF SUBSTRATE ; % THICKNESS OF METAL ; % r.m.s. surface roughness ; % PERMITTIVITY ; % RELATIVE PERMITTIVITY ; % PERMEABILITY ; % RELATIVE PERMEABILITY (1 for nonmag) ; % CONDUCTIVITY OF METAL ; % FREQUENCY ; % SPEED OF LIGHT
10

Rm=sqrt(2pif MUo/(2SIGMA)) ; % Metal Resistance Zo=120pi ; % Free Space Impedance TANDEL=0.03 ; % Parameter of Substrate: LOSS TANGENT

20

% TANDEL for FR4 goes from .019 to .025. Supposedly TANDEL is just TANGENT % of Skin Depth. . . Hmmm. . . but from calculation, probably wrong. . . [We, Wecheck]=Wecalc(w, h, t); [Ee, Eecheck]=Eecalc(w, h, Er); [Zc, Zccheck]=Zccalc(w, h, Eo, MUo, We, Ee); Lg=Lgcalc(f, c, Ee); Eef=Eefcalc(w, h, Er, f, Ee); K=Kcalc(Eo, MUo, f, Eef); [Skin, Skincheck]=Skincalc(t, MUo, SIGMA, f); [Ad, Am, loss]=. . . Losscalc(w, l, h, t, SurfRu, Er, MUo, Rm, Zo, TANDEL, Lg, We, Zc, Eef, Ee, Skin); [Le, Lecheck]=Lecalc(w, h, Er, Ee); [velocity, delay]=Veldelcalc(l, Eo, MUo, Ee); %% %% Frequency Cutos % %% % % Fhom. Frequency below at which higher order modes do not propogate. % Fsurf. Frequency at which below, you do not have surface waves. % Frad. Frequency at which radiation become signicant. % Fhom. Frequency below at which higher order modes do not propogate. % Variables needed for Fcutcheck: % % w = width of metal. % h = thickness of substrate. % Er = relative permittivity.

30

40

50

98

% f = frequency. % c = speed of light. [Fhom, Fhomcheck, Fsurf, Fsurfcheck, Frad, Fradcheck]=Fcutcalc(w, h, Er, f, c); ErrorVector=[Wecheck Eecheck Zccheck Skincheck Lecheck Fhomcheck Fsurfcheck Fradcheck]

B.2

Chamcalc.m

function ss=Chamcalc(w, h) %% % Chamfered bend calculation % %% % % Input the width of the line. This way, we can calculate what the % diagonal of the corner will be. % % After the diagonal is calculated, we will then see how much we need % to shave o o of the diagonal length, so that the corner is % perpendicular to the diagonal, and that it happens at 45 degrees. % % Optimal chamfering occurs when we have 1 < Er < 25 and w/h > 0.25. d=sqrt(2)w; ss=d(0.52+0.65exp(1.35w/h))/25.4e6;

10

B.3

Eecalc.m

function [Ee, Eecheck]=Eecalc(w,h,Er) %% %% Ee QUASI-TEM APPROXIMATION at f=0 % %% % % Er is relative permittivity of the substrate. In microstrip, you have two % permittivities: Air and Dielectric. For most of operating freq of % microstrips, the longitudinal components of the elds are much smaller % than transverse waves, so they can be neglected. Thus, dominant mode % behaves like TEM. This is called the QUASI-TEM APPROXIMATION. In % QUASI-TEM APPROXIMATION, you have an Ee, which is the relative Eective % permittivity. % % Variables needed for Ee: % % w = width of metal. % h = thickness of substrate. % Er= relative permittivity of substrate. aEe=1+1/49(log10((w/h)^4 + (w/(h52))^2)log10((w/h)^4+0.432))+. . .

10

20

99

1/18.7log10(1+(w/(18.1h))^3); bEe=0.564((Er0.9)/(Er+3))^0.053; Ee=(Er+1)/2 + ((Er1)/2)(1+10h/w)^(aEebEe); % Ee is better than 0.2% IF 0.01 < w/h < 100 and 1 < Er < 128. Check Eecheck. if ((w/h < 100) & (w/h > 0.01) & (1 < Er) & (Er < 128)) Eecheck=1; else Eecheck=0; end

30

B.4
% % % % % % % % % % % % % % % % % %

Eefcalc.m

function Eef =Eefcalc(w, h, Er, f, Ee)

Eef FREQ DEP EFF PERM %

QUASI-TEM is only good at DC At low frequencies, the longitudinal elds increase, and the hybrid modes become signicant. As frequency increases, the energy is concentrated more and more in the dielectric. QUASI-TEM can be extended if we use a frequency dependent permittivity, Eef. At very high frequency, elds are contained all in the dielectric. Then, Eef is the same as Er. This aects only the losses and propogation K vector stu. Variables needed for Eef: w = width of metal. h = thickness of substrate. Er = relative permittivity of substrate. f = frequency. Ee = eective permittivity of substrate.

10

20

P1Eef=0.27488+w/h(0.6315+0.525/(1+0.157(10^7)f h)^20)0.065683exp(8.7513w/h); P2Eef=0.33622(1exp(0.03442Er)); P3Eef=0.0363exp(4.6w/h)(1exp(((f h10^7)/3.87)^4.97)); P4Eef=1+2.751(1exp(Er/15.916)^8); PEef=P1Eef P2Eef ((0.1844+P3Eef P4Eef)(10^6)f h)^1.5763; Eef=Er(ErEe)/(1+PEef);

B.5

Fcutcalc.m

function [Fhom, Fhomcheck, Fsurf, Fsurfcheck, Frad, Fradcheck]=Fcutcalc(w, h, Er, f, c) %% %% Frequency Cutos % %%

100

% % % % % % % % % % % %

Fhom. Frequency below at which higher order modes do not propogate. Fsurf. Frequency at which below, you do not have surface waves. Frad. Frequency at which radiation become signicant.
10

Variables needed for Fcutcheck: w = width of metal. h = thickness of substrate. Er = relative permittivity. f = frequency. c = speed of light.

Fhom=c/(sqrt(Er)(2w+0.8h)); if (f < Fhom) Fhomcheck=1; else Fhomcheck=0; end Fsurf=catan(Er)/(sqrt(2)pihsqrt(Er1)); if (f < Fsurf) Fsurfcheck=1; else Fsurfcheck=0; end Frad=2.14(Er)^(1/4)/(h1e6); if (f < Frad) Fradcheck=1; else Fradcheck=0; end

20

30

40

B.6

Kcalc.m

function K=Kcalc(Eo, MUo, f, Eef ) % %% K FACTOR % % % % This is of units 1/m. % K, the propogation factor, determines spacial frequency of propgation. % It is the complex component of the GAMMA factor. % % Variables needed for % % Eo = permittivity.

10

101

% MUo = permeability. % f = frequency. % Eef = USE Eefcalc.m. K=2pif sqrt(EoEef MUo);

B.7

Lecalc.m

function [Le, Lecheck]=Lecalc(w, h, Er, Ee) %% %% Le - What to add onto line if open circuit stub % %% % % Due to fringing elds, there is a fringing capacitance at the end of an % open circuit transmission line. This fringing capacitance can be modeled % as an ideal transmission line with the extra length we are going to % calculate. Thus, it is useful to just pretend we have an ideal tx line, with % added length at the end. This change in length aects the Zin calculation % in impedance.m. % % Variables needed for Le: % % w = width of metal. % h = thickness of substrate. % Er = relative permittivity. % Ee = USE Eecalc.m.

10

20

z1le=0.434907(Ee^0.81+0.26)((w/h)^0.8544+0.236)/((Ee^0.810.189)((w/h)^0.8544+0.87)); z2le=1+(w/h)^0.371/(2.358Er+1); z3le=1+0.5274(atan(0.084(w/h)^(1.9413/z2le)))/Ee^0.9236; z4le=1+0.0377atan(0.067(w/h)^1.456)(65exp(0.036(1Er))); z5le=10.218exp(7.5w/h); Le=z1le z3le z5le h/z4le; if ((0.01 < w/h < 100) & (Er < 128)) Lecheck=1; else Lecheck=0; Le=2pilog(2)h; end
30

B.8

Lgcalc.m

function Lg=Lgcalc(f, c, Ee) %

102

% % % % % % % % % %

Lg Wavelength %

This is the wavelength of the line. Variables needed for Lg:

10

f = frequency. c = speed of light. Ee = USE Eecalc.m.

Lg = (c/f)/sqrt(Ee);

B.9

Losscalc.m

function [Ad, Am, loss]=. . . Losscalc(w, l, h, t, SurfRu, Er, MUo, Rm, Zo, TANDEL, Lg, We, Zc, Eef, Ee, Skin) % %% Losses Am and Ad % % % % These variables are in dB/m % A is the spacial time constant that dictates how much loss the microstrip % contributes, due to lossy microstrip lines. Two factors make up A: the % substrate, Ad, and the metal conductor losses, Am. Losses in dielectric % substrate do not aect basic electromagnetic eld distribution. % % The substrate attenuation is pretty much indep of frequency, at least % when it is not dispersing (low freq). % % Even though Ad and Am go up to an exponential, I believe that we have % removed this from the equation, and we can go ahead and get the losses % from what we see here. So, just do (Ad+Am)l to get the loss in dB at the % end of the microstrip. % % Variables needed for Ad: % % Er = relative permittivity of substrate. % MUo = permeability. % TANDEL = loss tangent of substrate. % Lg = USE Lgcalc.m. % Eef = USE Eefcalc.m. % % Variables needed for Am: % % w = width of metal. % h = thickness of substrate. % t = thickness of metal. % SurfRu = metal surface roughness. approx 0.055. ask vendor. % Rm = metal resistance. % Zo = free space impedance.

10

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103

% % % % % % % % % %

We = USE Wecalc.m. Zc = USE Zccalc.m. Ee = USE Eecalc.m Skin = USE Skincalc.m Variables needed for Loss: l= length of metal. Ad = above. Am = above.

40

Ad=27.3(Eef 1)/(Er1)Er/Eef TANDEL/Lg; if (2piw>=h) dwdb=1/pilog(2h/t); else dwdb=1/pilog(4piw/t); end

50

if (w<=h) Am=10Rm(32(w/h)^2)/(hpilog(10)Zc(32+(w/h)^2))(1+h/w(1+dwdb)); else Am=20ZcRmEe/(hlog(10)ZoZo)(w/h+6h/w((1h/w)^5+0.08))(1+h/w(1+dwdb)); end Am=Am(1+2/piatan(1.4(SurfRu /Skin)^2)); loss=(Ad+Am)l;

60

B.10

Skincalc.m

function [Skin, Skincheck]=Skincalc(t, MUo, SIGMA, f ) % %% Skin Depth % % % % Skin Depth is the distance traveled by a wave into a material until its % amplitude decreases by a factor e. Aects Loss in Metal Calculation. % Also used to check if metal thickness is too thin. % % Variables needed for Skin: % % t = thickness of metal. % f = frequency. % MUo = permeability. % SIGMA = conductivity of metal. Skin=sqrt(2/(2pif MUoSIGMA)); if (t > 3Skin) Skincheck=1;
20

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104

else Skincheck=0; end

B.11

Veldelcalc.m

function [velocity, delay]=Veldelcalc(l, Eo, MUo, Ee) % %% delay [ns] % % % % Delay time for signal to get across the transmission line. Basically you % have velocity, and then take length over velocity. % % Variables needed for Velocity and Delay: % % l = length of metal. % Eo = permittivity. % MUo = permeability. % Ee = eective permittivity of substrate. velocity=1/sqrt(MUoEoEe); delay=l/velocity1e9;

10

B.12

Wecalc.m

function [We, Wecheck]=Wecalc(w,h,t) %% %% We THIN MICROSTRIP APPROX % %% % % If the thickness of the upper conductor is about the same as the height h, % then we need a special approximation for w to compensate. Well call this % We. USE THIS ONLY FOR Zc CALCULATION. % % Variables needed for We: % % w = width of metal. % h = thickness of substrate. % t = metal thickness. ask vendor. below are some approx values. % % 1 oz. copper = 1.3mils % 0.5 oz. copper = 0.65mils % 1 mil = 25.4e-6 meters if (w > h/(2pi))

10

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105

We=w+t/pi(1+log(2h/t)); Wecheck=1; else if (2t < w < h/(2pi)) We=w+t/pi(1+log(22piw/t)); Wecheck=2; else We=w; Wecheck=3; end end

30

B.13

Zccalc.m

function [Zc, Zccheck]=Zccalc(w, h, Eo, MUo, We, Ee) %% %% Zc CHARACTERISTIC IMPEDANCE at f=0. Does not depend on frequency. % %% % % For Zc, you must know Capacitance/Length and Inductance/Length, or Co and % Lo respectively. We cant get it accurately, but we can use data/curve % tting to get appropriate approximations. % % Variables needed for Zc: % % w = width of metal. % h = thickness of substrate. % Eo = permittivity of substrate. % MUo = permeability of substrate. % We = USE Wecalc.m. % Ee = USE Eecalc.m. F1Zc=6+(2pi6)exp((30.666h/We)^0.7528); Zc=1/(2pi)sqrt(MUo/(EoEe))log(F1Zch/We + sqrt(1+(2h/We)^2)); % Accuracy of 0.03% over the range of 0 < w/h < 1000 if (0<w/h<1000) Zccheck=1; else Zccheck=0; end

10

20

B.14

impedance.m

% Taking values from ustrip.m: Ee Eef Zc ; % EFF PERMITTIVITY ; % FREQ DEP EFF PERMITTIVITY ; % CHARACTERISTIC IMPEDANCE

106

K ; % PROPOGATION CONSTANT Ad ; % LOSS FROM SUBSTRATE [dB/m] Am ; % LOSS FROM METAL [dB/m] Le ; % Eective added length due to non-innite tx line length. loss ; % Loss due to length of line. delay ; % Delay time. l ; % LENGTH OF METAL w ; % WIDTH OF METAL t ; % THICKNESS OF METAL h ; % THICKNESS OF SUBSTRATE Er ; % RELATIVE PERMITTIVITY MUo ; % PERMEABILITY SIGMA ; % CONDUCTIVITY Eo ; % PERMITTIVITY f ; % FREQUENCY c ; % SPEED OF LIGHT % extra values needed for calculations: % Zload ; % ENTER THE FIRST TIME. ELSE, UNCOM LAST LINE TO STRING IMP Zln=Zload/Zc; % NORMALIZED LOAD IMPEDANCE Zin at length=Zc(Zln+itan(Kl))/(1+Zlnitan(Kl)); % IN IMP AT SPEC. LENGTH GL=(Zln1)/(Zln+1); % REFLECTION COEFFICIENT VSWR=(1abs(GL))/(1+abs(GL)); % VOLTAGE STANDING WAVE RATIO % More complicated impedance calculation: If you know Zload already. Plot % Zload with respect to length.

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%% % Zin PLOT SECTION %%

Wavelength=linspace(0,l/Lg,10000); % USE TO PLOT IMP UP TO LENGTH % Wavelength=linspace(0,1,10000); % USE TO PLOT IMP FOR AN ENTIRE WAVELENGTH % Wavelength=linspace(0,25/8,10000); % USE TO PLOT TO ANY CHOICE LENGTH I=0; for I=1:10000, Zin(I)=Zc(Zln+itan(KLgWavelength(I)))/(1+Zlnitan(KLgWavelength(I))); end subplot(3,1,1); plot(Wavelength, real(Zin)); subplot(3,1,2); plot(Wavelength, imag(Zin)); subplot(3,1,3); plot(Wavelength, abs(Zin)); Zload Zc Zin at length VSWR

40

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60

Zload = Zin at length; % USER DEFINED. FIND IMPEDANCE. Zload/50

B.15
ustrip impedance

quickrun.m

B.16

microstep.m

wshort=wws25.4e6; wlong=wwl25.4e6; h=625.4e6; b=1.325.4e6; f =2.45e9; c=299792458; Er=4.5; Eo=8.85e12; MUo=4pi1e7; Zload; % LongOrShrt=long; [Zout, Error, Lshort, Llong, C, Ltotal]=. . . ustep(wshort, wlong, h, b, f, c, Er, Eo, MUo, Zload, LongOrShrt) Zload Zload=Zout

10

B.17

ustep.m

function [Zout, Error, Lshort, Llong, C, Ltotal]=. . . ustep(wshort, wlong, h, b, f, c, Er, Eo, MUo, Zload, LongOrShrt) %% %% Zload of T network due to microstrip step % %% Ltotal=(40.5(wlong/wshort1)32.57log(wlong/wshort)+0.2(wlong/wshort1)^2)1e9h; Weshort=Wecalc(wshort, h, b); Eeshort=Eecalc(wshort, h, Er); Zcshort=Zccalc(Weshort, h, Eo, MUo, Weshort, Eeshort); Lpshort=Zcshort/c; Welong=Wecalc(wlong, h, b);
10

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Eelong=Eecalc(wlong, h, Er); Zclong=Zccalc(Welong, h, Eo, MUo, Welong, Eelong); Lplong=Zclong/c; Lshort=LpshortLtotal/(Lpshort+Lplong); Llong=LplongLtotal/(Lpshort+Lplong); C=(sqrt(wlongwshort)((4.386log(Er)+2.33)wlong/wshort5.472log(Er)3.17)1e12)h; if (LongOrShrt == 'long') Ztemp=Zload+i2pif Llong; Zcap=1/(i2pif C); Ztemp1=ZtempZcap/(Ztemp+Zcap); Zout=Ztemp1+i2pif Lshort; else if (LongOrShrt == 'shrt') Ztemp=Zload+i2pif Lshort; Zcap=1/(i2pif C); Ztemp=ZtempZcap/(Ztemp+Zcap); Zout=Ztemp+i2pif Llong; else Zout='DOH'; end end Error=1
20

30

40

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110

Appendix C Schematics and Layout for Radio Board

This chapter contains the schematics and actual implementation data for the radio board. Figures C-1 and C-2 are the schematics for the radio board. Figures C-3, C-4, C-5, C-6, and C-7 are the actual layers of the 5 layer board. They are respectively the layouts for the top metal, gnd plane (negative mask1 ), intermediate metal, power plane (negative mask), and bottom metal, respectively. All PCB design was done in the software package P-CAD 2000. The substrate that was used is FR4. The thickness of the board from top copper to ground plane is 10mils, for impedance matching. All other board thicknesses are arbitrary. The metal layers are in the order presented, top to bottom, from gure C-3 to gure C-7. Figure C-8 is all of the metal layers stacked upon each other. Tables C.1, C.2, C.3, and C.4 are the bill of materials for the radio board.

1 Negative mask means that wherever there is an object drawn on this layer, there is no metal placed where there is an object

111

Table C.1: Bill of Materials for ICs Quantity 3 1 1 1 1 1 1 1 1 6 1 1 1 3 1 3 1 1 1 1 1 1 Part No. 2N3904 BFP420 MAX2242 MAX1742 DFCB22G44LBJAA SAFUW110MCA0T00 FLAVUS SMV1763-079 IEEE1386 CRIMPS 4POS HEADER 4POS HOUSING LM6152 LMV7219 LMX3162 LP2980 OSCSG39 UCVE8X808A UPG152TA POT VARACTOR XC18V02 XCV300E Website www.digikey.com www.inneon.com www.maxim-ic.com www.maxim-ic.com www.murata.com www.murata.com www.gigaant.com www.alphaind.com www.digikey.com www.digikey.com www.digikey.com www.digikey.com www.digikey.com www.national.com www.national.com www.national.com www.digikey.com http://www.alps.co.jp/ www.digikey.com www.digikey.com www.xilinx.com www.xilinx.com Digikey Part No. FMMT3904CT-ND none none none none none none none WM17201-ND WM1775-ND WM1733-ND WM1722-ND LM6152BCN-ND none none none X493CT-ND none UPG152TA-ND SG2020CT-ND none none

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Table C.2: Bill of Materials for Inductors Quantity 2 1 2 2 1 1 1 1 1 1 2 1 Part No. 2.2nH 0402 2 5nH 0402 3.9nH 0402 4.7nH 0402 KIT 0402 68nH 1206 120nH 1206 150nH 1206 220uH 1206 5.3uH 1.045mH BIG INDUCTOR Website www.digikey.com www.digikey.com www.digikey.com www.digikey.com www.digikey.com www.digikey.com www.digikey.com www.digikey.com www.digikey.com www.digikey.com www.digikey.com www.digikey.com Digikey Part No. PCD1268CT-ND PCD1269CT-ND PCD1271CT-ND PCD1272CT-ND PCD3-KIT-ND M1163CT-ND M1166CT-ND M1167CT-ND M1169CT-ND TKS5514CT-ND DN4524CT-ND TKS5527CT-ND

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Table C.3: Bill of Materials for Capacitors Quantity 1 4 1 1 2 2 7 1 16 3 1 1 2 1 1 1 2 1 2 12 1 3 1 1 19 2 2 Part No. 2.97pF 0402 0.1uF 0402 6pF 0402 10pF 0402 33pF 0402 100pF 0402 0.01uF 0603 0.015uF 0603 0.1uF 0603 1nF 0603 1uF 0603 6.8nF 0603 10pF 0603 15pF 0603 18pF 0603 22pF 0603 27pF 0603 39pF 0603 47pF 0603 100pF 0603 389pF 0603 470pF 0603 560pF 0603 2700pF 0603 10uF 1206 47uF BIG CAP Website www.digikey.com www.digikey.com www.digikey.com www.digikey.com www.digikey.com www.digikey.com www.digikey.com www.digikey.com www.digikey.com www.digikey.com www.digikey.com www.digikey.com www.digikey.com www.digikey.com www.digikey.com www.digikey.com www.digikey.com www.digikey.com www.digikey.com www.digikey.com www.digikey.com www.digikey.com www.digikey.com www.digikey.com www.digikey.com www.digikey.com www.digikey.com Digikey Part No. PCC2223CT-ND PCC1731CT-ND PCC060CQCT-ND PCC100CQCT-ND PCC330CQCT-ND PCC101CQCT-ND PCC1750CT-ND PCC153BVCT-ND PCC1762CT-ND PCC1772CT-ND PCC1787CT-ND PCC1800CT-ND PCC100ACVCT-ND PCC150ACVCT-ND PCC180ACVCT-ND PCC220ACVCT-ND PCC270ACVCT-ND PCC390ACVCT-ND PCC470ACVCT-ND PCC101ACVCT-ND PCC391ACVCT-ND PCC2147CT-ND PCC2148CT-ND PCC1777CT-ND PCC1894CT-ND PCE3160CT-ND P11308CT-ND

114

Table C.4: Bill of Materials for Resistors Quantity 3 8 1 1 7 2 1 6 1 2 1 2 2 1 1 1 3 1 1 1 1 1 1 1 1 1 8 Part No. 50 0402 100 0402 6.8k 0402 KIT 0603 5 0603 100 0603 300 0603 1k 0603 1.2k 0603 3.3k 0603 3.47k 0603 3.9k 0603 4.7k 0603 5.86k 0603 8k 0603 8.2k 0603 10k 0603 15k 0603 40k 0603 75k 0603 100k 0603 140k 0603 165k 0603 180k 0603 300k 0603 1M 0603 LEDs 0603 Website Digikey Part No. www.digikey.com P49.9LCT-ND www.digikey.com P100LCT-ND www.digikey.com P6.8KLCT-ND www.digikey.com CR5A-KIT-ND www.digikey.com P5.1GCT-ND www.digikey.com P100HCT-ND www.digikey.com P301HCT-ND www.digikey.com P1000HCT-ND www.digikey.com P1.21KHCT-ND www.digikey.com P3.32KHCT-ND www.digikey.com P3.48KHCT-ND www.digikey.com P3.92KHCT-ND www.digikey.com P4.64KHCT-ND www.digikey.com P5.9KHCT-ND www.digikey.com P8.06KHCT-ND www.digikey.com P8.25KHCT-ND www.digikey.com P10.0KHCT-ND www.digikey.com P15.0KHCT-ND www.digikey.com P40.2KHCT-ND www.digikey.com P75.0KHCT-ND www.digikey.com P100KHCT-ND www.digikey.com P140KHCT-ND www.digikey.com P165KHCT-ND www.digikey.com P182KHCT-ND www.digikey.com P301KHCT-ND www.digikey.com P1.00MHCT-ND www.digikey.com none

115

Figure C-1: Schematic of analog circuits for the radio board 116

Figure C-2: Schematic of digital circuits for the radio board 117

Figure C-3: PCB layout of top metal

118

Figure C-4: PCB layout of gnd plane (negative mask)

119

Figure C-5: PCB layout of intermediate metal layer

120

Figure C-6: PCB layout of power plane (negative mask)

121

Figure C-7: PCB layout of bottom metal

122

Figure C-8: PCB layout of all metal layers

123

124

Bibliography
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[15] K. C. Gupta. Microstrip Lines and Slotlines, 2nd edition. Artech House. March 1996. [16] gigaAnt. Bluetooth Flavus Snap-In Antenna. January 2001. [17] gigaAnt. Document No. AA000214 Application Note. March 2001. [18] Maxim Integrated Circuits. MAX2242 2.4GHz to 2.5GHz Linear Power Amplier. January 2001. [19] Maxim Integrated Circuits. MAX2242 Power Amplier: Crucial Application Issues. http://dbserv.maxim-ic.com/appnotes.cfm?appnote number=615 June 2001. [20] Siemens. SIEGET 25 BFP420 NPN Silicon RF Transistor. 1996. [21] Kenneth O. SNR vs. BER with diversity variable in BPSK. MIT 6.976 class, spring 2002. [22] Murata. DFC22R44P084LHA Image Reject Filter http://www.murata.com [23] Murata. SAFU110.6MSA40T Band-Select Filter http://www.murata.com [24] Sawtek. Fundamentals of SAW http://www.sawtek.com/techsupport/fundsaw.htm Transversal Filters.

[25] Alpha Industries. Hyperabrupt Junction Tuning Varactor. October 1999. [26] National Semiconductor Corporation. LM6152 Dual and Quad 75MHz GBW Rail-to-Rail I/O Operational Ampliers. August 2000.

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