ANNA UNIVERSITY,CHENNAI PRACTICAL EXAMINATIONS OCTOBER 2012 CENTRE CODE: 1131 COLLEGE NAME: VELTECH MULTITECH Dr.RANGARAJAN Dr.

SAKUNTHALA ENGINEERING COLLEGE SUBJECT CODE: EC2207 DATE: 29.10.12 TO 31.10.12 SUBJECT NAME: DIGITAL ELECTRONICS LAB QUESTIONS 1. A)Design and implement a circuit that performs addition of two significant bits and a previous carry B) Perform Simulation of a mod 12 counter using Verilog HDL. 2. A) Design and implement a circuit that performs addition of two binary inputs. B) Perform Simulation of a SIPO shift register using Verilog HDL. 3. A) Design and implement a BCD to Excess-3 code converter using logic gates. B) Perform Simulation of a half adder circuit using Verilog HDL. 4. A) Design and implement a Excess-3 to BCD code converter using logic gates. B) Perform Simulation of a PISO shift register using Verilog HDL. 5. A) Design and implement a Binary to Gray code converter using logic gates. B) Perform Simulation of a mod 10 counter using Verilog HDL. 6. A) Design and implement a Gray to Binary code converter using logic gates. B) Perform Simulation of a demultiplexer circuit using Verilog HDL. 7. A) Design and implement a circuit that performs BCD addition using specific IC. B) Perform Simulation of a half adder circuit using Verilog HDL. 8. A) Design and implement a circuit that performs addition and subtraction of 4 bits using specific IC. B) Perform Simulation of a multiplexer circuit using Verilog HDL. 9. A) Design and implement a circuit that compares the relative magnitude of 2 bits using logic gates. B) Perform Simulation of a half subtractor circuit using Verilog HDL. 10.A) Design and implement a circuit that compares the relative magnitude of 8 bits using specific ICs. SEM/DEPT: III/ECE

B) Perform Simulation of a full subtractor circuit using Verilog HDL. 11.A) Design and implement a circuit that generates an extra bit for errorless data transmission using specific IC. B) Perform Simulation of a mod 10 counter using Verilog HDL. 12.A) Design and implement a circuit that checks for error during data transmission using specific IC. B) Perform Simulation of a mod 12 counter using Verilog HDL. 13.A) Design and implement a circuit that performs as a data selector using logic gates. B) Perform Simulation of a D Flip Flop using Verilog HDL. 14.A) Design and implement a circuit that receives information on a single line and transmits the same on 2n output lines using logic gates. B) Perform Simulation of a SISO shift register using Verilog HDL. 15.A) Design and implement a circuit that has n input lines and 2 n output lines using logic gates. B) Perform Simulation of a PIPO shift register using Verilog HDL. 16.A) Design and implement a circuit that has 2 n input lines and n output lines using logic gates. B) Perform Simulation of a full adder circuit using Verilog HDL.

17.A) Construct and verify a 4 bit ripple counter using specific IC. B) Perform Simulation of a half adder circuit using Verilog HDL. 18.A) Construct and verify a mod 10 ripple counter using specific IC. B) Perform Simulation of a half adder circuit using Verilog HDL. 19.A) Construct and verify a mod 12 ripple counter using specific IC. B) Perform Simulation of a D Flip Flop using Verilog HDL. 20. Design and implement a 3 bit synchronous up/down counter. 21. A) Implement a SISO shift register using Flip Flops. B) Perform Simulation of a multiplexer circuit using Verilog HDL. 22. A) Implement a SIPO shift register using Flip Flops. B) Perform Simulation of a demultiplexer circuit using Verilog HDL. 23. A) Implement a PISO shift register using Flip Flops.

B) Perform Simulation of a full adder circuit using Verilog HDL. 24. A) Implement a PIPO shift register using Flip Flops. B) Perform Simulation of a full subtractor circuit using Verilog HDL.

INTERNAL EXAMINERS EXTERNAL EXAMINERS 1. 2.

1. A)Design and implement a circuit that performs addition of two significant bits and a previous carry B) Perform Simulation of a mod 12 counter using Verilog HDL.

AIM, PROCEDU RE, K MAP (20)

CIRCUIT DIAGRAM & PROGRAM (25+10=35)

OUTPUT VERIFICATION & SIMULATION (15+10=25)

RESUL T (10)

VIV A(1 0)

TOT AL(1 00)

INTERNAL EXAMINER EXAMINER

EXTERNAL

2. A) Design and implement a circuit that performs addition of two binary inputs. B) Perform Simulation of a SIPO shift register using Verilog HDL. AIM, PROCEDU RE, K MAP (20) CIRCUIT DIAGRAM & PROGRAM (25+10=35) OUTPUT VERIFICATION & SIMULATION (15+10=25) RESUL T (10) VIV A(1 0) TOT AL(1 00)

INTERNAL EXAMINER EXAMINER

EXTERNAL

3. A) Design and implement a BCD to Excess-3 code converter using logic gates. B) Perform Simulation of a half adder circuit using Verilog HDL. AIM, PROCEDU RE, K MAP (20) CIRCUIT DIAGRAM & PROGRAM (25+10=35) OUTPUT VERIFICATION & SIMULATION (15+10=25) RESUL T (10) VIV A(1 0) TOT AL(1 00)

INTERNAL EXAMINER EXAMINER

EXTERNAL

4. A) Design and implement a Excess-3 to BCD code converter using logic gates. B) Perform Simulation of a PISO shift register using Verilog HDL. AIM, PROCEDU RE, K MAP (20) CIRCUIT DIAGRAM & PROGRAM (25+10=35) OUTPUT VERIFICATION & SIMULATION (15+10=25) RESUL T (10) VIV A(1 0) TOT AL(1 00)

INTERNAL EXAMINER EXAMINER

EXTERNAL

5. A) Design and implement a Binary to Gray code converter using logic gates. B) Perform Simulation of a mod 10 counter using Verilog HDL. AIM, PROCEDU RE, K MAP (20) CIRCUIT DIAGRAM & PROGRAM (25+10=35) OUTPUT VERIFICATION & SIMULATION (15+10=25) RESUL T (10) VIV A(1 0) TOT AL(1 00)

INTERNAL EXAMINER EXAMINER

EXTERNAL

6. A) Design and implement a Gray to Binary code converter using logic gates. B) Perform Simulation of a demultiplexer circuit using Verilog HDL. AIM, PROCEDU RE, K MAP (20) CIRCUIT DIAGRAM & PROGRAM (25+10=35) OUTPUT VERIFICATION & SIMULATION (15+10=25) RESUL T (10) VIV A(1 0) TOT AL(1 00)

INTERNAL EXAMINER EXAMINER

EXTERNAL

7. A) Design and implement a circuit that performs BCD addition using specific IC. B) Perform Simulation of a half adder circuit using Verilog HDL. AIM, PROCEDU RE, K MAP (20) CIRCUIT DIAGRAM & PROGRAM (25+10=35) OUTPUT VERIFICATION & SIMULATION (15+10=25) RESUL T (10) VIV A(1 0) TOT AL(1 00)

INTERNAL EXAMINER EXAMINER

EXTERNAL

8. A) Design and implement a circuit that performs addition and subtraction of 4 bits using specific IC. B) Perform Simulation of a multiplexer circuit using Verilog HDL. AIM, PROCEDU RE, K MAP (20) CIRCUIT DIAGRAM & PROGRAM (25+10=35) OUTPUT VERIFICATION & SIMULATION (15+10=25) RESUL T (10) VIV A(1 0) TOT AL(1 00)

INTERNAL EXAMINER EXAMINER

EXTERNAL

9. A) Design and implement a circuit that compares the relative magnitude of 2 bits using logic gates. B) Perform Simulation of a half subtractor circuit using Verilog HDL.

AIM, PROCEDU RE, K MAP (20)

CIRCUIT DIAGRAM & PROGRAM (25+10=35)

OUTPUT VERIFICATION & SIMULATION (15+10=25)

RESUL T (10)

VIV A(1 0)

TOT AL(1 00)

INTERNAL EXAMINER EXAMINER

EXTERNAL

10.A) Design and implement a circuit that compares the relative magnitude of 8 bits using specific ICs. B) Perform Simulation of a full subtractor circuit using Verilog HDL. AIM, PROCEDU RE, K MAP (20) CIRCUIT DIAGRAM & PROGRAM (25+10=35) OUTPUT VERIFICATION & SIMULATION (15+10=25) RESUL T (10) VIV A(1 0) TOT AL(1 00)

INTERNAL EXAMINER EXAMINER

EXTERNAL

11.A) Design and implement a circuit that generates an extra bit for errorless data transmission using specific IC. B) Perform Simulation of a mod 10 counter using Verilog HDL. AIM, PROCEDU RE, K MAP (20) CIRCUIT DIAGRAM & PROGRAM (25+10=35) OUTPUT VERIFICATION & SIMULATION (15+10=25) RESUL T (10) VIV A(1 0) TOT AL(1 00)

INTERNAL EXAMINER EXAMINER

EXTERNAL

12.A) Design and implement a circuit that checks for error during data transmission using specific IC. B) Perform Simulation of a mod 12 counter using Verilog HDL. AIM, PROCEDU RE, K MAP (20) CIRCUIT DIAGRAM & PROGRAM (25+10=35) OUTPUT VERIFICATION & SIMULATION (15+10=25) RESUL T (10) VIV A(1 0) TOT AL(1 00)

INTERNAL EXAMINER EXAMINER

EXTERNAL

13.A) Design and implement a circuit that performs as a data selector using logic gates. B) Perform Simulation of a D Flip Flop using Verilog HDL. AIM, PROCEDU RE, K MAP (20) CIRCUIT DIAGRAM & PROGRAM (25+10=35) OUTPUT VERIFICATION & SIMULATION (15+10=25) RESUL T (10) VIV A(1 0) TOT AL(1 00)

INTERNAL EXAMINER EXAMINER

EXTERNAL

14.A) Design and implement a circuit that receives information on a single line and transmits the same on 2n output lines using logic gates. B) Perform Simulation of a SISO shift register using Verilog HDL. AIM, CIRCUIT OUTPUT

PROCEDU RE, K MAP (20)

DIAGRAM & PROGRAM (25+10=35)

VERIFICATION & SIMULATION (15+10=25)

RESUL T (10)

VIV A(1 0)

TOT AL(1 00)

INTERNAL EXAMINER EXAMINER

EXTERNAL

15.A) Design and implement a circuit that has n input lines and 2 n output lines using logic gates. B) Perform Simulation of a PIPO shift register using Verilog HDL. AIM, PROCEDU RE, K MAP (20) CIRCUIT DIAGRAM & PROGRAM (25+10=35) OUTPUT VERIFICATION & SIMULATION (15+10=25) RESUL T (10) VIV A(1 0) TOT AL(1 00)

INTERNAL EXAMINER EXAMINER

EXTERNAL

16.A) Design and implement a circuit that has 2 n input lines and n output lines using logic gates. B) Perform Simulation of a full adder circuit using Verilog HDL. AIM, PROCEDU RE, K MAP (20) CIRCUIT DIAGRAM & PROGRAM (25+10=35) OUTPUT VERIFICATION & SIMULATION (15+10=25) RESUL T (10) VIV A(1 0) TOT AL(1 00)

INTERNAL EXAMINER EXAMINER

EXTERNAL

17.A) Construct and verify a 4 bit ripple counter using specific IC. B) Perform Simulation of a half adder circuit using Verilog HDL. AIM, PROCEDU RE, K MAP (20) CIRCUIT DIAGRAM & PROGRAM (25+10=35) OUTPUT VERIFICATION & SIMULATION (15+10=25) RESUL T (10) VIV A(1 0) TOT AL(1 00)

INTERNAL EXAMINER EXAMINER

EXTERNAL

18.A) Construct and verify a mod 10 ripple counter using specific IC. B) Perform Simulation of a half adder circuit using Verilog HDL. AIM, PROCEDU RE, K MAP (20) CIRCUIT DIAGRAM & PROGRAM (25+10=35) OUTPUT VERIFICATION & SIMULATION (15+10=25) RESUL T (10) VIV A(1 0) TOT AL(1 00)

INTERNAL EXAMINER EXAMINER

EXTERNAL

19.A) Construct and verify a mod 12 ripple counter using specific IC. B) Perform Simulation of a D Flip Flop using Verilog HDL. AIM, PROCEDU RE, K MAP (20) CIRCUIT DIAGRAM & PROGRAM (25+10=35) OUTPUT VERIFICATION & SIMULATION (15+10=25) RESUL T (10) VIV A(1 0) TOT AL(1 00)

INTERNAL EXAMINER EXAMINER

EXTERNAL

20.Design and implement a 3 bit synchronous up/down counter. AIM, PROCEDU RE, K MAP (20) CIRCUIT DIAGRAM & PROGRAM (25+10=35) OUTPUT VERIFICATION & SIMULATION (15+10=25) RESUL T (10) VIV A(1 0) TOT AL(1 00)

INTERNAL EXAMINER EXAMINER

EXTERNAL

21. A) Implement a SISO shift register using Flip Flops. B) Perform Simulation of a multiplexer circuit using Verilog HDL. AIM, PROCEDU RE, K MAP (20) CIRCUIT DIAGRAM & PROGRAM (25+10=35) OUTPUT VERIFICATION & SIMULATION (15+10=25) RESUL T (10) VIV A(1 0) TOT AL(1 00)

INTERNAL EXAMINER EXAMINER 22. A) Implement a SIPO shift register using Flip Flops.

EXTERNAL

B) Perform Simulation of a demultiplexer circuit using Verilog HDL. AIM, PROCEDU RE, K MAP (20) CIRCUIT DIAGRAM & PROGRAM (25+10=35) OUTPUT VERIFICATION & SIMULATION (15+10=25) RESUL T (10) VIV A(1 0) TOT AL(1 00)

INTERNAL EXAMINER EXAMINER

EXTERNAL

23. A) Implement a PISO shift register using Flip Flops. B) Perform Simulation of a full adder circuit using Verilog HDL. AIM, PROCEDU RE, K MAP (20) CIRCUIT DIAGRAM & PROGRAM (25+10=35) OUTPUT VERIFICATION & SIMULATION (15+10=25) RESUL T (10) VIV A(1 0) TOT AL(1 00)

INTERNAL EXAMINER EXAMINER 24. A) Implement a PIPO shift register using Flip Flops.

EXTERNAL

B) Perform Simulation of a full subtractor circuit using Verilog HDL. AIM, PROCEDU RE, K MAP (20) CIRCUIT DIAGRAM & PROGRAM (25+10=35) OUTPUT VERIFICATION & SIMULATION (15+10=25) RESUL T (10) VIV A(1 0) TOT AL(1 00)

INTERNAL EXAMINER EXAMINER

EXTERNAL