Unversity of Microchip

11002 GS2
Getting Started with PIC MCU Mid-Range

Architecture, Instruction Set and Assembly Language Programming
2007 Microchip Technology Incorporated. All Rights Reserved.
11002 GS2
Slide
Class Objective
When you finish this class you will:
Understand the basics of the inner workings of a PIC16 Understand most instructions Understand memory organization Understand how to write simple programs
2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2 Slide 2
Agenda
O O O O O
Architecture Basics Instruction Set Overview Memory Organization and Addressing Modes Special Features Hands-on Exercises
11002 GS2
Slide
Architecture
O
The high performance of the PIC microcontroller can be attributed to the following architectural features:
Harvard Architecture Instruction Pipelining Large Register File Single Cycle Instructions Single Word Instructions Long Word Instructions Reduced Instruction Set Orthogonal Instruction Set
11002 GS2
Slide
Harvard Architecture
O
Von Neumann Architecture:

Fetches instructions and data from a single memory space Limits operating bandwidth
Harvard Architecture:
Uses two separate memory spaces for program instructions and data Improved operating bandwidth Allows for different bus widths
Slide 5
11002 GS2
Instruction Pipelining
O
Instruction fetch is overlapped with execution of previously fetched instruction
Instruction Cycles
T2 T3 T4
Example Program
1 MAIN movlw 2 movwf 3 call 4 addwf 0x05 REG1 SUB1 REG2
T0
T1
T5
T6
T7
Fetch Execute Fetch Execute
Time to execute normal instruction Time to execute call instruction includes pipeline flush
Fetch Execute Fetch Flush
Fetch
51 SUB1 movf PORTB,w 52 return 53 SUB2 movf PORTC,w 54 return

2007 Microchip Technology Incorporated. All Rights Reserved. 11002 GS2
Fetch Execute Fetch Execute Fetch Flush
Slide
Pre-Fetched Instruction Executing Instruction
movlw 0x05
Instruction Cycles
Example Program
T0 Fetch

movwf REG1
movlw 0x05
Instruction Cycles
Example Program
T0
T1
Fetch Execute Fetch

call SUB1
movwf REG1
Instruction Cycles
Example Program
T0
T1
T2
Time to execute normal instruction
Fetch Execute Fetch Execute Fetch

addwf REG2
call SUB1
Instruction Cycles
Example Program
T0
T1
T2
T3
Fetch Execute Fetch Execute Fetch Execute Fetch

movf PORTB,w
call SUB1
Instruction Cycles
Example Program
T0
T1
T2
T3
T4
Fetch Execute Fetch Execute Fetch Execute Fetch Flush

Time to execute call instruction includes pipeline flush

Fetch
Slide
11
return
movf PORTB,w
Instruction Cycles
Example Program
T0
T1
T2
T3
T4
T5

Fetch Execute Fetch
Slide
12
movf PORTC,w
return
Instruction Cycles
Example Program
T0
T1
T2
T3
T4
T5
T6

Fetch Execute Fetch Execute Fetch
Slide
13
addwf REG2
return
Instruction Cycles
Example Program
T0
T1
T2
T3
T4
T5
T6
T7
Fetch Execute Fetch Execute Fetch Execute Fetch Flush Fetch

Fetch Execute Fetch Execute Fetch Flush
Slide
14
Long Word Instruction

8-bit Program Memory
8-bit Instruction on typical 8-bit MCU

Example: Freescale Load Accumulator A: 2 Program Memory Locations 2 Instruction Cycles to Execute
ldaa #k
1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 k k k k k k k k k k k k k k k k
Limits Bandwidth Increases Memory Size Requirements
14-bit Program Memory
14-bit Instruction on PIC16 8-bit MCU

Example: Move Literal to Working Register 1 Program Memory Location 1 Instruction Cycle to Execute
movlw k
1 1 1 1 0 0 0 0 0 0 0 0 k k k k k k k k k k k k k k k k
O O
Separate busses allow different widths 2k x 14 is roughly equivalent to 4k x 8

11002 GS2 Slide 15
Register File Concept

Data Memory (Register File) w f
07h 08h 09h
ALU
Data Bus Bus Data
0Ah 0Bh 0Ch 0Dh 0Eh 0Fh
Register File Concept: All of data memory is part of the register file, so any location in data memory may be operated on directly All peripherals are mapped into data memory as a series of registers Orthogonal Instruction Set: ALL instructions can operate on ANY data memory location The Long Word Instruction format allows a directly addressable register file
Slide 16
W W
10h
Decoded Instruction from Program Memory:
Opcode d Opcode d
Address Address
Address of Second Source Operand
Arithmetic/Logic Function to be Performed
Result Destination
11002 GS2
Instruction Set Overview
11002 GS2
Slide
17
11002 GS2
Slide
18
11002 GS2
Slide
19
PIC16 Instruction Set

addwf addwf andwf andwf clrf clrf clrw clrw comf comf decf decf decfsz decfsz incf incf incfsz incfsz iorwf iorwf movf movf movwf movwf nop nop rlf rlf rrf rrf subwf subwf swapf swapf xorwf xorwf Byte Byte Oriented Oriented Operations Operations f,d Add W W and and ff f,d Add f,d f,d ff -f,d f,d f,d f,d f,d f,d f,d f,d f,d f,d f,d f,d f,d f,d ff -f,d f,d f,d f,d f,d f,d f,d f,d f,d f,d AND AND W W with with ff Clear Clear ff Clear Clear W W Complement Complement ff Decrement Decrement ff Decrement Decrement f, f, Skip Skip if if 0 0 Increment Increment ff Increment Increment f, f, Skip Skip if if 0 0 Inclusive Inclusive OR OR W W with with ff Move Move ff Move Move W W to to ff No No Operation Operation Rotate Rotate Left Left ff through through Carry Carry Rotate Rotate Right Right ff through through Carry Carry Subtract Subtract W W from from ff Swap Swap nibbles nibbles in in ff Exclusive Exclusive OR OR W W with with ff bcf bcf bsf bsf btfsc btfsc btfss btfss addlw addlw andlw andlw call call clrwdt clrwdt goto goto iorlw iorlw movlw movlw retfie retfie retlw retlw return return sleep sleep sublw sublw xorlw xorlw
11002 GS2
Bit Bit Oriented Oriented Operations Operations f,b f,b Bit Bit Clear Clear ff f,b f,b f,b f,b Bit Bit Set Set ff Bit Bit Test Test f, f, Skip Skip if if Clear Clear
f,b f,b Bit Bit Test Test f, f, Skip Skip if if Set Set Literal Literal and and Control Control Operations Operations k k k k k k -k k k k k k -k k --k k k k Add Add literal literal and and W W AND AND literal literal with with W W Call Call subroutine subroutine Clear Clear Watchdog Watchdog Timer Timer Go Go to to address address Inclusive Inclusive OR OR literal literal with with W W Move Move literal literal to to W W Return Return from from interrupt interrupt Return Return with with literal literal in in W W Return Return from from Subroutine Subroutine Go Go into into standby standby mode mode Subtract Subtract W W from from literal literal Exclusive Exclusive OR OR literal literal with with W W
Slide 20
PIC16 Visual Interpreter

ADDLW
Hex Dec Bin
0x0A ,
Literal Data from Instruction Word Data Bus Register File
Execute
Reset
Address
w d
ALU
FF FF FF 18 FF FF FF FF FF FF
11002 GS2
FF
W
Register
00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh
STATUS 2 1 0
1 0 0
Z DC C
Slide
21
Data Memory Organization

PIC16F876/877 Register File Map
368 Bytes of General Purpose RAM Plus Special Function Registers
000h 080h 100h 180h
SFR
SFR
10Fh 110h
SFR
18Fh 190h
SFR
01Fh 020h
09Fh 0A0h
128 Bytes
GPR 96 Bytes
GPR 80 Bytes
GPR 96 Bytes
GPR 96 Bytes
0EFh 07Fh 0FFh
16Fh
1EFh
Accesses Accesses 70h 70h 7Fh 7Fh Bank 1
17Fh
1FFh

Slide 22
Bank 0
11002 GS2
Data Memory Organization

Bank 0 000 001 002 003 004 005 006 007 008 009 00A 00B 00C 00D INDF INDF TMR0 TMR0 PCL PCL STATUS STATUS FSR FSR PORTA PORTA PORTB PORTB PORTC PORTC PORTD PORTD PORTE PORTE PCLATH PCLATH INTCON INTCON PIR1 PIR1 PIR2 PIR2 080 081 082 083 084 085 086 087 088 089 08A 08B 08C 08D Bank 1 INDF INDF OPTION_REG OPTION_REG PCL PCL STATUS STATUS FSR FSR TRISA TRISA TRISB TRISB TRISC TRISC TRISD TRISD TRISE TRISE PCLATH PCLATH INTCON INTCON PIE1 PIE1 PIE2 PIE2 100 101 102 103 104 105 106 107 108 109 10A 10B 10C 10D PCLATH PCLATH INTCON INTCON EEDATA EEDATA EEADR EEADR PORTB PORTB Bank 2 INDF INDF TMR0 TMR0 PCL PCL STATUS STATUS FSR FSR 180 181 182 183 184 185 186 187 188 189 18A 18B 18C 18D PCLATH PCLATH INTCON INTCON EECON1 EECON1 EECON2 EECON2 TRISB TRISB Bank 3 INDF INDF OPTION_REG OPTION_REG PCL PCL STATUS STATUS FSR FSR
Device Specific Registers

STATUS Register
IRP IRP
bit 7
RP1 RP1
RP0 RP0
TO TO
PD PD
Z Z
DC DC
C C
bit 0
IRP: Register Bank Select (used for Indirect addressing)

0 = Bank 0, 1 1 = Bank 2, 3
RP1:RP0: Register Bank Select Bits (used for direct addressing)

00 = Bank 0, 01 = Bank 1, 10 = Bank 2, 11 = Bank 3
TO: Time-out bit

0 = A WDT time-out occurred
PD: Power-down bit

0 = SLEEP instruction executed
Z: Zero bit
1 = Result of arithmetic operation is zero
DC: Digit cary / borrow bit

1 = Carry out of 4th low order bit occurred / No borrow occurred
C: Carry / borrow bit

1 = Carry out of MSb occurred / No borrow occurred
11002 GS2
Slide
24
PIC16 Addressing Modes

O
Data Memory Access:

Direct Indirect addwf <data_address>, <d> addwf INDF, <d>
Immediate (Literal) movlw <constant>

O
Program Memory Access:

Absolute Relative goto <program_address> addwf PCL,f
11002 GS2 Slide 25
Register Direct Addressing

2-bits from STATUS Register 7-bits Encoded in Instruction 9-bit Effective Address (Use this when coding)
0 0
RP1 RP0
0 0 0 0 0 0 0
f Operand
0x183
Bank 3 FF FF FF FF FF FF 1C 1C FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
Register File Address Bus
Bank 0 00h 01h 02h 03h 04h 05h 7Ah 7Bh 7Ch 7Dh 7Eh 7Fh FF FF FF FF FF FF
Bank 1
Bank 2 FF FF FF FF FF FF 18 18 FF FF FF FF
Address
FF FF FF FF FF FF FF FF FF FF FF FF
11002 GS2
Slide
26
Register Direct Addressing

Example: Initialize bits 0-3 of PORTB as outputs W Register: Address INDF: 00h TMR0: 01h PCL : 02h STATUS: 03h FSR: 04h PORTA: 05h PORTB: 06h PORTC: 07h 20h 21h 22h 23h Register File Bank 1 Bank 0 Address 80h : INDF 81h : OPTION 82h : PCL 83h : STATUS 84h : FSR 85h : TRISA 86h : TRISB 87h : TRISC A0h A1h A2h A3h
F0
9-Bit Effective Address:
0 0 0 0
RP1 RP0
0 0 0 0 0 0 0 0 0 0 0 0 0 0
7-bits from Instruction
bsf movlw movwf bcf clrf
STATUS,RP0 b11110000 TRISB STATUS,RP0 PORTB
FF FF FF FF FF FF 38 38 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
Bin Dec
FF FF FF FF FF FF 38 38 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
Hex
11002 GS2
Slide
27
Register Indirect Addressing

1-bit from STATUS Register 8-bits from FSR Register 9-bit Effective Address (Use this when coding)
0
IRP
0 0 0 0 0 0 0 0
FSR
0x1FC
Bank 0,1 000h 001h 002h 003h 004h 005h 0FAh 0FBh 0FCh 0FDh 0FEh 0FFh 100h 101h 102h 103h 104h 105h 1FAh 1FBh 1FCh 1FDh 1FEh 1FFh
Bank 2,3
FF FF FF FF FF FF 1C 1C FF FF FF FF
FF FF
Register File Address Bus
11002 GS2
Slide
28
Register Indirect Addressing

Example: Clear all RAM locations from 20h to 7Fh W Register: Register File Address
20
9-Bit Effective Address:
0 0
IRP
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FSR
00 00 FF FF FF FF 18 18 80 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 FF FF
00h : INDF 01h : TMR0 02h : PCL 03h : STATUS 04h : FSR 20h 21h 22h 23h 7Dh 7Eh 7Fh 80h
Slide 29
LOOP
bcf STATUS,IRP movlw 0x20 movwf FSR clrf INDF incf FSR,f btfss FSR,7 goto LOOP <next instruction>
11002 GS2
Program Memory Organization

O
Program memory is divided into four 2k14 pages Required to maintain single word/single cycle execution Paging is only a concern when using the call or goto instructions, or when directly modifying the program counter
0000h 0004h
14-bits Reset Reset Vector Vector Interrupt Interrupt Vector Vector 2k
Page Page 0 0
PCH PCH = = 00h 00h 0800h
Page Page 1 1
PCH PCH = = 08h 08h
2k
1000h
Page Page 2 2
PCH PCH = = 10h 10h
2k
1800h
Page Page 3 3
PCH PCH = = 18h 18h 1FFFh
11002 GS2 Slide
2k
30
Program Counter
PCH
12 11 10 9 8 7 6 5
PCL
4 3 2 1 0
Program Counter
O O O O O O
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
13-bit PC can access up to 213 = 8192 words Contains address of NEXT instruction (pipelining) Lower byte accessible in data memory as PCL Upper byte indirectly accessible via PCLATH Runs freely across page boundaries Events that modify PC out of sequence:
Interrupts Instructions: CALL, GOTO, RETURN, RETLW, RETFIE Any instruction that uses the PCL register as an operand
11002 GS2 Slide 31
PC Absolute Addressing
CALL and GOTO Instructions:
13 12 11 10 9 8 7 6 5 4 3 2 1 0
Opcode Opcode
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
PC Absolute Addressing (Program Memory)

Jump to another program memory location out of PC sequence Call a subroutine
Used by the CALL and GOTO instructions

11-bits of the required 13 address bits are encoded in the instruction 2 additional bits will come from the PCLATH register
Used when performing Computed Goto operation

Address to jump to is calculated by the program Computed address is written directly into the Program Counter
11002 GS2 Slide 32
14-Bit CALL or GOTO Instruction in Program Memory
13 12 11 10 9 8 7 6 5 4 3 2 1 0
Opcode Opcode PCLATH Register in Data Memory

7 6 5 4 3 2 1 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
2-Bits From PCLATH

12 11 10 9 8 7 6 5
11-Bits From Instruction

4 3 2 1 0
0 0
0 0
0 0 PCH PCH
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
PCL PCL
13-Bit Program Counter
11002 GS2
Slide
33
Example: Jumping to code located in a different program memory page. PCLATH Register
7 6 5 4 3 2 1 0
CALL Instruction in Program Memory

13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0
0 0
0 0
0 0
0 0
Opcode Opcode
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
W Register
Program Counter - PCH:PCL
FF
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
MySubroutine
org 0x0020 movlw HIGH MySubroutine movwf PCLATH call MySubroutine org 0x1250 <do something useful> return
11002 GS2 Slide 34
CALL / RETURN Stack

0020 0021 0022 0023 0024 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 100A movlw movwf call call bsf bsf call return bsf call return bsf return bsf call return HIGH MySub1 PCLATH MySub1 MySub4 PORTB,7 PORTB,0 MySub2 PORTB,1 MySub3 PORTB,2 PORTB,3 MySub2
13-bit Program Counter
0020
0 1 2 3 4 5 6 7 13-bit x 8-Level Return Address Stack
MySub1
MySub2
MySub3 MySub4
11002 GS2
Slide
35
PC Relative Addressing
W Register
FF
8-bit Data Bus
To write to PC:
n Write high byte to PCLATH o Write low byte to PCL (PCH will be loaded with value from PCLATH)
PCLATH
FF
PCH PCL
FF
FF
movlw movwf movlw movwf
HIGH 0x1250 PCLATH LOW 0x1250 PCL
11002 GS2
Slide
36
PC Relative Addressing: Lookup Table

ORG 0x0020 ;Page 0 movlw HIGH SevenSegDecode Example: Use a lookup movwf PCLATH table with relative movlw .5 addressing to retrieve the call SevenSegDecode movwf PORTB bit pattern to display a digit on a 7-segment LED ORG 0x1800 ;Page 3 SevenSegDecode: addwf PCL,f retlw b00111111 ;0 retlw b00000110 ;1 retlw b01011011 ;2 retlw b01001111 ;3 retlw b01100110 ;4 retlw b01101101 ;5 retlw b01111101 ;6 retlw b00000111 ;7 retlw b01111111 ;8 retlw b01101111 ;9
PIC MCU
11002 GS2
Slide
37
Special Features Overview

11002 GS2
Slide
38
Configuration Word
CP CP bit 1 -DEBUG DEBUG WRT1 WRT1 WRT0 WRT0 CPD CPD LVP LVP BOREN BOREN --PWRTEN PWRTEN WDTEN WDTEN FOSC1 FOSC1 FOSC0 FOSC0 bit 0
Located in program memory space, outside the reach of the program counter Used to setup device options:
Code Protection Oscillator Mode Watchdog Timer Power Up Timer Brown Out Reset Low Voltage Programming Flash Program Memory Write
Only readable at program time on most PIC16 devices

11002 GS2 Slide 39
PIC16 Oscillator Options

XT XT HS HS LP LP RC RC INTRC INTRC
O
Standard Standard frequency frequency crystal crystal oscillator oscillator High High frequency frequency crystal crystal oscillator oscillator Low Low frequency frequency crystal crystal oscillator oscillator External External RC RC oscillator oscillator Internal Internal RC RC oscillator oscillator
100kHz 100kHz - 4MHz 4MHz 4MHz 4MHz - 20MHz 20MHz 5kHz 5kHz - 200kHz 200kHz DC DC - 4MHz 4MHz 4 4 or or 8 8 MHz MHz 2% 2%
Selectable clock options provide greater flexibility for the designer:

LP Oscillator designed to draw least amount of current RC or INTRC provide ultra low cost oscillator solution XT optimized for most commonly used oscillator frequencies HS optimized to drive high frequency crystals or resonators
Speed ranges are guidelines only

11002 GS2 Slide 40
POR, OST, PWRT

O
POR: Power On Reset

With MCLR tied to VDD, a reset pulse is generated when VDD rise is detected Device is held in reset for 72ms (nominal) to allow VDD to rise to an acceptable level (after POR only) Holds device in reset for 1024 cycles to allow crystal or resonator to stabilize in frequency and amplitude; not active in RC modes; used only after POR or Wake Up from SLEEP
11002 GS2 Slide 41
PWRT: Power Up Timer
OST: Oscillator Start-up Timer
Sleep Mode
O
The processor can be put into a power-down mode by executing the SLEEP instruction
System oscillator is stopped Processor status is maintained (static design) Watchdog timer continues to run, if enabled Minimal supply current is drawn - mostly due to leakage (0.1 2.0A typical)
Events Events that that wake wake processor processor from from sleep sleep
MCLR MCLR WDT WDT INT INT TMR1 TMR1 ADC ADC CMP CMP Master Master Clear Clear Pin Pin Asserted Asserted (pulled (pulled low) low) Watchdog Watchdog Timer Timer Timeout Timeout INT INT Pin Pin Interrupt Interrupt Timer Timer 1 1 Interrupt Interrupt (or (or also also TMR3 TMR3 on on PIC18) PIC18) A/D A/D Conversion Conversion Complete Complete Interrupt Interrupt Comparator Comparator Output Output Change Change Interrupt Interrupt
CCP Input CCP Input Capture Capture Event Event PORTB PORTB PORTB PORTB Interrupt Interrupt on on Change Change 2 SSP Synchronous C SSP Synchronous Serial Serial Port Port (I (I2 C Mode) Mode) Start Start // Stop Stop Bit Bit Detect Detect Interrupt Interrupt PSP PSP Parallel Parallel Slave Slave Port Port Read Read or or Write Write
11002 GS2 Slide 42 2007 Microchip Technology Incorporated. All Rights Reserved.
Watchdog Timer
O O O O O O O
Helps recover from software malfunction Uses its own free-running on-chip RC oscillator WDT is cleared by CLRWDT instruction Enabled WDT cannot be disabled by software WDT overflow resets the chip Programmable timeout period: 18ms to 3.0s typical Operates in SLEEP; on time out, wakes up CPU
11002 GS2
Slide
43
BOR Brown Out Reset

O
When voltage drops below a particular threshold, the device is held in reset Prevents erratic or unexpected operation Eliminates need for external BOR circuitry
11002 GS2 Slide 44
PBOR Programmable Brown Out Reset

O
Configuration Option (set at program time) Cannot be enabled / disabled in software Four selectable BVDD trip points: 2.5V Minimum VDD for OTP PIC MCUs 2.7V 4.2V 4.5V
For other thresholds, use an external supervisor (MCP1xx, MCP8xx/TCM8xx, or TC12xx)

11002 GS2 Slide 45
(P)BOR Brown Out Reset

O
Holds PIC MCU in reset until ~72ms after VDD rises back above threshold
11002 GS2
Slide
46
PLVD Programmable Low Voltage Detect

O
Early warning before brown out 16 selectable trip points:

1.8V up to 4.5V in 0.1 to 0.2V steps External analog input
VDD LVDIN LVDCON
16-bit Multiplexer VREF LVDIN
LVDIF
Internal VREF
11002 GS2
Slide
47
In-Circuit Serial Programming

O O
Only two pins required for programming Convenient for In-System Programming of
Calibration Data Serialization Data
Pin Pin V VPP PP V VDD DD V VSS SS RB6 RB6 RB7 RB7
Function Function Programming Programming Voltage Voltage = = 13V 13V Supply Supply Voltage Voltage Ground Ground Clock Clock Input Input Data Data I/O I/O & & Command Command Input Input
Supported by MPLAB PM3 & ICD2

Application PCB VDD VDD
MCLR/VPP
ICSP Connector ICSP Connector
VDD VSS RB6 RB7
To application circuit
Isolation circuits
11002 GS2
Slide
48
I/O Ports
O O O
High Drive Capability Can directly drive LEDs Direct, single cycle bit manipulation Each pin has individual direction control under software All pins have ESD protection diodes Pin RA4 is usually open drain All I/O pins default to inputs (high impedance) on startup All pins multiplexed with analog functions default to analog inputs on startup
11002 GS2 Slide 49
O O O
I/O Pin Conceptual Diagram

Bit 1 of TRISB Register
movwf PORTB
Write Operation
PORTB Bit 1 Latch
1 = RB1 is input 0 = RB1 is output
Bit 1 of Data Bus
RB1
Read Operation
movf PORTB,w
I/O Ports
Bit n in TRISx controls the data direction of Bit n in PORTx 1 = Input, 0 = Output
11002 GS2 Slide 51
Hands-on Exercises
11002 GS2
Slide
52
MPLAB ICD2
11002 GS2
Slide
53
PICDEM 2 Plus Board
11002 GS2
Slide
54
MPASM Assembler Template

1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 LIST LIST p=16f877a p=16f877a #include #include <p16f877a.inc> <p16f877a.inc> org org goto goto 0x0000 0x0000 START START ;Explicitly ;Explicitly declare declare processor processor ;Include ;Include register register label label definitions definitions ;Put ;Put next next line line of of code code at at address address 0x0000 0x0000 ;Reset Vector ;Reset Vector ;Put ;Put next next line line of of code code at at address address 0x0004 0x0004 ;Interrupt ;Interrupt Vector Vector ;Your ;Your code code goes goes here here ;Tell ;Tell MPASM MPASM that that this this is is the the end end
RESET_V RESET_V
INT_V INT_V START START
org org 0x0004 0x0004 retfie retfie {Begin {Begin your your code code here} here} END END
O O
If not using interrupts, lines 8 and 9 could be omitted The labels in the left column may be anything you want; these are just examples
11002 GS2 Slide 55
Specifying the Radix

O O
By default, MPASM assembler expects numbers in hexadecimal Default can be changed through IDE or by adding r=hex or r=dec as a parameter to the LIST directive:
LIST LIST p=16f877a, p=16f877a, r=dec r=dec
Good programming practice suggests that a numbers radix be specified explicitly: Radix MPASM Syntax
Binary b10101010 Decimal d25 or .25 Hexadecimal h2A or 0x2A

Lab 1: The Task

O
Turn on LED connected to bit 0 of PORTB (RB0)
11002 GS2
Slide
57
Lab 1: Program Structure

Switch to Bank 1
1 Instruction
Load number into W
4 Instructions
Move value to TRISB
1 Instruction
Switch to Bank 0
1 Instruction: goto $ (Go to self)
11002 GS2
Slide
58
Lab 1: Template
11002 GS2
Slide
59
Lab 1: Solution
11002 GS2
Slide
60
Lab 1: Results
O
You have learned:

How to program a device and run the code using the MPLAB ICD2 How to configure an I/O port How to manipulate I/O pins How to code an infinite loop (the equivalent of while(1) in C)
11002 GS2
Slide
61
Lab 2: The Task

O
Make the LED connected to bit 0 of PORTB (RB0) blink
11002 GS2
Slide
62
Lab 2: The Task

O
A delay is required to make the blinking slow enough for the human eye At 4MHz, one instruction executes in 1s A 16-bit software counter is sufficient to implement the delay
11002 GS2 Slide 63
Naming Registers/Constants
O
Equate Method: MyReg0 equ 0x20 MyReg1 equ 0x21 MyReg2 equ 0x23
;MyReg0 = 0x20 ;MyReg1 = 0x21 ;MyReg2 = 0x23
Constant Block Method: CBLOCK 0x20 MyReg0 ;MyReg0 = 0x20 MyReg1: 2 ;MyReg1 = 0x21 MyReg2 ;MyReg2 = 0x23 ENDC
11002 GS2 Slide 64

Taken from Lab 1
1 Instruction 1 Instruction Subroutine Call 1 Instruction 1 Instruction Subroutine Call
11002 GS2
Slide
65

Delay Subroutine
1 Instruction
Hint: Use decfsz

1 Instruction
1 Instruction
1 Instruction
1 Instruction
Lab 2: Template Part 1
11002 GS2
Slide
67
11002 GS2
Slide
68
Lab 2: Solution Part 1
11002 GS2
Slide
69
11002 GS2
Slide
70
Lab 2: Results
O
You have learned:

How to define register labels How to implement a loop How to implement software delays How to use a skip instruction How to call a subroutine
11002 GS2
Slide
71
Lab 3: The Task

O
Using one of the rotate instructions, move the illuminated LED across the lower 4 bits of PORTB. When it reaches one side, send it back to the start.
RB3 RB2 RB1 RB0
11002 GS2
Slide
72

Same setup code from Lab 1 1 Instruction 1 Instruction
Rember: The rotate instructions operate on 9-bits, with the Carry bit in the STATUS register as the 9th bit
1 Instruction
1 Instruction 1 Instruction Call same subroutine from Lab 2
11002 GS2
Slide
73
11002 GS2
Slide
74
11002 GS2
Slide
75
11002 GS2
Slide
76
11002 GS2
Slide
77
Lab 3: Results
O
You have learned:

How to use the rotate instructions How to use the bit test & skip instructions
11002 GS2
Slide
78
Lab 4: The Task

O
Same as Lab 3, but this time make the direction of rotation change when the LED is rotated to either end
11002 GS2
Slide
79

START
Same setup code from Lab 1
Setup PORTB
bsf STATUS,C
1 Instruction 1 Instruction Subroutine Call
No
Set Carry Bit
Rotate Left PORTB
Delay
2 Instructions 1 Instruction 1 Instruction Subroutine Call 2 Instructions

RB3 = 1?
Yes
Rotate Right PORTB
Delay
No
RB0 = 1?
Yes
Slide 80
Lab 4: Template
O
Setup is identical to Lab 3 up to the LOOP

Lab Lab 3: 3: Rotating Rotating LED LED -- Continued Continued 18 18 19 19 20 20 21 21 22 22 23 23 24 24 25 25 26 26 27 27 28 28 29 29 30 30 31 31 32 32 33 33 34 34 35 35 36 36 37 37 bsf bsf LEFT LEFT STATUS,C STATUS,C ;Set ;Set carry carry bit bit for for initial initial rotate rotate ;Rotate ;Rotate PORTB PORTB to to left left ;Call ;Call delay delay routine routine ;Is ;Is the the LED LED on on RB3 RB3 (PORTB,3) (PORTB,3) on? on? ;if ;if no, no, rotate rotate left left again again ;Rotate ;Rotate PORTB PORTB to to right right ;Call delay routine ;Call delay routine ;Is ;Is the the LED LED on on RB0 RB0 (PORTB,0) (PORTB,0) on? on? ;if ;if no, no, rotate rotate right right again again ;if ;if yes, yes, rotate rotate left left ;Decrement ;Decrement COUNTERL COUNTERL ;If ;If not not zero, zero, keep keep decrementing decrementing COUNTERL COUNTERL ;Decrement COUNTERH ;Decrement COUNTERH ;If ;If not not zero, zero, decrement decrement COUNTERL COUNTERL again again ;Return to main subroutine ;Return to main subroutine
st {1 {1st Instruction} Instruction} nd nd {2 Instruction} {2 Instruction} rd rd {3 Instruction} {3 Instruction} th th {4 {4 Instruction} Instruction} th {5 Instruction} {5th Instruction} th th Instruction} {6 {6 Instruction} th {7 {7th Instruction} Instruction} th th {8 Instruction} {8 Instruction} th th {9 Instruction} {9 Instruction}
RIGHT RIGHT
DELAY DELAY
decfsz decfsz goto goto decfsz decfsz goto goto return return END END
COUNTERL COUNTERL DELAY DELAY COUNTERH COUNTERH DELAY DELAY
11002 GS2
Slide
81
Lab 4: Solution
11002 GS2
Slide
82
Lab 4: Results
O
You have learned:

How to make decisions in software and take different courses of action
11002 GS2
Slide
83
Lab 5: The Task

O
Use a lookup table to obtain the bit pattern to be displayed on PORTB
11002 GS2
Slide
84

1 Instruction Lab 1 Setup Code 1 Instruction 2 Instructions 1 Instruction 1 Instruction 1 Instruction Subroutine Call 1 Instruction
3 Instructions
1 Instruction
11002 GS2
Slide
85

Lab Lab 5: 5: Lookup Lookup Table Table 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 RESET_V 11 RESET_V 12 12 13 START 13 START 14 14 15 15 16 16 17 17 18 18 19 19 20 20 LIST LIST p=16f877a p=16f877a #include #include <p16f877a.inc> <p16f877a.inc> cblock cblock 0x020 0x020 COUNTERL COUNTERL COUNTERH COUNTERH endc endc org org goto goto 0x0000 0x0000 START START
;Reset ;Reset Vector Vector ;Clear ;Clear PORTB PORTB output output latches latches ;Switch ;Switch to to bank bank 1 1 ;Load value to make ;Load value to make lower lower 4 4 bits bits outputs outputs ;Move value to TRISB ;Move value to TRISB ;Switch ;Switch to to bank bank 0 0 ;Clear ;Clear index index into into table table ;Load ;Load W W with with high high byte byte of of TABLE TABLE address address ;Move ;Move W W to to PCLATH PCLATH
clrf PORTB clrf PORTB bsf STATUS,RP0 bsf STATUS,RP0 movlw b11110000' movlw b11110000' movwf TRISB movwf TRISB bcf STATUS,RP0 bcf STATUS,RP0 st st {1 Instruction} {1 Instruction} nd nd {2 Instruction} {2 Instruction} rd rd {3 Instruction} {3 Instruction}
;CONTINUED ;CONTINUED ON ON NEXT NEXT SLIDE SLIDE

11002 GS2
Slide
87
11002 GS2
Slide
88

Lab Lab 5: 5: Lookup Lookup Table Table 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 RESET_V 11 RESET_V 12 12 13 START 13 START 14 14 15 15 16 16 17 17 18 18 19 19 20 20 LIST LIST p=16f877a p=16f877a #include #include <p16f877a.inc> <p16f877a.inc> cblock cblock 0x020 0x020 COUNTERL COUNTERL COUNTERH COUNTERH endc endc org org goto goto clrf clrf bsf bsf movlw movlw movwf movwf bcf bcf clrf clrf movlw movlw movwf movwf 0x0000 0x0000 START START PORTB PORTB STATUS,RP0 STATUS,RP0 b11110000' b11110000' TRISB TRISB STATUS,RP0 STATUS,RP0 INDEX INDEX HIGH HIGH TABLE TABLE PCLATH PCLATH
;Reset ;Reset Vector Vector ;Clear ;Clear PORTB PORTB output output latches latches ;Switch to bank 1 ;Switch to bank 1 ;Load ;Load value value to to make make lower lower 4 4 bits bits outputs outputs ;Move ;Move value value to to TRISB TRISB ;Switch ;Switch to to bank bank 0 0 ;Clear ;Clear index index into into table table ;Load W with high byte ;Load W with high byte of of TABLE TABLE address address ;Move ;Move W W to to PCLATH PCLATH
;CONTINUED ;CONTINUED ON ON NEXT NEXT SLIDE SLIDE

11002 GS2
Slide
90
11002 GS2
Slide
91
Lab 5: Results
O
You have learned:

How to implement a lookup table How to retrieve data from a lookup table How to call a subroutine on another page How to perform a computed goto
11002 GS2
Slide
92
Summary
O O O O
PIC16 Architecture PIC16 Instruction Set PIC16 Memory Organization Simple Programming Techniques
11002 GS2
Slide
93
References
O
PIC MCU Mid-Range Family Reference Manual (DS33023A) Microchip Technology Programming and Customizing PICmicro Microcontrollers by Myke Predko Design with PIC Microcontrollers by John B. Peatman
11002 GS2 Slide 94
References
O
123 PIC Microcontroller Experiments for the Evil Genius by Myke Predko
11002 GS2
Slide
95
Thank You
11002 GS2
Slide
96
Trademarks
The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KeeLoq, KeeLoq logo, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Linear Active Thermistor, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies.
11002 GS2
Slide
97

Unversity of Microchip

Diunggah oleh

Informasi Dokumen

Deskripsi Asli:

Hak Cipta

Format Tersedia

Bagikan dokumen Ini

Bagikan atau Tanam Dokumen

Opsi Berbagi

Apakah menurut Anda dokumen ini bermanfaat?

Apakah konten ini tidak pantas?

Hak Cipta:

Format Tersedia

Unversity of Microchip

Diunggah oleh

Hak Cipta:

Format Tersedia

11002 GS2

Getting Started with PIC MCU Mid-Range

2005 Microchip Technology Incorporated. All Rights Reserved.

2007 Microchip Technology Incorporated. All Rights Reserved.

2007 Microchip Technology Incorporated. All Rights Reserved.

Von Neumann Architecture:

2007 Microchip Technology Incorporated. All Rights Reserved.

Instruction fetch is overlapped with execution of previously fetched instruction

Fetch Execute Fetch Execute

Fetch Execute Fetch Flush

51 SUB1 movf PORTB,w 52 return 53 SUB2 movf PORTC,w 54 return

Fetch Execute Fetch Execute Fetch Flush

51 SUB1 movf PORTB,w 52 return 53 SUB2 movf PORTC,w 54 return

Fetch Execute Fetch

51 SUB1 movf PORTB,w 52 return 53 SUB2 movf PORTC,w 54 return

Fetch Execute Fetch Execute Fetch

51 SUB1 movf PORTB,w 52 return 53 SUB2 movf PORTC,w 54 return

Fetch Execute Fetch Execute Fetch Execute Fetch

51 SUB1 movf PORTB,w 52 return 53 SUB2 movf PORTC,w 54 return

Fetch Execute Fetch Execute Fetch Execute Fetch Flush

51 SUB1 movf PORTB,w 52 return 53 SUB2 movf PORTC,w 54 return

Fetch Execute Fetch Execute Fetch Execute Fetch Flush

51 SUB1 movf PORTB,w 52 return 53 SUB2 movf PORTC,w 54 return

Fetch Execute Fetch

Fetch Execute Fetch Execute Fetch Execute Fetch Flush

51 SUB1 movf PORTB,w 52 return 53 SUB2 movf PORTC,w 54 return

Fetch Execute Fetch Execute Fetch

Fetch Execute Fetch Execute Fetch Execute Fetch Flush Fetch

51 SUB1 movf PORTB,w 52 return 53 SUB2 movf PORTC,w 54 return

Fetch Execute Fetch Execute Fetch Flush

Long Word Instruction

8-bit Instruction on typical 8-bit MCU

Limits Bandwidth Increases Memory Size Requirements

14-bit Program Memory

14-bit Instruction on PIC16 8-bit MCU

Separate busses allow different widths 2k x 14 is roughly equivalent to 4k x 8

Register File Concept

0Ah 0Bh 0Ch 0Dh 0Eh 0Fh

Decoded Instruction from Program Memory:

Arithmetic/Logic Function to be Performed

2007 Microchip Technology Incorporated. All Rights Reserved.

Instruction Set Overview

2007 Microchip Technology Incorporated. All Rights Reserved.

Instruction Set Overview

2007 Microchip Technology Incorporated. All Rights Reserved.

Instruction Set Overview

2007 Microchip Technology Incorporated. All Rights Reserved.

PIC16 Instruction Set

2007 Microchip Technology Incorporated. All Rights Reserved.

PIC16 Visual Interpreter

Data Memory Organization

0EFh 07Fh 0FFh

Accesses Accesses 70h 70h 7Fh 7Fh Bank 1

Accesses Accesses 70h 70h 7Fh 7Fh Bank 2

Accesses Accesses 70h 70h 7Fh 7Fh Bank 3

Data Memory Organization

Device Specific Registers

IRP: Register Bank Select (used for Indirect addressing)

RP1:RP0: Register Bank Select Bits (used for direct addressing)

TO: Time-out bit

PD: Power-down bit

DC: Digit cary / borrow bit

C: Carry / borrow bit