September 2012

EC2303 COMPUTER ARCHITECTURE AND ORGANIZATION UNIT IV PART A 1) What is cache memory? The small and fast RAM units are called as caches. When the execution of an instruction calls for data located in the main memory, the data are fetched and a copy is placed in the cache. Later if the same data is required it is read directly from the cache. Processor Cache Main memory

2) What is the use of cache memory? The use of cache memories solves the memory access problem. In particular, when a cache is included on the same chip as the processor, access time to the cache is usually the same as the time needed to perform other basic operations inside the processor. This makes it possible to stages, and the clock period is chosen to correspond to the longest one. 3) Define cache line. Cache block is used to refer to a set of contiguous address locations of some size. Cache block is also referred to as cache line. 4) What are the two ways in which the system using cache can proceed for a write operation? * Write through protocol technique * Write back or copy back protocol technique 5) How is the average access time of two level memory systems computed? May 2010 The average access time experienced by the processor in a system with 2 levels of caches is tave = h1C1 + (1 - h1) h2C2 + (1 - h1) (1 - h2) M where h1 Hit rate in the L1 cache h2 Hit rate in the L2 cache C1 Time to access information in the L1 cache C2 Time to access information in the L2 cache M Time to access information in the memory 6) Define MFC. To accommodate the variability in response time, the processor waits until it receives an indication that the requested read operation has been completed. The control signal used for this purpose is known as Memory-Function-Completed (MFC).

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7) Compare vertical organization and horizontal organization. Vertical organization Highly encoded schemes Specify only a small number of control signals. Operating speed is high. Horizontal organization Minimally encoded schemes Many resources can be controlled. Operating speed is low. 8) What is byte addressable memory? The assignment of successive addresses to successive byte locations in the memory is called byte addressable memory. 9) What is the maximum size of the memory that can be used in a 16-bit computer and 32-bit computer? The maximum size of the memory that can be used in a 16-bit computer is 2 = 64K memory locations. The maximum size of the memory that can be used in a 32-bit computer is 2 = 4G memory locations. 10) Define memory access time? The time required to access one word is called the memory access time. 11) Define memory cycle time? It is the minimum time delay required between the initiations of two successive memory operations. Ex: The time between two successive read operations. 12) When is a memory unit called as RAM? Memory units is called as RAM if any location can be accessed for a read or write operation in some fixed amount of time that is independent of the locations address. 13) What is MMU? MMU is the Memory Management Unit. It is a special memory control circuit used for implementing the mapping of the virtual address space onto the physical memory. 14) Define static memories? A memory that consists of circuits capable of retaining their state as long as power is applied is called Static memories.

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15) What are the characteristics of semiconductor RAM memories? * They are available in a wide range of speeds. * Their cycle time range from 100ns to less than 10ns. * They replaced the expensive magnetic core memories. * They are used for implementing memories. 16) Why SRAMs are said to be volatile? Because their contents are lost when power is interrupted. So SRAMs are said to be volatile. 17) What are the characteristics of SRAMs? * SRAMs are fast. * They are volatile. * They are of high cost. * Less density. 18) What are the characteristics of DRAMs? * Low cost. * High density. * Refresh circuitry is needed. 19) Define memory latency? It is used to refer to the amount of time it takes to transfer a word of data to or from the memory. 20) What are asynchronous DRAMs? In asynchronous DRAMs, the timing of the memory device is controlled asynchronously. A specialized memory controller circuit provides the necessary control signals RAS and CAS that govern the timing. The processor must take into account the delay in the response of the memory. Such memories are asynchronous DRAMs. 21) Define bandwidth? When transferring blocks of data, it is of interest to know how much time is needed to transfer an entire block. Since blocks can be variable in size it is useful to define a performance measure in terms of number of bits or bytes that can be transferred in one second. This measure is often referred to as the memory bandwidth. 22) What is double data rate SDRAMs? Double data rates SDRAMs are those which can transfer data on both edges of the clock and their bandwidth is essentially doubled for long burst transfers.

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23) What are SIMMs and DIMMs? SIMMs are Single In-line Memory Modules. DIMMs are Dual In-line Memory Modules. Such modules are an assembly of several memory chips on a separate small board that plugs vertically into a single socket on the motherboard. 24) What is memory controller? A memory controller is a circuit which is interposed between the processor and the dynamic memory. It is used for performing multiplexing of address bits. It provides RAS-CAS timing. It also sends R/W and CS signals to the memory. When used with DRAMs chips, which do not have self refreshing capability, the memory controller has to provide all the information needed to control the refreshing process. 25) Differentiate static RAM and dynamic RAM? Sl.No 1 2 3 4 5 Static RAM They are fast They are very expensive They retain their state indefinitely They require several transistors Low density Dynamic RAM They are slow They are less expensive They donot retain their indefinitely They require less transistors High density May 2008

state

26) What are the features of PROM? * They are programmed directly by the user * Faster * Less expensive * More flexible 27) Why EPROM chips are mounted in packages that have transparent window? Since the erasure requires dissipating the charges trapped in the transistors of memory cells. This can be done by exposing the chip to UV light. 28) What are the disadvantages of EPROM? The chip must be physically removed from the circuit for reprogramming and its entire contents are erased by the ultraviolet light. 29) What are the advantages and disadvantages of using EEPROM? The advantages are that EEPROMs do not have to be removed for erasure. Also it is possible to erase the cell contents selectively. The only disadvantage is that different voltages are needed for erasing, writing and reading the stored data.

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September 2012

30) Define flash memory? It is an approach similar to EEPROM technology. A flash cell is based on a single transistor controlled by trapped charge just like an EEPROM cell. 31) What is locality of reference? May 2008, Nov 2009 The point that many instructions in localized areas of the program are executed repeatedly during some time period, and the remainder of the program is accessed relatively infrequently is referred to as locality of reference. 32) What are the two aspects of locality of reference? Define them. Two aspects of locality of reference are temporal aspect and spatial aspect. Temporal aspect is that a recently executed instruction is likely to be executed again very soon. The spatial aspect is that instructions in close proximity to a recently executed instruction are also to be executed soon. 33) Explain MDR and MAR The data and address lines of the external memory bus connected to the internal processor bus via the memory data register. MDR, and the memory address register, MAR, respectively. Register MDR has two inputs and two outputs. Data may be loaded into MDR either from the memory bus or from the internal processor bus. The data stored in MDR may be placed on either bus. The input of MAR is connected to the internal bus, and its output is connected to the external bus. 34) Define datapath. The registers, the ALU, and the interconnecting bus are collectively referred to as the datapath. 35) Define access time for magnetic disks? The sum of seek time and rotational delay is called as access time for disks. Seek time is the time required to move the read/write head to the proper track. Rotational delay or latency is the amount of time that elapses after the head is positioned over the correct track until the starting position of the addressed sector passes under the read/write head. 36) What is virtual memory? Techniques that automatically move program and data blocks into the physical main memory when they are required for execution are called as virtual memory. 37) What is virtual address? The binary address that the processor used for either instruction or data called as virtual address. 38) What is virtual page number? Each virtual address generated by the processor whether it is for an instruction fetches interpreted as a virtual page. 39) What is TLB? May 2006, May 2010 Translation Look aside Buffer (TLB) is an on chip cache which is used to store the most recently used page table entries. The TLB holds upto 32 page table entries.
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40) Describe the two control signals used for register transfer. For each register, two control signals are used to place the contents of that register on the bus or to load data on the bus into the register. The input and output of register Ri are connected to the bus via switches controlled by the signals Riin and Riout, respectively. When Riin is set to 1, the data on the bus are loaded into Ri. Similarly, when Riout is set to 1, the contents of register Ri are placed on the bus. While Riout is equal to 0, the bus can be used for transferring data from other registers.

41) Calculate the effective access time if average page fault service time of 20 ms and a memory access time of 80 ns. Let us assume the probability of a page fault 10%. Nov 2009 Data given: Page fault service time = 20 ms Memory access time, ma = 80 ns Probability of a page fault, = 10% = 0.1 Effective access time = (1 ) x ma + x page fault service time = (1 0.1) x 80 x 10-9 + 0.1 x 20 x 10-3 sec = 2.000072 x 10-3 sec = 2 ms 42) What is data stripping? Nov 2009 In a RAID system, a single large file is stored in several separate disk units by breaking the file up into a number of smaller pieces and storing these pieces on different disks. This is called data stripping. 43) How many 128 x 4 RAM memory chips are required to construct RAM memory system of 1 K bytes? May 2009 1 Kbytes = 210 x 8 bits = 211 x 4 = 24 x 27 x 4 = 24 x (128 x 4) = 16 (128 x 4) Therefore 16 number of (128 x 4) RAM chips are required to construct RAM memory of 1 Kbytes. 44) Compare SDRAM with DDR SDRAM. May 2009

SDRAM DDR SDRAM Synchronous Dynamic Random Access Double Data Rate Synchronous Dynamic Memory Random Access Memory Cell array is organized as only one Cell array is organized in two memory banks. memory bank. Performs all actions on the rising edge of Performs all actions on both the edges of the the clock. clock. High memory band width Memory bandwidth is twice that of SDRAM

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45) What is the formula for calculating the average access time experienced by the processor? t ave =hc +(1-h)M Where h =Hit rate M=miss penalty C=Time to access information in the cache. 46) Give the features of a ROM cell. May 2008 Non volatile memory devices that retain the stored information if power is turned off. A small amount of nonvolatile memory can had the instruction large execution results in loading the boot program from the disk. Since its normal operation involves only reading of stored data, a memory of this type is called ROM. 47) What is a hit? A successful access to data in cache memory is called hit. 48) Define hit rate? The number of hits stated as a fraction of all attempted access. 49) Define miss rate? It is the number of misses stated as a fraction of attempted accesses. 50) Define miss penalty? The extra time needed to bring the desired information into the cache.

PART B 1) Describe the organization of a typical RAM chip.

Refer page: 407 2) Explain about Static & Dynamic memory systems. Refer page: 400 3) Write note on: i) ROM technologies. ii) Set associative mapping of cache. Refer page: 415 & 462 4) Explain about Cache memory in detail. Refer page: 452 Nov 2006 Nov 2007 May 2007

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5) What is mapping? Explain its types in detail. (OR) Explain various mechanisms of mapping main memory address into cache memory addresses. May 2006, May 2008 Refer page: 457

6) Explain the performance factors in memory.

Refer page: 429 7) Explain the concept of memory hierarchy. Refer page: 426

May 2006

Nov 2006, Nov 2007

8) Explain how the virtual address is converted into real address in a paged virtual memory system. May 2008 Refer page: 438 9) Discuss the address translation mechanism and the different page replacement policies used in a virtual memory system. May 2006 Refer page: 432 10) Describe the working principle of a typical magnetic disk. Refer page: 423 May 2008

11) How a virtual address gets translated into a physical address? Explain in detail with a neat diagram. Explain the use of TLB. Nov 2006, May 2007, May 2008, Nov 2009 Refer page: 432 12) What is virtual memory? How is it implemented? Refer page: 438 13) Discuss the various memory types and mention their advantages. Refer page: 400 14) Explain the operation of Associative cache memories. Refer page: 452 15) Explain in detail internal organization of memory chip. Refer page: 407 Nov 2007

Nov 2009

Nov 2009

May 2010

16) Explain various types of optical memory in detail

Refer page: 424

May 2010

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