INTERCONNECT STRATEGIES

Loading Effects on Transmission Lines, Part 1

Device loading can influence critical transmission line characteristics, and the design of high-speed PCBs.
Ed. This PDF contains both parts 1 and 2 from the May and June issues.
WHEN DEVICES SUCH as ICs are

connected to highspeed PCB traces, their inductance and capacitance add to that traces inductance and ABE RIAZI capacitance, thus loading down the line1. This loading effect can alter certain transmission line properties, such as characteristic impedance (Zo) and propagation delay (Tpd), and hence influence the board design. Let us first consider Zo and Tpd formulas for two commonly occurring PCB trace geometries2, microstrip and stripline, when loading effects are negligible (i.e., unloaded line) as in Table 1. Equation 1, relating to characteristic impedance3,4 Zo of microstrip, is IPC recommended4. FIGURE 1 demonstrates the Zo of an unloaded microstrip vs. trace width (W) for four different values of trace height (substrate thickness) based on Equation 1. It is recommended5 that the results of Equation 1 be utilized only for conditions involving narrow

microstrip (i.e., when 0.1<W/H<2.0). Formulas for microstrip Zo suitable for skinny traces (W<H) and wide traces (W>H) are discussed by Howard Johnson et al.5. This plot assumes a relative dielectric constant Er = 4.25 for an FR-4 substrate. It utilizes a fixed trace thickness of .00141 (1 oz copper weight), and ignores effects due to soldermask. The impact of trace thickness variations on impedance is relatively small6 about 1 ohm per .001 (a thicker line produces smaller Zo). The effect of soldermask on microstrip Zo can also be easily estimated. Zo decreases by approximately 1 ohm/0.001 of soldermask thickness6. The influence of W, H and Er upon Zo are regarded as first order factors, whereas T and soldermask possess second order effects6 on characteristic impedance. For stripline, impedance formulas3,4 include Equations 3 and 4 (approximately equivalent). The latter formula4 is IPC recommended. Generally, formulas in TABLE 1 are approximations with higher accuracies achievable using field solvers.

TABLE 1. The characteristic impedance and propagation delay values for

(unloaded) microstrip and symmetric stripline are shown.

Parameter Characteristic Impedance (Microstrip) Propagation Delay (Microstrip) Characteristic Impedance (Stripline) Characteristic Impedance (Stripline) Propagation Delay (Stripline) Formula Zo = 87/ Er+1.41 x {ln[5.98H / (0.8W+T)]} (Equation 1) Tpd = 1.017 0.475Er + 0.67 (Equation 2) Zo = (60 / Er) x {ln[4B / (0.67W(0.8+T / W))]} (Equation 3) Zo = (60 / Er) x {ln[(2B + T) / (0.8W+T)]} (Equation 4) Tpd = 1.017 Er (Equation 5) Unit
T H

PCB Geometry
W

Microstrip nS/ft Signal layer Dielectric substrate Ground/ Power layer

W

T H B

nS/ft

Stripline

Er is a relative dielectric constant of the substrate material. W is trace width. H is height of microstrip relative to reference power/ground plane (i.e., dielectric substrate thickness). T is thickness of trace. B is separation of the two plane layers (for the symmetric stripline configuration).

FIGURE 2, based on Equation 4, shows unloaded characteristic impedance of a symmetric stripline (trace equidistant from two planes) as a function of trace width for four values (B) of plane-to-plane spacing. For Figure 2, it is assumed that Er = 4.25, and T= .00141. The Zo formulas (Equations 1, 3 and 4) reveal that the physical dimensions appear as arguments to a natural logarithm (log to base e=2.7182818 as opposed to common log having a base 10) function. Subsequently, impedance varies slowly as a function of trace geometry. This indicates that large changes in physical dimensions cause a small impact5 on impedance. This is desirable and implies that impedance is not very sensitive to physical dimensions. (Impedance sensitivity5 is the percent change in impedance per percent change in line width as revealed by the slope of the impedance function on a log-log plot.) The microstrip propagation delay expression3 in Equation 2 assumes that effective dielectric coefficient Er_eff (= 0.475Er + 0.67) is a constant, which is an approximation, since the microstrip propagation time can vary7,8 with trace width and height above the ground. The Tpd formulas for outer and inner layers (Equations 2 and 5, plotted in FIGURE 3) vary only with substrate dielectric constant, and indicate independence from physical trace dimensions within the first order approximations. Applying these formulas to FR-4 whose nominal Er = 4.25 (FR-4 Er can range4 from approximately 4.0 to 4.5) will yield a Tpd of ~ 1.67 nsec/ft and ~ 2.09 nsec/ft for microstrip and stripline, respectively. In Figure 3, the unit of propagation delay is nsec/ft. Another common unit for Tpd is psec/in. Since 1 nsec = 1000 psec and 1in = 1/12 ft,
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150

3 H (mils) 2.5
Tpd (nS/ft)

Stripline

Zo (ohms)

100 H=30 50 H=15 H=8 3 3 5 10 15 W (mils) H=3 20

2 1.5 1 3 3.5 4 4.5 5 5.5 Er

Microstrip

6.5

FIGURE 1. Microstrip impedance as a function of trace width is shown for several different height values. (All plots generated on MathCAD.) 100 80
Zo (ohms)

FIGURE 3. Propagation delay Tpd for outer and inner layers is shown as a function of the substrates relative dielectric constant, Er.

B (mils)

when routed as stripline but 5.5 if routed as microstrip. PCD&M

B=40 B=30 B=20 ABE (ABBAS) RIAZI ( ariazi@server works.com) is a senior signal integrity engineer with ServerWorks (a Broadcom company) in Santa Clara, CA.

60 40 20 3 3 5 10 15 W (mils)

B=10 20

FIGURE 2. This plot shows symmetric stripline Zo vs. W for several different values of B.

Ed. Part II will be published in the next installment of Interconnect Strategies.

values in nsec/ft can be multiplied by 83.33 (1000/12) to convert to psec/in. Conversely, psec/in is translated to nsec/ft by dividing by 83.333 or multiplying by 0.012 (1/83.333). The first example treats such unit conversions. Example 1. Converting 1.67 nsec/ft to its equivalent in psec/in requires multiplication by 83.333. Hence, 1.67 nsec/ft = 139.17 psec/in. Translation of 180 psec/in to nsec/ft is achieved by multiplying by 0.012, which yields 2.16 nsec/ft. The Tpd for microstrip is smaller than the Tpd for stripline, because the signal velocity (V) on outer layers is faster than V on inner layers, with Tpd and V being inversely related. One implication of this concept is described by the next example. Example 2. Layout solution space analyses9,10 often necessitate determining the minimum and maximum lengths for high-speed nets. Because trace velocity is faster for microstrip (than stripline), the traces on outer layers can be longer (as compared to inner layer routing), which is frequently easier to route. For instance, in one application it was ascertained by simulations that the maximum allowable high-speed trace length could be 5
20

ACKNOWLEDGEMENTS
The author would like to thank Peter Arnold for reviewing the manuscript, and Jeremy Plunkett and Dean Gonzales for their helpful discussions.

REFERENCES
1. Transmission Line Effects In PCB Applications, Motorola Semiconductor Application Note AN1051/D, 1990, P . 10, PP . A-1 to A-4. 2. Abe Riazi, Engineers Rule of Thumb Simplifies PCB Signal Integrity, EEdesign, August 19, 2002. 3. James K. Hollomon, Jr., Surface Mount Technology for PC Board Design, Howard W. Sams & Co., 1989. PP . 180-182. 4. Eric Bogatin, Signal Integrity Simplified, Prentice Hall, 2004, P . 130, P . 260, PP . 320-323. 5. Howard Johnson and Martin Graham, High-Speed Digital Design a Handbook of Black Magic, Prentice Hall, Inc., 1993. P . 181, P . 187, P . 433. 6. Eric Bogatin, When Accuracy Counts, Printed Circuit Design & Manufacture, May 2003, P . 36. 7. Douglas Brooks, Signal Integrity Issues and Printed Circuit Board Design, Prentice Hall. 2003. P . 30, P . 206. 8. Douglas Brooks, Microstrip Propagation Time, Printed Circuit Design & Manufac. 28-29. ture, May 2004, PP 9. Stephen H. Hall, Garrett W. Hall and James A. McCall, High-Speed Digital System Design, A Handbook of Interconnect Theory and Design Practices, John W. Wiley and Sons, Inc. 2000, PP . 212-213. 10. Todd Westerhoff, Solution Space Analysis for High-Speed Design, Printed Circuit . 16-22. Design, August 2000, PP MAY 2005

PRINTED CIRCUIT DESIGN & MANUFACTURE

INTERCONNECT STRATEGIES

Loading Effects on Transmission Lines, Part 2

A minimum loaded line impedance may be essential to your design.

ABE RIAZI

Ed.: References for footnotes 1-10, equations 1-5, figures 1-3, and table 1 are found in Part 1 of this column, published in the May issue of PCD&M, available at www. pcdandm.com.

Co is the intrinsic capacitance of the trace and Cd is the distributed capacitance of the receivers, both per unit length. The normalized effective characteristic impedance12 and propagation delay are given by:
Zon = Zo / Zo = 1 / 1+Cr Tpdn = Tpd / Tpd = 1+ Cr EQUATION 13 EQUATION 14

A LOADED LINE may be defined as a

transmission line having a distribution of uniformly spaced capacitive loads4. The characteristic impedance and propagation delay formulas for loaded lines are shown in TABLE 2. A comparison of equations in Tables 1 and 2 reveals that the loaded or effective characteristics impedance (Zo) and propagation delay (Tpd) are related to the unloaded also called intrinsic or natural impedance (Zo) and propagation delay (Tpd)1, 11 by:
Zo = Zo / 1+ (Cd / Co) Tpd = Tpd x 1+ (Cd / Co) EQUATION 11 EQUATION 12

Where Cr = Cd/Co is a non-negative dimensionless number. Plots of Zon and Tpdn (also dimensionless) in terms of Cr are shown in FIGURE 4. 1+Cr (and its square root) is equal to or greater than unity (1 + Cr = 1 corresponds to the case of the unloaded line). Subsequently, EQUATIONS 13 and 14 (also Figure 4) reveal that impedance is decreased and propagation delay is increased (signal velocity is slowed down) due to loading effects. For instance, Cr = 3.0 results in the doubling of the transmission line propagation delay (i.e., Tpdn = 2.0), and halving the effective characteristic impedance (i.e., Zon = 0.5). One implication of loading con-

TABLE 2. The effective impedance and propagation delay for loaded

microstrip and symmetric stripline.

Parameter Formula Unit Effective Characteristic Zo = 87 / Er+1.41 x {ln[5.98H / (0.8W+T)]} / 1+(Cd/Co) Impedance (Microstrip) (Equation 6) Effective Propagation Delay (Microstrip) Effective Characteristic Impedance (Stripline) Effective Characteristic Impedance (Stripline) Effective Propagation Delay (Microstrip) Tpd = 1.017 0.475Er + 0.67 x 1+(Cd/Co) (Equation 7) Zo = (60 / Er) x {ln[4B / (0.67W(0.8+T / W))]} / 1+(Cd/Co) (Equation 8) Zo = (60 / Er) x {ln[(2B + T) / (0.8W+T)]} / 1+(Cd/Co) (Equation 9) Tpd = (1.017 Er) x 1+(Cd/Co) (Equation 10)

ns/ft

ns/ft

Er is a relative dielectric constant of the substrate material. W is trace width. H is height of microstrip relative to reference power/ground plane (i.e., dielectric substrate thickness). T is thickness of trace. B is separation of the two plane layers (for the symmetric stripline configuration). Cd is the distributed capacitance of receivers. Co is a traces intrinsic capacitance.

cepts is that in various high-speed PCB termination11 techniques such as series, parallel, Thevenin, etc., the loaded line characteristic impedance (Zo) should be utilized when computing the optimum values for terminators, not the unloaded (Zo). Loading effects can also impose the insertion of dummy vias13 on some nets of a high-speed bus, in order to equalize the loading and delay differences between various lines of the bus by forcing each line to have the same number of dummy and real vias. This can minimize layer-to-layer skew and thus maximize performance of the design. In some cases a minimum loaded line impedance is essential for maintaining signal quality, such as keeping the first signal plateau beyond receiver threshold. A formula for calculating the maximum load density that sustains the line impedance above the minimum pre-defined value is presented in IPC-D-31714. Such loading effect concepts hold valid for electrically short topologies. Examples 3 and 4 provide further insight regarding applications of loading effects. Example 3. A topology with several loads uniformly distributed (with negligibly short stub lengths to minimize noise) along a transmission line is shown in FIGURE 5. The transmission line includes four segments: T1, T2, T3 and T4, having length Y. Each receiver presents a load capacitance CL. The formulas discussed earlier can be applied to this network. Assuming each segment has unloaded characteristic impedance (Zo) and propagation delay (Tpd), then: Co = Tpd / Zo The distributed capacitance (Cd) is computed from the ratio of total receivers loading capacitance (4CL) to line length (4Y): Cd = 4CL/4Y = CL/Y The corresponding loaded line impedance and delay can then be cal(continued on page 35)
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INTERCONNECT STRATEGIES
ABE (ABBAS) RIAZI (ariazi@server works.com) is a senior signal integrity engineer with ServerWorks (a Broadcom Company) in Santa Clara, CA.

5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0

Tpdn

ACKNOWLEDGEMENTS
The author would like to thank Peter Arnold for reviewing this column, and Jeremy Plunkett and Dean Gonzales for their helpful discussions.

Zon 0 2 4 6 8 10 12 14 16 18 20 Cr

FIGURE 6. Loads clustered at the end of the line (a), and the equivalent circuit (b).

REFERENCES
nF/ft = 30 pF/ft = 2.5 pF/in. Let trace length = 5 inches with three receiver ICs to be distributed along the line, with zero stub lengths. Assume a loading of 4.0 pF per device, resulting in total loading of 12 pF, and a driver rise/fall time of 0.7 ns. Subsequently, Cd = 12pF/5 in = 2.4 pF/in. The calculated loaded values are: Zo = 42.86 Ohms and Tpd = 2.52 ns/ft. Furthermore, 2 x Tpd x trace length = 2 x 2.52 ns/ft x 0.417 ft = 2.1 ns. Since this exceeds the signals rise or fall times, there may be transmission line effects such as ringing and a need for termination. PCD&M
11. Karthik Ethirajan and John Nemec, Termination Techniques for High-speed Buses, EDN, Feb. 16, 1998, PP . 135-143. 12. Jose M. Soltero, Design High-Speed Backplanes That Work, Electronic Design (Components & Packaging Vision Supplement), Oct. 29, 2001, PP . 12-20. 13. Bryce Horine and Mike Leddige, Using Routing Techniques to Minimize Skew, Print. 24-27 . ed Circuit Design, December 1999, PP 14. Design Guidelines for Electronic Packaging Utilizing High-speed Techniques, IPCD-317, April 1990, PP . 24-26. 15. Sol Rosenstark, Transmission Lines in Computer Engineering, McGraw Hill, Inc., 1994, PP . 67-85. 16. Understanding and Minimizing Ground Bounce, Fairchild Application Note 640, February 1998.

FIGURE 4. Zon and Tpdn as a function of Cr, generated with Mathcad.

FIGURE 5. This topology includes four loads uniformly distributed along a transmission line (a), and its equivalent representation (b).

culated via EQUATIONS 11 and 12. To assert distributed (rather than lumped) effect, the capacitive loads need to be distributed uniformly, and the electrical delay between the neighboring loads should be less than the rise or fall times of the signal. Such loading effectively alters the transmission lines propagation velocity and characteristic impedance. No terminators are shown for this topology, although termination may be required depending on such factors as the signal rise/fall times, the line length, value of CL, and amount of ringing which can be tolerated on the bus. Loading types are frequently15, 16 classified as distributed (uniform along a length of line) or lumped (concentrated at a single point). A lumped variation of Figure 5 is depicted in FIGURE 6. All receivers are located at the far end of the line producing a large capacitive load. At fast edge rates, the distributed proves superior to the lumped modeling. A numerical specimen is furnished by the final example. Example 4. Consider a microstrip with unloaded Zo = 60_ and Tpd = 1.8 ns/ft. This indicates intrinsic trace capacitance of Co = Tpd/Zo = 0.030
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