Laboratory Manual For Embedded Systems

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 1
Laboratory Manual for

Embedded Systems

B. Tech.
TABLE OF CONTENTS

Sr. No. Title Page No.
1. Study of Environment of Keil icrovision 3. 03
2. Program Development process in icrovision . 21
3. Programming General Purpose Input Output Ports 25
4. Analog to Digital Converter and Programming 34
5. Digital to Analog Converter and Programming 41
6. Study of Different Sections of a Startup File 48
7. UART and its programming 62
8. Array Processing and Assembly Language Programming 68
9. (I ) Inline assembly instructions in C program. 80
(II ) ARM state & THUMB state Interworking 86
(III) Co-processor Instructions. 89
10. Software interrupts with their handlers. 94
11. Subroutines 101
12. IRQ Exception Handling and Vectored Interrupt Controller 105
13. Fast Interrupt Handling 109



LAB 1
Keil icrovision 3.
AIM:-To study the environment of Keil icrovision 3.
VISION3 OVERVIEW
The Vision3 IDE is a Windows-based software development platform that combines a robust editor,
project manager, and makes facility. Vision3 integrates all tools including the C compiler, macro
assembler, linker/locator, and HEX file generator. Vision3 helps expedite the development process of
your embedded applications by providing the following:
Full-featured source code editor,
Device database for configuring the development tool setting,
Project manager for creating and maintaining your projects,
Integrated make facility for assembling, compiling, and linking your embedded applications,
Dialogs for all development tool settings,
True integrated source-level Debugger with high-speed CPU and peripheral simulator,
Advanced GDI interface for software debugging in the target hardware and for connection to Keil
ULINK
Flash programming utility for downloading the application program into Flash ROM,
Links to development tools manuals, device datasheets & users guides.
The Vision3 IDE offers numerous features and advantages that help you quickly and successfully
develop embedded applications. They are easy to use and are guaranteed to help you achieve your
design goals.
The Vision3 IDE and Debugger is the central part of the Keil development toolchain. Vision3 offers a
Build Mode and a Debug Mode.
In the Vision3 Build Mode you maintain the project files and generate the application.
In the Vision3 Debug Mode you verify your program either with a powerful CPU and peripheral
simulator or with the Keil ULINK USB-JTAG Adapter (or other AGDI drivers) that connect the debugger
to the target system. The ULINK allows you also to download your application into Flash ROM of your
target system.
Menu Commands, Toolbars, and Shortcuts
The menu bar provides you with menus for editor operations, project maintenance, development tool
option settings, program debugging, external tool control, window selection and manipulation, and on-
line help.
The toolbar buttons allow you to rapidly execute Vision3 commands. A Status Bar provides editor
and debugger information. The various toolbars and the status bar can be enabled or disabled from the
View Menu commands.
The following sections list the Vision3 commands that can be reached by menu commands, toolbar
buttons, and keyboard shortcuts. The Vision3 commands are grouped mainly based on the
appearance in the menu bar:


File Menu and File Commands
Edit Menu and Editor Commands
Outlining Menu
Advanced Menu
Selecting Text Commands
View Menu
Project Menu and Project Commands
Debug Menu and Debug Commands
Flash Menu
Peripherals Menu
Tools Menu
SVCS Menu
Window Menu
Help Menu

Creating Applications
This part describes the Build Mode of Vision3 and is grouped into the following sections:
Create a Project: explains the steps required to setup a simple application and to generate HEX
output.
Project Target and File Groups: shows how to create application variants and organized the files
that belong to a project.
Tips and Tricks: provides information about the advanced features of the Vision3 Project
Manager.
1. Create Project File Folder and Specify Project Name
To create a new project file select from the Vision3 menu Project New Vision Project. This
opens a standard Windows dialog that asks you for the new project file name. You should you use a
separate folder for each project. You can simply use the icon Create New Folder in this dialog to get a
new empty folder.
Select this folder and enter the file name for the new project, i.e. Project1. Vision3 creates a new
project file with the name PROJECT1.UV2 which contains a default target and file group name. You can
see these names in the Project Workspace Files.
Copy and Add the CPU Startup Code
An embedded program requires CPU initialization code that needs to match the configuration of your
hardware design. This Startup Code depends also on the tool chain that you are using. Since you might
need to modify that file to match your target hardware, the file should be copied to your project folder.
For most devices, Vision3 asks you to copy the CPU specific Startup Code to your project. This is
required on almost all projects (exceptions are library projects and add-on projects). The Startup Code
performs configuration of the microcontroller device and initialization of the compiler run-time system.
Create New Source Files
You may create a new source file with the menu option File New. This opens an empty editor window
where you can enter your source code. Vision3 enables the C color syntax highlighting when you save
your file with the dialog File Save As under a filename with the extension *.C. We are saving our
example file under the name MAIN.C.

Add Source Files to Project
Once you have created your source file you can add this file to your project. Vision3 offers several
ways to add source files to a project. For example, you can select the file group in the Project
Workspace Files page and click with the right mouse key to open a local menu. The option Add
Files opens the standard files dialog. Select the file MAIN.C you have just created.
Set Tool Options for Target
Vision3 lets you set options for your target hardware. The dialog Options for Target opens via the
toolbar icon or via the Project - Options for Target menu item. In the Target tab you specify all
relevant parameters of your target hardware and the on-chip components of the device you have
selected. The following dialog shows the settings for our example.
Build Project
Typical, the tool settings under Options Target are all you need to start a new application. You may
translate all source files and link the application with a click on the Build Target toolbar icon. When you
build an application with syntax errors, Vision3 will display errors and warning messages in the Output
Window Build page. A double click on a message line opens the source file on the correct location in
a Vision3 editor window.
The next steps are:
Modify existing source code or add new source files to the project. The Build Target toolbar button
translates only modified or new source files and generates the executable file. Vision3 maintains a file
dependency list and knows all include files used within a source file. Even the tool options are saved in
the file dependency list, so that Vision3 rebuilds files only when needed. With the Rebuild Target
command, all source files are translated, regardless of modifications.
Test Programs with the Vision3 Debugger. The Vision3 Debugger offers two operating modes:
simulator that allows you to verify your application on your PC, or Target Debugging with an Evaluation
Board or your hardware platform
Program your application into Flash ROM. Vision3 integrates command-line driven Flash Utilities or
can use the ULINK USB-JTAG Adapter for Flash programming. You may need to create a HEX file to
use Flash programming utilities.
Create HEX File
Once you have successfully generated your application you can start debugging. After you have tested
your application, it is required to create an Intel HEX file to download the software into an EPROM
programmer or simulator. Vision3 creates HEX files with each build process when Create HEX file
under Options for Target Output is enabled. The FLASH Fill Byte, Start and End values direct the
OH166 utility to generate a sorted HEX files; sorted files are required for some Flash programming
utilities.
Test Programs with the Vision3 Debugger
This chapter describes the Debug Mode of Vision3 and shows you how to use the user interface to
test a sample program. Also discussed are simulation mode and the different options available for
program debugging.
You can use Vision3 Debugger to test the applications you develop. The Vision3 Debugger offers two
operating modes that are selected in the Options for Target Debug dialog.

Use Simulator configures the Vision3 Debugger as software-only product that simulates most features
of a microcontroller without actually having target hardware. You can test and debug your embedded
application before the hardware is ready. Vision3 simulates a wide variety of peripherals including the
serial port, external I/O, and timers. The peripheral set is selected when you select a CPU from the
device database for your target.
2. Debug Windows and Dialogs
During Debug Mode Vision3 offers additional Debug Windows and Dialogs that are summarized
below:
The Breakpoint Dialog allows you to define stop conditions for program execution.
The Code Coverage Window provides execution statistic information of execute and not
executed program parts.
The CPU Registers may be reviewed and modified in the Regs page of the Project Workspace
window.
The Disassembly Window allows program testing at the level of assembly instructions.
The Logic Analyzer provides a graphical display for value changes of peripheral registers and
variables.
The Memory Window may be used to review and modify memory content.
The Memory Map dialog specifies memory areas used by the application for program code and
data variables.
The Output Window - Command provides a command input/output window.
The Execution Profiler provides time and call statistics and is integrated into editor and
disassembly window.
The Performance Analyzer Window displays the execution time statistics.
The Serial Window displays the UART communication with the application program.
The Symbol Window shows debug symbol information of the application program.
The Toolbox provides configurable buttons for debug command and debug function execution.
The Watch Window lets you view and modify program variables and lists the current function call
nesting.

Flash Programming
Vision3 integrates Flash Programming Utilities in the project environment. All configurations are saved
in context with your current project.
You may use external command-line driven utilities (usually provided by the chip vendor) or the Keil
ULINK USB-JTAG Adapter. The Flash Programming Utilities are configured under Project - Options -
Utilities.
Flash Programming may be started from the Flash Menu or before starting the Vision3 Debugger
when you enable Project - Options - Utilities - Update Target before Debugging.


Fig. 1.1 Introduction to Keil Vision3

Fig. 1.2 Creating Project


Fig. 1.3 Selection of Target Device


Fig. 1.4 Selection of Target Device


Fig. 1.5 Selection Startup File

Fig. 1.6 Selection Startup File


Fig. 1.7 Creating main Program


Fig. 1.8 Adding Main file to Project


Fig. 1.9 Creating main Program

Fig. 1.10 Building Project

Fig. 1.11 Building Project

Fig1.12 Start debug session

Fig 1.13 Single step execution


Fig 1.14 Single step execution
ASSIGNMENT:
1. What is meaning of building process?
2. What are the contents of project workspace?
3. How to observe the present value of variables?
4. Discuss process of downloading hex code in to target device.


LAB 2
Program Development Process
AIM: - Write a first embedded program in C that adds and multiply two numbers.
PROGRAM DEVELOPMENT PROCESS

First, create a new project named first with extension .Uv2.We will select the device from NXP
(founded by Phillips) family. The board available with us is LPC 2368. So we will select every
time this hardware. After giving the name adds the startup code of LPC 2300.S to the project
file. After that the source codes save as text1.C. Add this file to the Source Group 1. Build the
project and Debug the project in simulator by selecting the option for target 1. You can see the
contents of user registers while running the program step by step.

SAMPLE PROGRAM: Addition and Multiplication
text1.C
# include<stdio.h>
int main ()
{
Int a, b, c;
a=2;
b=4;
c=a+b;
c=a*b;
return 0;
}


Screen Shots for Program Execution:

Fig. 2.1 main program and building

Fig. 2.2 Register Window and Program Execution

. 2.3 Register Window and Program Execution

ASSIGNMENT:
1. What is significance of disassembly window?
2. What is significance of memory window? How to open it and modify it?
3. What information is contained in project workspace?
4. How to set watch ? where it is useful?

LAB 3
GPIO
AIM: - Programming General Purpose Input Output Ports
SPECIAL FUNCTION REGISTERS FOR GPIO:
FIOXDIR
FIOXMASK
FIOXSET
FIOXCLR
FIOPIN

SPECIAL FUNCTION REGISTERS DESCRIPTION:


FEATURES OF DIGITAL GPIO PORTS:

- GPIO PORT0 and PORT1 are ports accessible via either the group of registers
providing enhanced features and accelerated port access or the legacy group of
registers. PORT2/3/4 are accessed as fast ports only.
- Accelerated GPIO functions:
GPIO registers are relocated to the ARM local bus so that the fastest possible I/O
timing can be achieved
Mask registers allow treating sets of port bits as a group, leaving other bits
unchanged
All GPIO registers are byte and half-word addressable
Entire port value can be written in one instruction
- Bit-level set and clear registers allow a single instruction set or clear of any number of
bits in one port
- Direction control of individual bits
- All I/O default to inputs after reset
- Backward compatibility with other earlier devices is maintained with legacy registers
appearing at the original addresses on the APB bus

SAMPLE PROGRAM: Program to generate LED flashing pattern on hardware board LPC 2368.
#include <LPC23xx.H>

void LED_Init(void) // Function that initializes LEDs
{
PINSEL10 = 0; // Disable ETM interface, enable LEDs
FIO2DIR = 0x000000FF; // P2.0..7 defined as Outputs
FIO2MASK = 0x00000000; // enable all pins for modification for port 2
}
void LED_on (unsigned int num) // Function that turns on requested LED
{
FIO2SET =(1 << num);
}
void LED_Off (unsigned int num) //Function that turns off requested LED
{
FIO2CLR = (1 << num);
}
void delay (void) // delay
{
for ( i=0; i<7099999; i++) { }
}
int main (void)

{
Int K=0;
LED_init (); // Initialize the port for output
delay ();
for ( k=0; k<8; k++)
{
LED_on (k); // make k th LED on
delay ();
LED_off (k); // make k th LED off
delay ();
}
}


SCREEN SHOTS FOR PROGRAM EXECUTION:

Fig 3.1 Sample program

Fig 3.2 GPIO Output window

Fig 3.3 Program Execution





Fig 3.6 Program Downloading

ASSIGNMENT:
1. Modify above program for displaying LED On-Off pattern
2. Modify above program for displaying LED scrolling pattern
3. What is significance of F prefix in all SFRs name?
4. Write above programs for port 1 and 3.


LAB 4
A/D CONVERTER
AIM: - A/D converter and programming
SPECIAL FUNCTION REGISTERS FOR A TO D CONVERTER:
AD0CR
AD0GDR
AD0STAT
ADDR0-7

FEATURES OF THE AVAILABLE A TO D CONVERTER ON LPC2368:
10 bit successive approximation analog to digital converter.
Input multiplexing among 6 pins (LPC2364/66/68) or 8 pins (LPC2378).
Power down mode.
Measurement range 0 to 3 V.
10 bit conversion time 2.44 s.
Burst conversion mode for single or multiple inputs.
Optional conversion on transition on input pin or Timer Match signal.
Individual result registers for each A/D channel to reduce interrupt overhead.

DESCRIPTION
Basic clocking for the A/D converters is provided by the APB clock (PCLK). A programmable divider is
included in each converter, to scale this clock to the 4.5 MHz (max) clock needed by the successive
approximation process. A fully accurate conversion requires 11 of these clocks.

Operation
- Hardware-triggered conversion
If the BURST bit in the ADCR is 0 and the START field contains 010-111, the A/D converter will
start a conversion when a transition occurs on a selected pin or Timer Match signal. The choices
include conversion on a specified edge of any of 4 Match signals, or conversion on a specified
edge of either of 2 Capture/Match pins. The pin state from the selected pad or the selected
Match signal, XORed with ADCR bit 27, is used in the edge detection logic.

- Interrupts
An interrupt is requested to the Vectored Interrupt Controller (VIC) when the ADINT bit in the
ADSTAT register is 1. The ADINT bit is one when any of the DONE bits of A/D channels that are
enabled for interrupts (via the ADINTEN register) are one. Software can use the Interrupt Enable
bit in the VIC that corresponds to the ADC to control whether this results in an interrupt. The
result register for an A/D channel that is generating an interrupt must be read in order to clear
the corresponding DONE flag.


SPECIAL FUNCTION REGISTER DESCRIPTION:



SAMPLE PROGRAM: Convert analog input given to channel 1 in to digital output
# Include < lpc23xx.h>
Int main ()
{
AD0CR=0X00200301; //pdn enabled, sel:00, clkdiv:03 clks:11clks/10bits
// start : none
AD0INTEN=0X00000100; //enable interrupt
AD0CR=0X01200301 // same as above but set start as :now
// to begin conversion
}


SCREEN SHOTS FOR PROGRAM EXECUTION :

Fig. 4.1 Sample Program

Fig. 4.2 A/D Out put Window


Fig. 4.3 Program Execution and Output Window

ASSIGNMENT:
1. What are the specifications of A/D converter?
2. What are the popular architectures of A/D conveter?
3. How speed of conversion can be compromised with resolution?
4. Modify above program to convert analog inputs of all channels and store result in array.


LAB 5
D/A Converter

AIM: - Digital to Analog converter and programming.
SPECIAL FUNCTION REGISTER OF DIGITAL TO ANALOG CONVERTER :
DACR
SPECIAL FUNCTION REGISTER DESCRIPTION: DACR

SAMPLE PROGRAM : (i)Generate triangle wave using D/A converter
#include<lpc23xx.h>
#include<stdio.h>
#include<math.h>
int main()
{
int i,n;
i=n=0;
PINSEL1=(1<<21); //for aout pin we select 21 pin
label: while(i<100) // for increasng cycle
{DACR=n<<6; // keeping the value of n &shifting by 6 places
i++;
n++;
}
while(i>0) //for decrasing cycle
{DACR=n<<6;

i--;
n--;
}
goto label; //for conti. cycle
}
}

SAMPLE PROGRAM : (i)Generate sine wave using D/A converter
#include<lpc23xx.h>
#include<stdio.h>
#include<math.h>
int main()
{
int i,j,n;
int arr[19]={100,109,117,126,134,142,150,157,164,170,176,181,186,190,194,197,198,199,200};
int arr1[19]={100,91,83,74,66,58,50,43,36,30,24,19,14,10,6,3,2,1,0};
i=0;
n=0;
PINSEL1=(1<<21);
label:
for(i=0;i<19;i++) //for cycle 0 to 90 degree
{n=arr[i];
DACR=n<<6; //keeping the value of n and shifting by
//6 places
}
for(j=18;j>=0;j--) //for cycle 90 to 180 degree
{n=arr[j];
DACR=n<<6;
}
for(i=0;i<19;i++) //for cycle 180 to 270 degree
{n=arr1[i];
DACR=n<<6;
}
for(j=18;j>=0;j--) //for cycle 270 to 360 degree
{n=arr1[j];

DACR=n<<6;
}

goto label;
}


SCREEN SHOT FOR PROGRAM EXECUTION :

Fig 5.1 Sample Program Execution

Fig 5.2 Logic Analyzer Window


Fig 5.3 Triangular Waveform on Logic Analyzer


Fig 5.3 Sinusoidal Waveform on Logic Analyzer

ASSIGNMENT:
1. What are the specifications of D/A converter?
2. What are the popular architectures of D/A converter?
3. Modify above program to generate sawtooth waveform.
4. What is logic Analyzer? How it is useful?
5. How amplitude of the waveform generated can be varied?


LAB 6
Startup File
AIM: - To study startup file for embedded project.
THEORY:
A startup code performs stack initialization and the microcontroller setup, before an arm
microcontroller can execute main program. The startup file LPC2300.s code is executed after CPU
reset.
The file LPC2300.s is an assembler module provided by keil. As its name implies, the startup code
is located to run from the reset vector. It provides the exception vector table as well as initialising the
stack pointer for the different operating modes. It also initialises some of the on-chip system
peripherals and the on-chip RAM before it jumps to the main function in c code. The startup code
will vary depending on which arm7 device you are using and which the compiler you are using, so
for your own project it is important to make sure you are using the correct file.
First of all the startup provides the exception Vector table as shown below. The vector table is
located. At 0x00000000 and provides a jump to interrupt service routines(ISR) on each vector to
ensure that the full Address range of the processor is available, the LDR(load Register)instruction is
used. The area command is used by the linker to the Place the vector table at the correct start
address. for a Single chip use this is always 0x00000000,however if you are using the external bus
and want to boot from external Memory, the vector table must be located at 0x80000000.

SECTIONS OF A STARTUP FILE:
1. Interrupt Vector Table
2. Clock Selection and PLL configuration
3. Peripheral configuration
4. Stack definition

LPC2300.S: Startup file for Philips LPC2300/LPC2400 device series :
Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs

Mode_USR EQU 0x10
Mode_FIQ EQU 0x11
Mode_IRQ EQU 0x12
Mode_SVC EQU 0x13
Mode_ABT EQU 0x17
Mode_UND EQU 0x1B
Mode_SYS EQU 0x1F

I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled

;// <h> Stack Configuration (Stack Sizes in Bytes)
;// <o0> Undefined Mode <0x0-0xFFFFFFFF:8>
;// <o1> Supervisor Mode <0x0-0xFFFFFFFF:8>
;// <o2> Abort Mode <0x0-0xFFFFFFFF:8>
;// <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8>
;// <o4> Interrupt Mode <0x0-0xFFFFFFFF:8>
;// <o5> User/System Mode <0x0-0xFFFFFFFF:8>
;// </h>

UND_Stack_Size EQU 0x00000000
SVC_Stack_Size EQU 0x00000008
ABT_Stack_Size EQU 0x00000000
FIQ_Stack_Size EQU 0x00000000
IRQ_Stack_Size EQU 0x00000100
USR_Stack_Size EQU 0x00000400

ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
FIQ_Stack_Size + IRQ_Stack_Size)

AREA STACK, NOINIT, READWRITE, ALIGN=3

Stack_Mem SPACE USR_Stack_Size
__initial_sp SPACE ISR_Stack_Size

Stack_Top

;// <h> Heap Configuration
;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF>
;// </h>

Heap_Size EQU 0x00000000

AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size

__heap_limit

System Control Block (SCB) Module Definitions
SCB_BASE EQU 0xE01FC000 ; SCB Base Address
PLLCON_OFS EQU 0x80 ; PLL Control Offset
PLLCFG_OFS EQU 0x84 ; PLL Configuration Offset
PLLSTAT_OFS EQU 0x88 ; PLL Status Offset
PLLFEED_OFS EQU 0x8C ; PLL Feed Offset
CCLKCFG_OFS EQU 0x104 ; CPU Clock Divider Reg Offset
USBCLKCFG_OFS EQU 0x108 ; USB Clock Divider Reg Offset
CLKSRCSEL_OFS EQU 0x10C ; Clock Source Select Reg Offset
SCS_OFS EQU 0x1A0 ; System Control and Status Reg Offset
PCLKSEL0_OFS EQU 0x1A8 ; Peripheral Clock Select Reg 0 Offset
PCLKSEL1_OFS EQU 0x1AC ; Peripheral Clock Select Reg 1 Offset

Constants
OSCRANGE EQU (1<<4) ; Oscillator Range Select
OSCEN EQU (1<<5) ; Main oscillator Enable
OSCSTAT EQU (1<<6) ; Main Oscillator Status
PLLCON_PLLE EQU (1<<0) ; PLL Enable
PLLCON_PLLC EQU (1<<1) ; PLL Connect
PLLSTAT_M EQU (0x7FFF<<0) ; PLL M Value
PLLSTAT_N EQU (0xFF<<16) ; PLL N Value
PLLSTAT_PLOCK EQU (1<<26) ; PLL Lock Status

Clock Setup
;// <h> System Controls and Status Register (SCS)
;// <o1.4> OSCRANGE: Main Oscillator Range Select
;// <0=> 1 MHz to 20 MHz
;// <1=> 15 MHz to 24 MHz
;// <e1.5> OSCEN: Main Oscillator Enable
;// </e>
;// </h>
;//
;// <h> Clock Source Select Register (CLKSRCSEL)
;// <o2.0..1> CLKSRC: PLL Clock Source Selection
;// <0=> Internal RC oscillator

;// <1=> Main oscillator
;// <1=> RTC oscillator
;// </h>
;//
;// <h> PLL Configuration Register (PLLCFG)
;// PLL_clk = (2* M * PLL_clk_src) / N
;// <o3.0..14> MSEL: PLL Multiplier Selection
;// <1-32768><#-1>
;// M Value
;// <o3.16..23> NSEL: PLL Divider Selection
;// <1-256><#-1>
;// N Value
;// </h>
;//
;// <h> CPU Clock Configuration Register (CCLKCFG)
;// <o4.0..7> CCLKSEL: Divide Value for CPU Clock from PLL
;// <1-256><#-1>
;// </h>
;//
;// <h> USB Clock Configuration Register (USBCLKCFG)
;// <o5.0..3> USBSEL: Divide Value for USB Clock from PLL
;// <1-16><#-1>
;// </h>
;//
;// <h> Peripheral Clock Selection Register 0 (PCLKSEL0)
;// <o6.0..1> PCLK_WDT: Peripheral Clock Selection for WDT
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 8
;// <o6.2..3> PCLK_TIMER0: Peripheral Clock Selection for TIMER0
;// <0=> Pclk = Cclk / 4
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 8
;// <0=> Pclk = Cclk / 4

;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 8
;// <o6.6..7> PCLK_UART0: Peripheral Clock Selection for UART0
;// <0=> Pclk = Cclk / 4
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 8
;// <0=> Pclk = Cclk / 4
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 8
;// <o6.10..11> PCLK_PWM0: Peripheral Clock Selection for PWM0
;// <0=> Pclk = Cclk / 4
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 8
;// <o6.12..13> PCLK_PWM1: Peripheral Clock Selection for PWM1
;// <0=> Pclk = Cclk / 4
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 8
;// <o6.14..15> PCLK_I2C0: Peripheral Clock Selection for I2C0
;// <0=> Pclk = Cclk / 4
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 8
;// <o6.16..17> PCLK_SPI: Peripheral Clock Selection for SPI
;// <0=> Pclk = Cclk / 4
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 8
;// <o6.18..19> PCLK_RTC: Peripheral Clock Selection for RTC
;// <0=> Pclk = Cclk / 4
;// <2=> Pclk = Cclk / 2

;// <3=> Pclk = Hclk / 8
;// <o6.20..21> PCLK_SSP1: Peripheral Clock Selection for SSP1
;// <0=> Pclk = Cclk / 4
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 8
;// <o6.22..23> PCLK_DAC: Peripheral Clock Selection for DAC
;// <0=> Pclk = Cclk / 4
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 8
;// <o6.24..25> PCLK_ADC: Peripheral Clock Selection for ADC
;// <0=> Pclk = Cclk / 4
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 8
;// <o6.26..27> PCLK_CAN1: Peripheral Clock Selection for CAN1
;// <0=> Pclk = Cclk / 4
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 6
;// <o6.28..29> PCLK_CAN2: Peripheral Clock Selection for CAN2
;// <0=> Pclk = Cclk / 4
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 6
;// <o6.30..31> PCLK_ACF: Peripheral Clock Selection for ACF
;// <0=> Pclk = Cclk / 4
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 6
;// </h>
;//
;// <h> Peripheral Clock Selection Register 1 (PCLKSEL1)
;// <o7.0..1> PCLK_BAT_RAM: Peripheral Clock Selection for the Battery Supported RAM
;// <0=> Pclk = Cclk / 4

;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 8
;// <o7.2..3> PCLK_GPIO: Peripheral Clock Selection for GPIOs
;// <0=> Pclk = Cclk / 4
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 8
;// <o7.4..5> PCLK_PCB: Peripheral Clock Selection for Pin Connect Block
;// <0=> Pclk = Cclk / 4
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 8
;// <0=> Pclk = Cclk / 4
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 8
;// <o7.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0
;// <0=> Pclk = Cclk / 4
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 8
;// <0=> Pclk = Cclk / 4
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 8
;// <0=> Pclk = Cclk / 4
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 8
;// <0=> Pclk = Cclk / 4
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 8

;// <0=> Pclk = Cclk / 4
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 8
;// <0=> Pclk = Cclk / 4
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 8
;// <o7.22..23> PCLK_I2S: Peripheral Clock Selection for I2S
;// <0=> Pclk = Cclk / 4
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 8
;// <o7.24..25> PCLK_MCI: Peripheral Clock Selection for MCI
;// <0=> Pclk = Cclk / 4
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 8
;// <o7.28..29> PCLK_SYSCON: Peripheral Clock Selection for System Control Block
;// <0=> Pclk = Cclk / 4
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 8
;// </h>
;// </e>
CLOCK_SETUP EQU 1
SCS_Val EQU 0x00000020
CLKSRCSEL_Val EQU 0x00000001
PLLCFG_Val EQU 0x0000000B
CCLKCFG_Val EQU 0x00000004
USBCLKCFG_Val EQU 0x00000005
PCLKSEL0_Val EQU 0x00000000
PCLKSEL1_Val EQU 0x00000000


Memory Accelerator Module (MAM) definitions
MAM_BASE EQU 0xE01FC000 ; MAM Base Address
MAMCR_OFS EQU 0x00 ; MAM Control Offset
MAMTIM_OFS EQU 0x04 ; MAM Timing Offset

;// <e> MAM Setup
;// <o1.0..1> MAM Control
;// <0=> Disabled
;// <1=> Partially Enabled
;// <2=> Fully Enabled
;// Mode
;// <o2.0..2> MAM Timing
;// <0=> Reserved <1=> 1 <2=> 2 <3=> 3
;// <4=> 4 <5=> 5 <6=> 6 <7=> 7
;// Fetch Cycles
;// </e>
MAM_SETUP EQU 1
MAMCR_Val EQU 0x00000002
MAMTIM_Val EQU 0x00000004

Area Definition and Entry Point
; Startup Code must be linked first at Address at which it expects to run.

AREA RESET, CODE, READONLY
ARM

; Exception Vectors
; Mapped to Address 0.
; Absolute addressing mode must be used.
; Dummy Handlers are implemented as infinite loops which can be modified.

Vectors LDR PC, Reset_Addr
LDR PC, Undef_Addr
LDR PC, SWI_Addr
LDR PC, PAbt_Addr

LDR PC, DAbt_Addr
NOP ; Reserved Vector
; LDR PC, IRQ_Addr
LDR PC, [PC, #-0x0120] ; Vector from VicVectAddr
LDR PC, FIQ_Addr

Reset_Addr DCD Reset_Handler
Undef_Addr DCD Undef_Handler
SWI_Addr DCD SWI_Handler
PAbt_Addr DCD PAbt_Handler
DAbt_Addr DCD DAbt_Handler
DCD 0 ; Reserved Address
IRQ_Addr DCD IRQ_Handler
FIQ_Addr DCD FIQ_Handler

Undef_Handler B Undef_Handler
SWI_Handler B SWI_Handler
PAbt_Handler B PAbt_Handler
DAbt_Handler B DAbt_Handler
IRQ_Handler B IRQ_Handler
FIQ_Handler B FIQ_Handler

; Reset Handler

EXPORT Reset_Handler
Reset_Handler

; Setup Clock
IF CLOCK_SETUP != 0
LDR R0, =SCB_BASE
MOV R1, #0xAA
MOV R2, #0x55

; Configure and Enable PLL
LDR R3, =SCS_Val ; Enable main oscillator

STR R3, [R0, #SCS_OFS]

IF (SCS_Val:AND:OSCEN) != 0
OSC_Loop LDR R3, [R0, #SCS_OFS] ; Wait for main osc stabilize
ANDS R3, R3, #OSCSTAT
BEQ OSC_Loop
ENDIF

LDR R3, =CLKSRCSEL_Val ; Select PLL source clock
STR R3, [R0, #CLKSRCSEL_OFS]
LDR R3, =PLLCFG_Val
STR R3, [R0, #PLLCFG_OFS]
STR R1, [R0, #PLLFEED_OFS]
MOV R3, #PLLCON_PLLE
STR R3, [R0, #PLLCON_OFS]
; Wait until PLL Locked
PLL_Loop LDR R3, [R0, #PLLSTAT_OFS]
ANDS R3, R3, #PLLSTAT_PLOCK
BEQ PLL_Loop

M_N_Lock LDR R3, [R0, #PLLSTAT_OFS]
LDR R4, =(PLLSTAT_M:OR:PLLSTAT_N)
AND R3, R3, R4
LDR R4, =PLLCFG_Val
EORS R3, R3, R4
BNE M_N_Lock
; Setup CPU clock divider
MOV R3, #CCLKCFG_Val
STR R3, [R0, #CCLKCFG_OFS]

; Setup USB clock divider
LDR R3, =USBCLKCFG_Val
STR R3, [R0, #USBCLKCFG_OFS]


; Setup Peripheral Clock
LDR R3, =PCLKSEL0_Val
STR R3, [R0, #PCLKSEL0_OFS]
LDR R3, =PCLKSEL1_Val
STR R3, [R0, #PCLKSEL1_OFS]
; Switch to PLL Clock
MOV R3, #(PLLCON_PLLE:OR:PLLCON_PLLC)
STR R3, [R0, #PLLCON_OFS]
ENDIF ; CLOCK_SETUP
; Setup MAM
IF MAM_SETUP != 0
LDR R0, =MAM_BASE
MOV R1, #MAMTIM_Val
STR R1, [R0, #MAMTIM_OFS]
MOV R1, #MAMCR_Val
STR R1, [R0, #MAMCR_OFS]
ENDIF ; MAM_SETUP

Memory Mapping (when Interrupt Vectors are in RAM)
MEMMAP EQU 0xE01FC040 ; Memory Mapping Control
IF :DEF:REMAP
LDR R0, =MEMMAP
IF :DEF:RAM_MODE
MOV R1, #2
ELSE
MOV R1, #1
ENDIF
STR R1, [R0]
ENDIF

; Initialise Interrupt System
; ...

; Setup Stack for each mode


LDR R0, =Stack_Top

; Enter Undefined Instruction Mode and set its Stack Pointer
MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #UND_Stack_Size

; Enter Abort Mode and set its Stack Pointer
MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #ABT_Stack_Size

; Enter FIQ Mode and set its Stack Pointer
MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #FIQ_Stack_Size

; Enter IRQ Mode and set its Stack Pointer
MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #IRQ_Stack_Size

; Enter Supervisor Mode and set its Stack Pointer
MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #SVC_Stack_Size

; Enter User Mode and set its Stack Pointer
MSR CPSR_c, #Mode_USR
IF :DEF:__MICROLIB

EXPORT __initial_sp
ELSE
MOV SP, R0
SUB SL, SP, #USR_Stack_Size

ENDIF

; Enter the C code
IMPORT __main
LDR R0, =__main
BX R0 // Branch to main program

IF :DEF:__MICROLIB
EXPORT __heap_base
EXPORT __heap_limit

ELSE
; User Initial Stack & Heap
AREA |.text|, CODE, READONLY

IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap

LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + USR_Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDIF
END
ASSIGNMENT:
1. Where Startup file is located? How to load startup file in project?
2. What are the sections of Startup file? Discuss them in Detail.
3. Where Interrupt vector table is located?
4. How Program execution is switched to main program?


LAB 7
UART
AIM: - Write a program that shows the use of serial device.
The UART is a Universal Asynchronous Receiver Transmitter device. It is used for serial communication.
In serial communication baud rate is important factor determines number of bits transmitted per second.

SPECIAL FUNCTION REGISTERS:

UARTn Transmit Holding Register
UARTn Divisor Latch LSB Register
UARTn Line Control Register
UARTn Line Status Register
UARTn Fractional Divider Register

SPECIAL FUNCTION REGISTERS DESCRIPTION:

UARTn Transmit Holding Register (U0THR - 0xE000 C000, U2THR - 0xE007 8000, U3THR - 0xE007
C000 when DLAB = 0, Write Only).
The UnTHR is the top byte of the UARTn TX FIFO. The top byte is the newest character in the TX FIFO
and can be written via the bus interface. The LSB represents the first bit to transmit.
The Divisor Latch Access Bit (DLAB) in UnLCR must be zero in order to access the UnTHR. The UnTHR
is always Write Only.
UART0 Transmit Holding Register (U0THR - address 0xE000 C000, U2THR - 0xE007 8000, U3THR -
0xE007 C000 when DLAB = 0, Write Only) bit description

UARTn Divisor Latch LSB Register (U0DLL - 0xE000 C000, U2DLL - 0xE007 8000, U3DLL - 0xE007
C000 when DLAB = 1) and UARTn Divisor Latch MSB Register (U0DLM - 0xE000 C004, U2DLL -
0xE007 8004, U3DLL - 0xE007 C004 when DLAB = 1).

The UARTn Divisor Latch is part of the UARTn Baud Rate Generator and holds the value used to divide
the APB clock (PCLK) in order to produce the baud rate clock, which must be 16 the desired baud
rate. The UnDLL and UnDLM registers together form a 16 bit divisor where UnDLL contains the lower 8
bits of the divisor and UnDLM contains the higher 8 bits of the divisor. A 0x0000 value is treated like a
0x0001 value as division by zero is not allowed. The Divisor Latch Access Bit (DLAB) in UnLCR must
be one in order to access the UARTn Divisor Latches.
UARTn Divisor Latch LSB Register (U0DLL - address 0xE000 C000,U2DLL - 0xE007 8000, U3DLL -
0xE007 C000 when DLAB = 1) bit description

Bit Symbol Description

7:0 DLLSB Used to determine baud rate of UARTn.
UARTn Divisor Latch MSB Register (U0DLM - address 0xE000 C004,

U2DLM - 0xE007 8004, U3DLM - 0xE007 C004 when DLAB = 1) bit
description
Bit Symbol Description Reset Value
7:0 DLMSB Used to determined baud rate of UARTn.
.

UARTn Line Control Register (U0LCR - 0xE000 C00C, U2LCR -0xE007 800C, U3LCR - 0xE007
C00C)
The UnLCR determines the format of the data character that is to be transmitted or received.

UARTn Line Control Register (U0LCR - address 0xE000 C00C, U2LCR - 0xE007 00C,
U3LCR - 0xE007 C00C) bit description

Bit Symbol Value Description Reset

1:0 Word Lengths
Select

00 5 bit character length 0

01 6 bit character length

10 7 bit character lengths

11 8 bit character lengths

2 Stop Bit Select 0 1 stop bit. 0

1 2 stop bits (1.5 if UnLCR[1:0]=00).

3 Parity Enable 0 Disable parity generation and checking. 0

1 Enable parity generation and checking. Enable parity generation and checking.

5:4 Parity Select 00 Odd parity. Number of 1s in the transmitted character and 0
the attached parity bit will be odd.
01 Even Parity. Number of 1s in the transmitted character and
the attached parity bit will be even.

10 Forced "1" stick parity.

11 Forced "0" stick parity.
Break Control 0 Disable trans. 0
1 Enable break transmission. Output pin UART0 TXD is
forced to logic 0 when UnLCR[6] is active high.

7 Divisor Latch
Access Bit
(DLAB)

0 Disable access to Divisor Latches. 0

1 Enable access to Divisor Latches.

UARTn Line Status Register (U0LSR - 0xE000 C014, U2LSR -
0xE007 8014, U3LSR - 0xE007 C014, Read Only)

The UnLSR is a read-only register that provides status information on the UARTn
TX and RX blocks.

Value

0 Receiver 0
Data Ready
(RDR)
0

UnLSR0 is set when the UnRBR holds an unread character 0
and is cleared when the UARTn RBR FIFO is empty.
UnRBR is empty.

1 Overrun
Error
(OE)

1 UnRBR contains valid data.
1 UnRBR contains valid data.

The overrun error condition is set as soon as it occurs. An
UnLSR read clears UnLSR1. UnLSR1 is set when UARTn
RSR has a new character assembled and the UARTn RBR
FIFO is full. In this case, the UARTn RBR FIFO will not be
overwritten and the character in the UARTn RSR will be lo

UARTn Line Status Register (U0LSR - address 0xE000 C014,
U2LSR - 0xE007 8014, U3LSR - 0xE007 C014, Read Only) bit description
Value

2 Parity Error
(PE)

3 Framing Error
(FE)

When the parity bit of a received character is in the wrong 0
state, a parity error occurs. An UnLSR read clears UnLSR[2].
Time of parity error detection is dependent on UnFCR[0].
Note: A parity error is associated with the character at the top
of the UARTn RBR FIFO.

0 Parity error status is inactive.

1 Parity error status is active.

When the stop bit of a received character is a logic 0, a 0
framing error occurs. An UnLSR read clears UnLSR[3]. The
time of the framing error detection is dependent on UnFCR0.
Upon detection of a framing error, the Rx will attempt to
resynchronize to the data and assume that the bad stop bit is
actually an early start bit. However, it cannot be assumed that
the next received byte will be correct even if there is no
Framing Error.
Note: A framing error is associated with the character at the
top of the UARTn RBR FIFO.

0 Framing error status is inactive.

4 Break
Interrupt
(BI)

1 Framing error status is active.

When RXDn is held in the spacing state (all 0s) for one full 0
character transmission (start, data, parity, stop), a break
interrupt occurs. Once the break condition has been detected,
the receiver goes idle until RXDn goes to marking state (all
1s). An UnLSR read clears this status bit. The time of break
detection is dependent on UnFCR[0].
Note: The break interrupt is associated with the character at
the top of the UARTn RBR FIFO.

0 Break interrupt status is inactive.

5 Transmitter
Holding
Register
Empty
(THRE))

6 Transmitter
Empty
(TEMT)

1 Break interrupt status is active.

THRE is set immediately upon detection of an empty UARTn 1
THR and is cleared on a UnTHR write.

0 UnTHR contains valid data.

1 UnTHR is empty.

TEMT is set when both UnTHR and UnTSR are empty; TEMT 1
is cleared when either the UnTSR or the UnTHR contain valid
data.

0 UnTHR and/or the UnTSR contains valid data.

7 Error in RX
FIFO
(RXFE)

1 UnTHR and the UnTSR are empty.

UnLSR[7] is set when a character with a Rx error such as 0
framing error, parity error or break interrupt, is loaded into the
UnRBR. This bit is cleared when the UnLSR register is read
and there are no subsequent errors in the UARTn FIFO.
UnRBR contains no UARTn RX errors or UnFCR[0]=0.

1 UARTn RBR contains at least one UARTn RX error

UARTn Fractional Divider Register (U0FDR - 0xE000 C028, U2FDR -
0xE007 8028, U3FDR - 0xE007 C028)
The UARTn Fractional Divider Register (UnFDR) controls the clock pre-scaler for the baud
rate generation and can be read and written at users discretion.

UARTn Fractional Divider Register (U0FDR - address 0xE000 C028, U2FDR -
0xE007 8028, U3FDR - 0xE007 C028) bit description
Bit Function Value Description Reset value

3:0 DIVADDVAL 0 Baud-rate generation pre-scaler divisor value. If this field is 0
0, fractional baud-rate generator will not impact the
UARTn baudrate.

7:4 MULVAL 1 Baud-rate pre-scaler multiplier value. This field must be 1
greater or equal 1 for UARTn to operate properly,
regardless of whether the fractional baud-rate
generator is used or not.

31:8 - Reserved, user software should not write ones to reserved 0
bits. The value read from a reserved bit is not defined.

SAMPLE PROGRAM:
#include <stdio.h>
#include <LPC23xx.h>
int main (void) // Initialize Serial Interface
{
int i;
char st[11] = hello there; //message to be displayed
PINSELO | = 0x00000050; //Enable TxD0 and RxD0
U0FDR = 0; // Fractional divider not used
U0LCR = 0x83; // 8-bits, no parity, 1 stop bit
U0DLL = 78; //9600 baud rate at 12.0 MHz PCLK
U0DLM = 0; // High divisor Latch =0;
U0LCR = 0x03; //DLAB=0;
for(i=0; i<12; i++)
{
While (! (U0LSR & 0x20));
U0THR = st[i];
}
}

SCREEN SHOTS OF PROGRAM EXECUTION:

Fig.7.1 Program for serial interface

Fig.7.2 Display UART Output Window
ASSINGMENT:
1. Write a program that shows receive the data serially using UART.
2. Determine the value of respective SFR registers for various possible value of baud rate.
3. Use sample program to display output of A/D converter on UART output window

LAB 8
Array Processing
AIM: To study an ARM assembly language program to sort five numbers in ascending and
descending order.
THEORY:
Procedure to write an ARM assembly program:

In built ARM starter file (lpc2300.s) is written for high language applications, i.e. C. To write the
low language program (assembly program), it is required to make certain modifications in
startup file. Steps are mentioned below to write ARM assembly language program / application.
1. In startup file, replace actual code from line number 488 till end as shown below.

IMPORT start
LDR R0, =start
BX R0
END

Here, start is a block of area in which assembly program / application code exists.

2. An assembly program / application code will start with AREA directive, which instructs the
assembler to assemble a new code or data section. Sections are independent, named,
indivisible chunks of code or data that are manipulated by the linker.
- Here, ykm is name of block where program code resides, instead of ykm, any name
can be given.
- CODE means its program code.
- READONLY means given area code is read-only.
- start is starting point of program.
- end is ending point of program.

SAMPLE PROGRAM:

AREA ykm, CODE, READONLY ; ** One tab should be given to differentiate
between AREA directive and lable
EXPORT start ; ** One tab should be given to differentiate
between EXPORT directive and lable
start mov r7,#0x00

order mov r0,#0x40000000
mov r5,#0x00

loop add r5,#0x1
ldr r1,[r0]
add r0,#0x4
ldr r2,[r0]
cmp r5,#0x09
bge over
cmp r1,r2
blt loop
str r1,[r0],#-4
str r2m[r0],#4
cmp r5,#0x08
blt loop
over add r7,#0x1
cmp r7,#0x08
blt order
end

SCREEN SHOT FOR PROGRAM EXECUTION:
Fig. 8.1 Sample Program

Fig. 8.2 Debug Session step1

Fig. 8.3 Debug Session -
Fig. 8.4 Debug Session - Step3

Fig. 8.5 Debug Session Step4

Fig. 8.6 Debug Session main Program




Fig. 8.9 Debug Session - Step 8
0

Fig. 8.10 Debug Session - Result in Memory Window

ASSIGNMENT:
1. Explain steps required to write ARM assembly language program.
2. Write ascending order program to sort 10 numbers.
3. Write descending order program to sort 10 numbers.

LAB 9
Inline Assembly, Thumb State, and Co-processor
AIM: (i) To study an ARM higher language (C) program that allows inline assembly
instructions in C program.
THEORY:
Inline assembly is a special provision in the ARM processors which allows user to write ARM
assembly language program in higher language (C) program. Basic advantage of such
provision is to get high code density. This provision is mostly used where code storage capacity
of processor is less compared to the requirement.
Restrictions on inline assembly operations:
There are a number of restrictions on the operations that can be performed in inline assembly
code. These restrictions provide a measure of safety, and ensure that the assumptions in
compiled C and C++ code are not violated in the assembled assembly code.

Miscellaneous restrictions
The inline assembler has the following restrictions:
- The inline assembler is a high-level assembler, and the code it generates might not
always be exactly what you write. Do not use it to generate more efficient code than the
compiler generates. Use embedded assembler or the ARM assembler armasm for this
purpose.
- Some low-level features that are available in the ARM assembler armasm, such as
branching and writing to PC, are not supported.
- Label expressions are not supported.
- You cannot get the address of the current instruction using dot notation (.) or {PC}.
- The & operator cannot be used to denote hexadecimal constants. Use the 0x prefix
instead. For example:__asm { AND x, y, 0xF00 }
- The notation to specify the actual rotate of an 8-bit constant is not available in inline
assembly language. This means that where an 8-bit shifted constant is used, the C flag
must be regarded as corrupted if the NZCV flags are updated.
- You must not modify the stack. This is not necessary because the compiler automatically
stacks and restores any working registers as required. The compiler does not permit you
to explicitly stack and restore work registers.

Registers
Registers, such as r0-r3, sp, lr, and the NZCV flags in the CPSR must be used with caution. If
you use C or C++ expressions, these might be used as temporary registers and NZCV flags
might be corrupted by the compiler when evaluating the expression.

The pc, lr, and sp registers cannot be explicitly read or modified using inline assembly code
because there is no direct access to any physical registers. However, you can use the following
intrinsics to access these registers:
- current_pc in the Compiler Reference Guide
- current_sp in the Compiler Reference Guide
- return_address in the Compiler Reference Guide.

Thumb instruction set
The inline assembler is not available when compiling C or C++ for Thumb state, and the inline
assembler does not assemble Thumb instructions. Instead, the compiler switches to ARM state
automatically.
If you want to include inline assembly in code to be compiled for Thumb, enclose the functions
containing inline assembler code between #pragma arm and #pragma thumb statements. For
example:
#pragma arm
int add(int i, int j)
{
int res;
__asm
{
ADD res, i, j // add here
}
return res;
}
#pragma thumb
You must also compile your code using the --apcs /interwork compiler option.

VFP coprocessor
The inline assembler does not provide direct support for VFP instructions. However, you can
specify them using the generic coprocessor instructions.
Inline assembly code must not be used to change VFP vector mode. Inline assembly can
contain floating-point expression operands that can be evaluated using compiler-generated VFP
code. Therefore, it is important that only the compiler modifies the state of the VFP.

Unsupported instructions
The following instructions are not supported in the inline assembler:
- BKPT , BX , BXJ, and BLX instructions
- SVC instruction
- LDR Rn, =expression pseudo-instruction. Use MOV Rn, expression instead (this can
generate a load from a literal pool)
- LDRT, LDRBT, STRT, and STRBT instructions
- MUL, MLA, UMULL, UMLAL, SMULL, and SMLAL flag setting instructions
- MOV or MVN flag-setting instructions where the second operand is a constant
- user-mode LDM instructions
- ADR and ADRL pseudo-instructions.


Program Format:
//*******************************************//
Include header files
//*******************************************//

int main()
{
//*******************************************//
Higher language (C) program
//*******************************************//
__asm
{
//*******************************************//
ARM Assembly language program
//*******************************************//
}
//*******************************************//
Higher language (C) program
//*******************************************//
}

SAMPLE PROGRAM:
This sample program illustrates how to write ARM assembly program into higher level language
program.

#include <stdio.h>

int main()
{
int a=2; b=4;c=0;
c=a*b;
__asm
{
mov a,#01;
mov b,#02;
mov c, #03;
add a, b, c;
}
}
Fig. 9(a).1 Sample Program

Fig. 9(a).2 Debug Session - Step1

Fig. 9(a).3 Debug Session - Step2

AIM: (ii) To study an ARM assembly language program having ARM state & thumb state.
The Thumb instruction set addresses the issue of code density. It may be viewed as a
compressed form of a subset of the ARM instruction set. Thumb instructions map onto ARM
instructions, and the Thumb programmer's model maps onto the ARM programmer's model.
Implementations of Thumb use dynamic decompression in an ARM instruction pipeline and then
instructions execute as standard ARM instructions within the processor.

Thumb is not a complete architecture; it is not anticipated that a processor would execute
Thumb instructions without also supporting the ARM instruction set. Therefore the Thumb
instruction set need only support common application functions, allowing recourse to the full
ARM instruction set where necessary (for instance, all exceptions automatically enter ARM
mode).

Thumb is fully supported by ARM development tools, and an application can mix ARM and
Thumb subroutines flexibly to optimize performance or code density on a routine-by-routine
basis.

SAMPLE PROGRAM:

AREA ykm, CODE, READONLY ; ** One tab should be given to differentiate
between AREA directive and lable
EXPORT square ; ** One tab should be given to differentiate
between EXPORT directive and lable
square
mov r1,#&44
movs r2,#44
adcs r3,r2,r1,asr#5
subs r7,r2,r1,lsl#4
ldr r5,=fun
movs lr,pc
bx r5
add r1,#1
add r1,#1
add r1,#1

b function

THUMB
fun
ldr r6,=0x40000000
movs r7,r6
ldr r0,=65534
ldr r1,=280
movs r2,#54
movs r3,#0
stmia r6!,{r0-r3}
movs r2,#0
loop
ldr r3,[r7]
adds R2,R3
adds r7,#4
cmp r6,r7
bgt loop
bx lr
ARM
function
add r5,r0,r1
end

Fig. 9(b).1 Sample Program


Fig. 9(b). 2 Debug Session - Step1



AIM: (iii) To study an ARM assembly language program for co-processor instructions.
The ARM architecture supports a general mechanism for extending the instruction set through
the addition of coprocessors. The most common use of a coprocessor is the system
coprocessor used to control on-chip functions such as the cache and memory management unit
on the ARM720. A floating-point ARM coprocessor has also been developed, and application-
specific coprocessors are a possibility.

Sample Program:

AREA cop, CODE, READONLY
EXPORT coprocessor

coprocessor
MOV r0, #06 ; Set up parameters
mov r1,#2
add r2,r0,r1
mcr p1,0,r0,c1,c2
mcr p1,0,r0,c1,c2
mcr p1,0,r0,c1,c2
mrc p1,0,r2,c1,c2
cdp p1,4,c1,c2,c3

END

Fig. 9(c). 1 Sample Program

Fig. 9(c). 2 Debug Session - Step1



Note: Here program enters into undefined mode because in the given ARM7 simulator
co-processor debugging option is not given.

ASSIGNMENT:
1. Explain different restrictions of inline programming?
2. Explain significance of inline programming?
3. Explain different unsupported instructions of inline programming with suitable example?
4. Briefly explain differences between ARM mode & Thumb mode?
5. Explain significance of THUMB mode?
6. Explain procedure to switch over between ARM & THUMB mode?
7. Write an example application which uses co-processor?
8. Explain coprocessor data transfer instructions with example?
9. Explain binary encoding of coprocessor register transfer instruction?

LAB 10
Software Interrupts
AIM: - Write a program that shows software interrupts with their handlers.
THEORY:
In ARM7TDMI, vector table is available in ROM which consists of vector address of desired
exception.
To write the assembly program we have to make some changes as shown below in startup file.
-in C program block at line no.500 instead of import _main we have to write the name which is
given to our assembly block in our program.
; Enter the C code
IMPORT start
LDR R0, =start
BX R0
END
The program will start with AREA directive, which instructs the assembler to assemble a new
code or data section. Sections are independent, named, indivisible chunks of code or data that
are manipulated by the linker.
SAMPLE PROGAM:
AREA prog, CODE, READONLY;
EXPORT start;
EXPORT SWI_0;
EXPORT SWI_1;
ENTRY

SWI_0; // int 0 subroutine starts here
mov r3, #19;
mov r2, #19;
mov pc, r14; // return from supervisor mode to user mode
SWI_1; // int 1 subroutine starts here
mov r3, #18;
mov r2, #18;
mov pc, r14; // return from supervisor mode to user mode
start; // main program starts from here
mov r0, #10;
mov r1, #12;
SWI # 0x0; //make interrupt 0 to occur by software
mov r3, #19;
SWI # 0x1; //make interrupt 1 to occur by software
mov r4, #19;
end



Fig. 10.1 Program shows generation of software interrupt with handlers.
Fig. 10.2 Assembling and Linking of program


Fig 10.3 Import SWI 0x0 and SWI 0x1

Fig.10.4 Debugging of program

Fig. 10.5 Debugging of program
ASSINGMENT:
1. Generate the software interrupt int 5 and int 6 and export their handlers from start up file.
2. Generate the software interrupt int 7 and int 8 and export their handlers from start up file.
3. How many SWI s are possible for ARM7 core
4. Explain in detail program execution flow in case of SWI instruction
5. Explain bit wise format of SWI instruction

LAB 11
Subroutines
AIM: - Write a program that shows use of subroutine.
THEORY :
The use of subroutine is to define function which required to call number of times. The
subroutine may be defined within the file or in separate assembly file.
To write the assembly program we have to make some changes as shown below in startup file.
-in C program block at line no.500 instead of import _main we have to write the name which is
given to our assembly block in our program.
; Enter the C code
IMPORT start
LDR R0, =start
BX R0
END
The program will start with AREA directive, which instructs the assembler to assemble a new
code or data section. Sections are independent, named, indivisible chunks of code or data that
are manipulated by the linker.
SAMPLE PROGRAM:
AREA subrout, CODE, READONLY
EXPORT start
IMPORT domul
doadd ADD r4, r0, r1
BX lr; // return from add
domul MUL r5, r2, r1;
BX lr; // return from mul

Start : mov r0, #10
mov r1, #3
bl doadd ; // call for add
mov r2, r4;
bl domul; // call for mul
mov r3, r5;
wait
B wait;
end
SCREEN SHOTS OF PROGRAM EXECUTION:
Fig.11.1 Subroutine for multiplication


Fig.11.2 Main program
Fig. 11.3 Debugging of Program
ASSINGMENT:
1. Define subroutine to find maximum number among ten numbers in separate file and call from
main program.
2. Define subroutine to arrange data in ascending order from ten numbers in separate file and
call from main program.
3. In which mode subroutines are executed?

LAB 12
IRQ Exception Handling and VIC

AIM: - To understand IRQ exception Handling mechanism and ISRs.
SPECIAL FUNCTION REGISTERS OF VECTORED INTERRUPT CONTROLLER :
VICIRQStatus VICFIQStatus VICRawintr
VICIntSelect VICIntEnable VICIntEnClr
VICSoftInt VICSoftIntClr

Special Function Register Description:


THEORY :
The ARM processor core has two interrupt inputs called Interrupt Request (IRQ) and Fast
Interrupt request (FIQ). The Vectored Interrupt Controller (VIC) takes 32 interrupt request inputs
and program assigns them as FIQ or vectored IRQ types. The programmable assignment
scheme means that priorities of interrupts from the various peripherals can be dynamically
assigned and adjusted. Vectored IRQs, which include all interrupt requests that are not
classified as FIQs, have a programmable interrupt priority. When more than one interrupt is
assigned the same priority and occur simultaneously, the one connected to the lowest
numbered VIC channel will be serviced first.
The VIC ORs the requests from all of the vectored IRQs to produce the IRQ signal to the ARM
processor. The IRQ service routine can start by reading a register from the VIC and jumping to
the address supplied by that register. IRQ is the Interrupt mode for general purpose interrupt
handling. The program and run mode is shown in following snaps.
SAMPLE PROGRAM : Program that show use of IRQ Interrupt Handling.
#include <lpc23xx.h>
#include <stdio.h>
__irq void IRQ_Handler (void) // IRQ handler definition
{ EXTINT = 01;
}
int main(void)
{ EXTMODE=0x00000001; //Interrupt configuration, edge triggered
EXTPOLAR=0x00000001; // positive going interrupt
VICIntEnable=0x00004000; // Enable interrupt
VICIntSelect=0x00000000; // set interrupt as IRQ
VICVectAddr14 = (unsigned long)IRQ_Handler;
VICVectAddr14 =15; // vector address of EXT0 interrupt
VICIntEnable=(1<<4);
VICSoftInt=0x00004000; // Software interrupt generation
while(1) {
} // wait here
}
SCREEN SHOTS FOR PROGRAM EXECUTION :

Fig 12.1 VIC configuration and ISR


Fig 12.2 Exception Vector Table

ASSIGNMENT:
1. What is role of exception vector table in exception handling?
2. Where exception vector table is located?
3. Explain program execution flow in case of IRQ exception.
4. How more than one IRQ s are serviced?
5. What are the changes we need to make in Startup file for writing our own ISR.

LAB 13
Fast Interrupts
AIM: To understand FIQ exception Handling mechanism
SPECIAL FUNCTION REGISTERS OF VECTORED INTERRUPT CONTROLLER :
VICIRQStatus VICFIQStatus VICRawintr
VICIntSelect VICIntEnable VICIntEnClr
VICSoftInt VICSoftIntClr
SPECIAL FUNCTION REGISTER DESCRIPTION:

THEORY:
Fast Interrupt request (FIQ) requests have the highest priority. If more than one request is
assigned to FIQ, the VIC ORs the requests to produce the FIQ signal to the ARM processor.
The fastest possible FIQ latency is achieved when only one request is classified as FIQ,
because then the FIQ service routine can simply start dealing with that device. But if more than
one request is assigned to the FIQ class, the FIQ service routine can read a word from the VIC
that identifies which FIQ source(s) is (are) requesting an interrupt.

Sample Program: Program that show use of FIQ Interrupt Handling.
#include <stdio.h>
#include <lpc23xx.h>
int a=0;
__irq void FIQ_Handler(void) // define FIQ handler
{
a++; // counter
}
int main()
{ SCS = (SCS|1);
PINMODE4 =(1<<20);
PINSEL4 = (1<<20);
EXTMODE =00; //Interrupt configuration, edge triggered
EXTPOLAR = 00; // positive going interrupt
VICIntEnable =(1<<14); // Enable interrupt
VICIntSelect =(1<<14); // set interrupt as IRQ
VICSoftInt =(1<<14); // Software interrupt generation
while(1) // wait for an interrupt
{
}
}
Fig 13.1 Main program and FIQ Handler

Fig 13.2 Branch to Interrupt Vector Table

ASSIGNMENT:
1. What information exception vector table contains?
2. Explain program execution flow in case of FIQ exception.
3. Why FIQ is known as Fast interrupt.
4. What are Dummy Exception handlers? Where they are written?
5. What are the changes we need to make in startup file when we want to define our exception
handlers?
6. What is Latency? Find Latency for FIQ.

APPENDIX A

Question Paper
DHARMSINH DESAI UNIVERSITY, NADIAD
(Faculty of Technology)
B. E. Sem.VII [EC] Examination
Embedded systems
Date: Time: 3 hours
Day: Marks: 60
_______________________________________________________________________
Instructions: 1. Assume suitable data if necessary.
2. Answer each section in separate answer book.

SECTION I
Q.1 Answer the following. [10]
a) Justify true/ false ARM core is having smaller die size compared to CISC core.
b) Mention registers visible in system mode and user mode.
c) An individual instruction takes three clock cycles to complete, so it has a three-cycle
latency, but the throughput is one instruction per cycle. Justify.
d) Which clocking scheme is implemented in ARM core. What is advantage of that scheme.
e) Draw ARM register bank floor plan.

Q.2. Attempt the following. [10]
a) Draw the sketch of data path activity for The first two (of three) cycles of a branch
instruction. Explain execution of Branch instruction using appropriate example.
b) Interface 10K half words of RAM and 16 K bytes of ROM with ARM7 core. How
processor deals with slower memory?
OR
a) What are the major components of the minimum data path cycle time. Explain ARM
data path timing (3-stage pipeline) using timing diagram.
b) Classify input /output signals to/from the ARM7TDMI core in terms of Address, Data and
Control signals.. Write significance of all signals in detail.
a) Draw and explain in detail ARM control logic structure. What type of control signals are
generated by this structure?
b) How VIC controller of LPC2368 generates FIQ or IRQ signals to ARM core? How
address of interrupt service routine is provided to ARM core when one of the thirty two
sources which are configured as IRQ is asserted?
OR
a) How barrel shifter is designed? What is the maximum number of bits that can be rotated
in single cycle in ARM7 core? Explain working of barrel shifter using left shift by two.
b) Draw timing diagram of Nonsequential memory cycle for 32 bit write operation. How
it differs from merged IS cycle?

SECTION II
Q.4. Answer following.
1. Serial peripheral interface is,
(i) full duplex & synchronous (ii) full duplex & asynchronous (iii) half duplex & asynchronous
(iv) half duplex & asynchronous [01]
2. In serial peripheral interface, during one data transfer the master can send,
(i) only a byte of data to the slave (ii) any byte of data to the slave
(iii) less than a byte of data to the slave (iv) 8-16 bit of data to the slave [01]
3. Find out the hexadecimal representation of 21.50 using IEEE 754 single precision standard.
[02]
4. Find out hexadecimal values of register R4 and R5 after executing given program.
MOV R2, #16
MOV R3, #0x10
CMP R3,R2
ADDLE R4, R2, R3
SUBGT R5, R2, R3 [02]
5. Explain pros & cons of Serial Peripheral Interface. [02]
6. Explain any four conditional branch instructions. [02]

Q.5 Attempt the following. [10]
1. Write an arm assembly program to load given eight decimal values sequentially in the
memory in arm state. Memory location starts from 0x50000000 & values are: 65434, 332, 54, 1,
64101, 02, 33. After loading data into memory, add all values and put result into register R2 &
average of all values in register R3. Do these two operations in the thumb state and after
completion of the task, return to arm state. Write comment for each instruction. Also write values
of R2 & R3.
OR
1. Explain different multiply instructions of ARM assembly language.
2. Explain co-processor data transfer & data operation instructions.

1. Explain different exception conditions of serial peripheral interface (SPI).
2.Mention the changes in different registers and memory location (if any) after executing
following ARM assembly instructions:
(i) STMDA r9!, {r0, r4, r6} (ii) LDMIB r11, {r1, r5, r8, r9} (iii) LDMFD r10!, {r1 r5}
OR
1. Explain all steps to configure SPI in master operation to transfer one byte data to slave. Take
necessary actions to make SPI ready for next data transfer.
2. Write an ARM assembly language program to find out minimum number from data given in
register r0 to r8.
____________________________________________________________________________

DHARMSINH DESAI UNIVERSITY, NADIAD.
(Faculty of Technology)
B. E. (EC), Sem-VII Embedded System
Third Sessional Examination
Date: 16/10/2008 Seat No:
Time : 12:00-1:00 Max. Marks: 36
Q.1 Do as directed: [12]
1. How the performance improvement of the ARM processor core is achieved?
2. Draw the standard ARM C program address space model & explain each part of the
model.
3. Justify ARM 7 core is biendian
4. How bits are stored and retrieved in ARM6 register cell circuit?
5. Justify true/false with suitable reason 2-phase non-overlapping clock
Scheme avoids racing problems
6. What are the sources of address to address multiplexer? Draw ARM address register
structure.

Q.2
1. Using Serial Peripheral Interface, master wants to transfer one byte data to slave.
Explain the procedure such that peripheral is ready for another data transfer in
future. [03]
2. Write down the steps to recover from given exception conditions in Serial
Peripheral Interface.
(i) SPI internal read buffer contains data that has not been read by the processor,
and a new transfer is completed.
(ii) Data is written in the SPI data register when a SPI data transfer is currently in
progress. [03]
3. Find out the value; which uses IEEE 754 single precision standard in keil Vision
real-view debugger, and; will give answer as C13C0000 in hexadecimal format.
[03]
4. Explain the different ways to access the operand in ARM if ARM gives architectural
support for high-level languages. [03]

-------------- OR -------------

Q.2
1. Find out the maximum speed that can be achieved in Serial Peripheral Interface using
external 12 MHz crystal & considering minimum value of the frequency of the
SYSCLK. Write & explain each step. [06]
2. Write the code for if-else conditional statement and for & do-while loops in
ARM assembly language as ARM gives architectural support for high-level
languages. [06]

Q. 3. [12]
1. Explain with suitable diagram Data processing instruction data path activity
for i) register-register operations and ii) register- immediate operations.
2. How cross-bar switch barrel shifter can shift 32 bits within single cycle? Explain
the principle of barrel shifter with example of left shift by 3.

-------------- OR -------------
Q.3 [12]
1. What are the design protocol for Advanced System Bus with respect to Bus
arbitration and bus transfers . Show how ARM7 is deploying these protocols
in its design.
2. Write all the steps taken by ARM 7 core when SWI XX instruction is executed.
Write program segment which identifies the number of SWI instruction.

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