CMOS Logic

INEL 4207 - Digital Electronics - Spring 2011

Figure 14.17 The CMOS inverter.

Microelectronic Circuits, Sixth Edition

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Copyright 2011 by Oxford University Press, Inc.

Figure 14.18

Microelectronic Circuits, Sixth Edition

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Copyright 2011 by Oxford University Press, Inc.

Figure 14.19

Microelectronic Circuits, Sixth Edition

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Copyright 2011 by Oxford University Press, Inc.

Figure 14.20 The voltage-transfer characteristic of the CMOS inverter when QN and QP are matched.

Microelectronic Circuits, Sixth Edition

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Copyright 2011 by Oxford University Press, Inc.

Qn and Qp are matched: kn = kp Use Vtn = Vtp = Vt .

VIH
Qp is in saturation, Qn is in triode region. = = kp 2 (VDD vi Vt ) 2 kn 2 2 (vi Vt ) vO vO 2

iDp iDn

2 (VDD vi Vt )2 = 2 (vi Vt ) vO vO

 vO vO 2(VDD vi Vt ) = 2vO + 2 (vi Vt ) 2vO vi vi vO = VIH VDD 2 VDD 2 VDD 2 2

(VDD VIH Vt )2 = 2 (VIH Vt ) VIH VIH

VIH

1 = (5VDD 2Vt ) 8

Use symmetry on VTC VIH VDD VDD = VIL 2 2 1 = (3VDD + 2Vt ) 8

VIL

1 N MH = (3VDD + 2Vt ) = N ML 8

 If Qn and Qp are not matched: r = kn /kp VM kn kp 2 (VDD VM + Vtp ) = (VM Vtn )2 2 2 VDD VM + Vtp = r (VM Vtn ) VDD + Vtp + rVtn = VM (1 + r) VM VDD + rVtn |Vtp | = 1+r

Figure 14.21

Microelectronic Circuits, Sixth Edition

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Copyright 2011 by Oxford University Press, Inc.

Figure 14.22 Dynamic operation of a capacitively loaded CMOS inverter: (a) circuit; (b) input and output waveforms; (c) equivalent circuit during the capacitor discharge; (d) trajectory of the operating point as the input goes high and C discharges through QN.

Microelectronic Circuits, Sixth Edition

Sedra/Smith

Copyright 2011 by Oxford University Press, Inc.

Approach from Secs. 10.2.3/4.10 5th edition Using piecewise integration

1.6C tP HL = W kn L n VDD 1.6C tP LH = W kp L p VDD

Discharge tP HL iav = C =

2nd approach using ave. current

VDD (VDD /2) CVDD = iav 2iav

iDN (E ) = iDN (M ) = tP HL n = =

1 (iDN (E ) + iDN (M )) 2 1 W (VDD Vtn )2 kn 2 L n 2 1 W VDD k (VDD Vtn )VDD 2 n L n 2

kn

n C W
L n 3Vtn VDD

7 4

VDD 2 2 Vtn + V DD

Equivalent to eq. 10.18 on 5th ed. but more general

Charging tP LH = p =
kp

p C W

L p VDD

2 +

7 4

3|Vtp | VDD

tP HL + tP LH tp = 2

Vtp VDD

Another Alternative Approach

Figure 14.23 Equivalent circuits for determining the propagation delays (a) tPHL and (b) tPLH of the inverter. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.

3rd Alternative approach

tP HL = 0.69RN C tP LH = 0.69RP C Empirical expressions 12.5 RN = k (W/L)n 30 RP = k (W/L)p These apply for several CMOS processes including 0.25m, 0.18m and 0.13m.

Logic Gates

Sec. 10.3 in 5th edition

Figure 14.28 Examples of pull-down networks.

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C = 2Cgd1 + 2Cgd2 + Cdb1 + Cdb2 + Cg3 + Cg4 + Cw Cg3,g4 = (W L)3,4 Cox + Cgsov3,gsov4 + Cgdov3,gdov4

Sec. 10.2.3 in 5th ed.

f14.24
Figure 14.24 Circuit for analyzing the propagation delay of the inverter formed by Q1 and Q2, which is driving a similar inverter formed by Q3 and Q4.

Microelectronic Circuits, Sixth Edition

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Copyright 2011 by Oxford University Press, Inc.

Cgd1,2, Cgsov3,4 and Cgdov3,4 are overlap capacitances

Figure 14.25 The Miller multiplication of the feedback capacitance Cgd1.

Microelectronic Circuits, Sixth Edition

Sedra/Smith

Copyright 2011 by Oxford University Press, Inc.

Example: CMOS 0.25m process with Cox = 6fF/m2, nCox = 115A/V2, pCox = 30A/V2, Vtn = - Vtp = 0.5V, and VDD = 2.5V. (W/L)n = 0.375m/0.25m, (W/L)p = 1.125m/0.25m Cgd, Cgsov, Cgdov 0.3fF/mW Cdbn = Cdbp = 1fF , CW= 0.2fF Find tp when the inverter is driving an identical inverter.

Inverter Sizing
C = Cint + Cext Increasing W/L by a factor S increases Cint C = SCint0 + Cext and decreases Req = (RN + RP )/2 by S with respect to the original Req0 . tp = 0.69 Req0 S (SCint0 + Cext )

1 = 0.69 Req0 Cint0 + Req0 Cext S

Example: If the inverter in the previous example, find (a) Cint and Cext, (b) factor S to reduce extrinsic part of tp by 2, (c) resulting tp, and (d) factor by which the area is increased.

Ipeak

n Cox = (W/L)n 2

VDD Vtn 2

f14.26

Figure 14.26 The current in the CMOS inverter versus the input voltage.

Microelectronic Circuits, Sixth Edition

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Copyright 2011 by Oxford University Press, Inc.

Figure 14.27 Representation of a three-input CMOS logic gate. The PUN comprises PMOS transistors, and the PDN comprises NMOS transistors.

Microelectronic Circuits, Sixth Edition

Sedra/Smith

Copyright 2011 by Oxford University Press, Inc.