Linear
VGSn VTn Vin VTn VDSn < VGSn VTn Vout < Vin VTn
Saturation
VGSn VTn Vin VTn VDSn VGSn VTn Vout Vin VTn VGSp VTp Vin VTp + VDD VDSp VGSp VTp Vout Vin VTp
NMO S
PMO S
VGSp VTp Vin VTp + VDD VDSp > VGSp VTp Vout > Vin VTp
(W (W
L )p L )n
115 10 6 0.63 ( 1.25 0.43 0.63 2 ) = 6 30 10 1.0 ( 2.5 1.25 0.4 1.0 2 )
= 3.5
VM versus Wp /Wn
1.8 1.7 1.6 1.5 1.4
10
Wp/Wn
10
VM is relatively insensitive to Wp/Wn around the center point. Small variations of the ratio do not change the VTC too much. For Wp=2Wn, VM1.2V Wp can be made only 2Wn instead of 3.5x or 3x saving some valuable area. Shifting of VTC by changing the Wn/Wp ratio results in a characteristics with asymmetric noise margins.
V (V)
VM
VM
Delays in a Circuit
Req depends strongly on the region of operation. For simple performance estimates use approximations: Using channel resistance in the linear region
where, k =
Req as the average of the two end points of the transition during switching. For an NMOSFET switching on in an inverter,
Req = V DD 1 = + = ( ) R V V R V on out DD on out 2 2
1 V DS = 2 I DS
+
Vout =V DD
V DS I DS
Vout =
V DD
(Ohm) R
eq
0 0 .5
1 .5
2 .5
DD
(V)
Effects of Resistance
Resistance affects performance RC delay Current supplied through resistive wire IR drop which degrades signal levels, especially important in the power distribution network reduces noise margin and changes logic levels as a function of the distance from the main supply terminals
Logic Logic Reduce distance between supply terminal & logic
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