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NETWORKS ON CHIPS

KIRAN.V Asst.Professor.RVCE,Bangalore-59

Motivation
Designing a system on a chip with large number of cores poses many challenging problems. Designing a flexible on-chip communication network. Designing a N/W which can provide the desired bandwidth and can be reused across many applications
KIRAN.V Asst.Professor.RVCE,Bangalore-59

Methodology
We can borrow and adapt the concept of packet switched communication from computer networks to design on chip networks The cores on the chip communicate among themselves by sending packets using a network of switches The network is built using a set of identical switches connected in regular topology.
KIRAN.V Asst.Professor.RVCE,Bangalore-59

Issues for design of the network


Switch design Design of network access by cores communication protocols

KIRAN.V Asst.Professor.RVCE,Bangalore-59

The inter connection architecture must provide facilities for a large number of cores to efficiently exchange information. Interconnection architecture should allow high communication bandwidth between pairs of cores Concurrent communication among many pairs of cores.
KIRAN.V Asst.Professor.RVCE,Bangalore-59

The communication architecture in such systems must also be able to support the Quality of service (QoS) The needs of heterogeneous systems that will require multiple-modes of operations and with varying levels real time response requirements The shrinking of process technology into the deepsubmicron (DSM) domain(i.e., below 90 nm)

KIRAN.V Asst.Professor.RVCE,Bangalore-59

Evolution of on-chip communication Architecture

KIRAN.V Asst.Professor.RVCE,Bangalore-59

Bus architecture
Bus-based interconnection is the most commonly used architecture for inter-core communication in present day SoCs. Buses help to time-share the wires among many communicating cores and lead to reduction of I/O pins incores and simplifies wiring. Buses are more scalable
KIRAN.V Asst.Professor.RVCE,Bangalore-59

Buses are also not scalable beyond some limit and may not provide required performance The available communication bandwidth is shared in large systems among all the units connected to the bus. To overcome above problem, bus based SoCs require interface designs or wrappers -Virtual Component (VC)interface. for every core before it can be connected to on-chip buses.
KIRAN.V Asst.Professor.RVCE,Bangalore-59

Standard On-Chip-Buses
ARM (www.arm.com)
AMBA (Advanced Microcontroller Bus Architecture)

IBM (www.chips.ibm.com)
CoreConnect (PLB/OPB/DCR)

PALM Chip (www.palmchip.com)


M Bus/Palm Bus

Mentor Graphics (www.inventra.com)


FISP Bus

OMI (www.omimo.be)
PI (peripheral Interconnect) Bus

Fujitsu (www.fujitsu.com)
Spcl Bus

KIRAN.V Asst.Professor.RVCE,Bangalore-59

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Virtual Socket Interface (VSI) Alliance design flow for SOC

KIRAN.V Asst.Professor.RVCE,Bangalore-59 H. V. RAVISH ARADHYA

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VSI hierarchical bus architecture for SOC design.

KIRAN.V Asst.Professor.RVCE,Bangalore-59

KIRAN.V Asst.Professor.RVCE,Bangalore-59

Unlike traditional bus-based on-chip communication architectures. NoCs are an attempt to scale down the concepts of large scale networks, and apply them to the embedded system-on-chip (SoC) domain. NoCs use packets to route data from the source to the destination component, via a network fabric consisting of switches (routers) and interconnection links (wires)
KIRAN.V Asst.Professor.RVCE,Bangalore-59

KIRAN.V Asst.Professor.RVCE,Bangalore-59

KIRAN.V Asst.Professor.RVCE,Bangalore-59

A network interface ( NI) at the boundary of each PE is used to packetize any data generated by the PE. NI is connected to a router,which has buffers at its input to accept data packets from a PE or from other routers connected to it. NI can be partitioned into two parts. The part connected to the network is resource independent and the other part connected is resource dependent. The resource independent part can be reused for interfacing any new resource crossbar switch inside the router is used to route the data packets from the input buffers to the appropriate output link, based on the address in the packet header. Arbiter component is used to determine which packets get priority when multiple packets from different sources are vying for transfer on the same interconnection link.

KIRAN.V Asst.Professor.RVCE,Bangalore-59

KIRAN.V Asst.Professor.RVCE,Bangalore-59

KIRAN.V Asst.Professor.RVCE,Bangalore-59

NETWORK TOPOLOGY
The topology of an NoC specifies the physical organization of the interconnection network It defines how nodes, switches, and links are connected to each other Classification Direct networks Indirect networks Irregular networks.
KIRAN.V Asst.Professor.RVCE,Bangalore-59

Parameters Which determines the Network Performance


Network Diameter: Maximum number of intermediate nodes between a source and any destination pair. Connectivity: Number of direct neighbors of any switch node in the network. Bandwidth: Measure of maximum rate (bits/second) of information flow in the network. Latency is the time taken by a message to travel from the source to the destination.
KIRAN.V Asst.Professor.RVCE,Bangalore-59

connection-oriented : Route is established between the source and the destination for the information transmission. connectionless-oriented : Information is encapsulated in entities, which travel through the network from source to the destination.
KIRAN.V Asst.Professor.RVCE,Bangalore-59

Connection-oriented and Connectionless Communication systems

Direct Networks
In direct network topologies, each node has direct point-to-point links to a subset of other nodes in the system called neighboring nodes. The nodes consist of computational blocks and/or memories. NI block that acts as a router, this router is connected to the routers of the neighboring nodes through links.
KIRAN.V Asst.Professor.RVCE,Bangalore-59

Point to point

Mesh

KIRAN.V Asst.Professor.RVCE,Bangalore-59

KIRAN.V Asst.Professor.RVCE,Bangalore-59

Indirect Networks
Each node is connected to an external switch switches have point-to-point links to other switches. The NI associated with each node connects to a port of a switch. Switches do not perform any information processing, and correspondingly nodes do not perform any packet switching.
KIRAN.V Asst.Professor.RVCE,Bangalore-59

KIRAN.V Asst.Professor.RVCE,Bangalore-59

Irregular Networks
Irregular network topologies are usually a mix of shared bus, direct, andindirect network topologies. The goal of these topologies is to increase available bandwidth as compared to traditional shared buses, and reduce the distance between nodes as compared to direct and indirect networks.
KIRAN.V Asst.Professor.RVCE,Bangalore-59

KIRAN.V Asst.Professor.RVCE,Bangalore-59

Communication Protocols: A set of rules and methods are required for transfer of information from one resource to another resource in any system. These rules are generally referred as protocols. communication protocols determine how a resource is connected to the network as well as how the information flows from source to destination protocols partitioned and organized in many layers The architecture defining the protocol layers is referred as a protocol stack
KIRAN.V Asst.Professor.RVCE,Bangalore-59

KIRAN.V Asst.Professor.RVCE,Bangalore-59

In a layered protocol, various functions required for communication are divided hierarchically among various layers. Physical Layer: concerned with physical characteristics of the physical medium used for connecting switches and resources with each other. In the context of SoC, it specifies voltage levels, length and width of wires, signal timings, number of wires connecting two units
KIRAN.V Asst.Professor.RVCE,Bangalore-59

Data Link Layer: This layer has the responsibility of reliably transferring information across the physical link. The data link layer takes care of hardware synchronization, error detection and Correction. Data encoding or data rate management for controlling power consumption
KIRAN.V Asst.Professor.RVCE,Bangalore-59

Network Layer: The network layer provides the service of communicating a packet from one resource to another using the network of switches. Its functionality includes buffering of packets Routing decisions in the intermediate switches. Packet switching techniques: Store and forward (SAF), Virtual cut through (VCT), Wormhole (WH).
KIRAN.V Asst.Professor.RVCE,Bangalore-59

Routing techniques Deterministic : same path between a source destination pair Adaptive :This use traffic and network condition information to dynamically create a path that avoids congestion Transport Layer: This layer has the responsibility of establishing end-to-end connection and delivery of messages using the lower layers. Functionality includes packetization of a message at the source and depacketization or assembly of packets into a message at the destination node.
KIRAN.V Asst.Professor.RVCE,Bangalore-59

Session, presentation, and application layers: software layers made up of the system software, System software provides an abstraction of the underlying hardware platform, and the application software, which leverages the hardware abstraction to effectively exploit the capability of the hardware. The system software is tightly coupled with the NIs that are responsible for connecting PEs to the NoC fabric.
KIRAN.V Asst.Professor.RVCE,Bangalore-59

Data Format at various layers

KIRAN.V Asst.Professor.RVCE,Bangalore-59

Packet Switching
Instead of establishing a path before sending any data as is done in circuit switching, the packets are transmitted from the source and make their way independently to the receiver, possibly along different routes and with different delays. SAF switching: Packet is sent from one router to the next only if the receiving router has buffer space for the entire packet. Routers forward a packet only when it has been receivedin its entirety. The buffer size in the router is at least equal to the size of apacket. Because of large buffer size requirements for this technique, it isnot commonly used in NoCs.
KIRAN.V Asst.Professor.RVCE,Bangalore-59

VCT switching: Technique reduces the router latency over SAF switching by forwarding the first flit of a packet as soon as space for the entire packet is available in the next router ,Theother flits follow the first flit without any delay. If no space is available in the receiving buffer, no flits are sent, and the entire packet is buffered. Since the buffering requirements of this scheme are the same as that for SAF, Not frequently used in NoCs.
KIRAN.V Asst.Professor.RVCE,Bangalore-59

KIRAN.V Asst.Professor.RVCE,Bangalore-59

WH switching: In this technique, buffer requirements are reduced to one flit, instead of an entire packet. A flit from a packet is forwarded to the receiving router if space for that flit is available in the router. If there is insufficient space in the next router to store the entire packet, parts of the packet are distributed among two or more routers. Distribution of packets among multiple routers can result in blocking of links,which leads to higher congestion than in SAF and VCT. WH switching is also more susceptible to deadlocks than both SAF and VCT switching,due to usage dependencies between links., NoC architectures use WH switching

KIRAN.V Asst.Professor.RVCE,Bangalore-59

ROUTING ALGORITHMS
Static routing Dynamic routing, Distributed routing Source routing Minimal routing Non-minimal routing

KIRAN.V Asst.Professor.RVCE,Bangalore-59

KIRAN.V Asst.Professor.RVCE,Bangalore-59