1464

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 3, MARCH 2013

Development of a SiC JFET-Based Six-Pack Power Module for a Fully Integrated Inverter
Fan Xu, Student Member, IEEE, Timothy J. Han, Member, IEEE, Dong Jiang, Member, IEEE, Leon M. Tolbert, Senior Member, IEEE, Fei (Fred) Wang, Fellow, IEEE, Jim Nagashima, Member, IEEE, Sung Joon Kim, Srikanth Kulkarni, and Fred Barlow, Senior Member, IEEE

AbstractIn this paper, a fully integrated silicon carbide (SiC)based six-pack power module is designed and developed. With 1200-V, 100-A module rating, each switching element is composed of four paralleled SiC junction gate eld-effect transistors (JFETs) with two antiparallel SiC Schottky barrier diodes. The stability of the module assembly processes is conrmed with 1000 cycles of 40 C to +200 C thermal shock tests with 1.3 C/s temperature change. The static characteristics of the module are evaluated and the results show 55 m on-state resistance of the phase leg at 200 C junction temperature. For switching performances, the experiments demonstrate that while utilizing a 650-V voltage and 60-A current, the module switching loss decreases as the junction temperature increases up to 150 C. The test setup over a large temperature range is also described. Meanwhile, the shoot-through inuenced by the SiC JFET internal capacitance as well as package parasitic inductances are discussed. Additionally, a liquid cooled three-phase inverter with 22.9 cm 22.4 cm 7.1 cm volume and 3.53-kg weight, based on this power module, is designed and developed for electric vehicle and hybrid electric vehicle applications. A conversion efciency of 98.5% is achieved at 10 kHz switching frequency at 5 kW output power. The inverter is evaluated with coolant temperature up to 95 C successfully. Index TermsElectric vehicle and hybrid electric vehicle (EV/HEV), SiC junction gate eld-effect transistor (JFET), silicon carbide (SiC) inverter, six-pack power module.

I. INTRODUCTION

HE advent of electric vehicle and hybrid electric vehicle (EV/HEV) brings several challenges to power electronic

Manuscript received February 15, 2012; revised April 29, 2012; accepted June 6, 2012. Date of current version October 12, 2012. This work was supported by the Engineering Research Center Program of the National Science Foundation (NSF) and the Department of Energy under NSF Award Number EEC-1041877 and the CURENT Industry Partnership Program. Recommended for publication by Associate Editor H.-P. Nee. F. Xu, L. M. Tolbert, and F. (Fred) Wang are with the Department of Electrical Engineering and Computer Science, The University of Tennessee at Knoxville, Knoxville, TN 37916 USA (e-mail: fxu6@utk.edu; tolbert@utk.edu; fred.wang@utk.edu). T. J. Han, J. Nagashima, and S. J. Kim are with the Global Power Electronics, Inc., Irvine, CA 92618 USA (e-mail: jhhan@gpe-energy.com; jnagashima@gpe-energy.com; sjkim@gpe-energy.com). D. Jiang is with the United Technologies Research Center, East Hartford, CT 06118 USA (e-mail: jiangd@utrc.utc.com). S. Kulkarni is with Micron Technology Inc., Boise, ID 83716 USA (e-mail: srikanth@vandals.uidaho.edu). F. Barlow is with the Department of Electrical and Computer Engineering, University of Idaho, Moscow, ID 83844 USA (e-mail: fbarlow@uidaho.edu). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TPEL.2012.2205946

modules on both power device and packaging technologies, to operate in a high-temperature environment and minimize weight and volume as well [1], [2]. In the harsh operating conditions, electrical, thermal, and lifetime limitations reduce the reliability of traditional Si insulated gate bipolar transistor (IGBT) power devices and modules [1][4]. To meet these design challenges, several options are provided in [5], such as the improvement of thermal management techniques, increasing the Si die area to increase cooling area, and using soft switching to eliminate loss which is realized in [6]. Another option is using wide bandgap power semiconductor materials such as silicon carbide (SiC), which shows characteristics superior to conventional Si semiconductors for high temperature, high power density converters in EV/HEV [7]. SiC power electronic semiconductors provide high breakdown voltage, fast switching, low on-state resistance, and high temperature tolerance. Meanwhile, SiC has high thermal conductivity, which leads to improved power dissipation and higher power handling capability. Fast switching and low on-state resistance increase the efciency of SiC-based power conversion systems, and reduce the requirement of the cooling system. High junction temperature capability helps SiC devices to work in a high-temperature environment. High switching frequency leads to the reduction of the number and mass of inductors [8], [9]. SiC diode is the rst commercial SiC power semiconductor and has been widely used with Si switching devices [10][12]. SiC bipolar junction transistor (BJT) has good performance for high-voltage and high-temperature application. However, a certain base current in steady state is necessary to drive BJT which causes high driving power [13], [14]. SiC MOSFET and SiC junction gate eld-effect transistor (JFET) have been improved through the years and have been commercialized. Research on the application of SiC MOSFETs and SiC MOSFET-based power module are presented in [15][19]. However, the modules cannot operate above 200 C, due to the SiC MOSFET inherent oxide interface issues at high temperatures [20][22]. Even though some of the SiC MOSFETs operating above 200 C have been demonstrated [23], [24], the data concerning their reliability are not provided. SiC JFETs do not have any interface issues and are considered good candidates for SiC-controlled switches. Many publications have presented SiC JFET-based power module and power conversion systems [25][29] in recent years. In [25], the SiC JFET has been pushed to extremely high ambient temperatures, 450 C. However, the JFET drain current Ids decreases signicantly with rising temperature [25], and thermal runaway is a potential

0885-8993/$31.00 2012 IEEE

XU et al.: DEVELOPMENT OF A SiC JFET-BASED SIX-PACK POWER MODULE FOR A FULLY INTEGRATED INVERTER

1465

Fig. 1.

Six-pack SiC JFET-based power module.

threat when the power devices operation temperature is higher than its allowable limit [7], [30], [31]. Most of the published SiC JFET power modules are single phase-leg modules [26], [27]. The modules in [28] and [29] are three-phase modules, but the power rating of them is 4 kW. Therefore, high-power, highdensity SiC JFET-based three-phase power modules with high operating temperature capabilities still need to be developed, for the tough operating conditions in EV/HEV applications. In addition, some issues of SiC JFET-based power module, such as packaging technologies and phase-leg shoot-through during fast switching [32], need to be solved. In this paper, a fully integrated SiC-based three-phase power module is designed and developed. With 1200-V, 100-A rating of the module, each switching element is composed of four paralleled SiC JFETs with two antiparallel SiC Schottky barrier diodes (SBDs). The stability of the module assembly processes is conrmed with the thermal shock test. The phaseleg shoot-through issue is analyzed by switching test with a 650-V voltage and 60-A current. Additionally, a three-phase inverter based on this power module is designed and developed for the EV/HEV applications. This paper is organized as follows: Section II describes the six-pack SiC power module, with its assembly processes and package parasitics; Section III shows the static characteristics of the module; the switching test and phase-leg shoot-through discussion are presented in Section IV; in Section V, the three-phase inverter is developed and tested; and nally, Section VI provides conclusions. II. SIX-PACK ALL-SIC POWER MODULE A. Module Overview and Layout Design Fig. 1 shows the picture of SiC JFET-based power module with 1200-V, 100-A power rating. The module size is 140 mm 70 mm 12.7 mm. The module consists of a three-phase bridge conguration with each switching element having four 4.17 mm 4.17 mm 1200 V normally-on SiC JFETs and two 2.7 mm 2.7 mm 1200 V SiC SBDs from SiCED in parallel. Each phase leg is designed in a separate substrate, 38.5 mm 38.5 mm. Fig. 2(a) shows the phase-leg circuit. The basic
Fig. 2. Phase-leg structure of six-pack SiC power module. (a) Phase-leg circuit. (b) Phase-leg layout. (c) Phase-leg picture.

switching cell theory proposed in [33] is used during the phaseleg layout design. As shown in Fig. 2(b), the devices in the commutation loop are placed at the same side. Thus, the physical length of the commutation loop is specically reduced compared with conventional module layout, in which the JFET and its antiparallel diode are seated at one side. This layout design

1466

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 3, MARCH 2013

TABLE I PARASITIC INDUCTANCES OF THE THREE-PHASE SiC POWER MODULE

leads to the reduction of parasitic inductance in natural current commutation path. The gate loop layout, shown in Fig. 2(b), is composed of two control pins placed between the two closer JFETs to make the distance evenly distributed among four paralleled JFETs. This step is necessary in order to balance gate loop parasitics in the module. Fig. 2(c) shows the phase-leg picture. The package parasitics of the module are extracted by Maxwell Q3D parameter extractor [34], and the values of parasitic inductances are listed in Table I, which come from the L matrix extracted by Q3D ac analysis at 100 MHz operating frequency, with a 1% margin of error. The common source inductance is the parasitic inductance shared by the JFET gate loop and the main loop, and the source inductance is the JFET sourceside parasitic inductance only in the main loop. The gate loop inductance value of each JFET includes the inductance shared by four paralleled JFETs, called common gate inductance, and the inductance only in each JFET gate loop. The common gate inductance includes the mutual couplings of paralleled JFETs gate loops, which are important for paralleled devices switching behaviors [35]. B. Package Design The package of the module is designed to work at a junction temperature of at least 200 C. The components and manufacturing processes that have been used can be broken down into several key pieces: die-attach, wire bonding, substrates, and housing/encapsulation. The SiC JFETs and SBDs are bonded to the active metal bonding Cu [36], [37] on Si3 N4 substrates with lead-based solder that melts at a temperature of 310 C. The solder and substrate are selected since they have been demonstrated in prior work to be stable when used continuously at 200 C, and survive thousands of thermal shock cycles from 40 C to + 200 C [38][40]. The die bonding is done in a uxless process with the aid of a vacuum soldering furnace. The source and gate connections for the JFETs and SBDs connections are formed using 99.99% pure 5-mil diameter Al wire bonds. In order to avoid very long gate wire bonds, the thin lm Al on ceramic or glass ceramic shunts are used. The metallization on these substrates is designed, in that the trace width is narrow so as to minimize the parasitic capacitive coupling to the metal

trace below the low-temperature co-red ceramic. To form the complete three-phase inverter, three substrates are bonded to a Ni-plated Cu molybdenum alloy base plate and connected in parallel by connecting the substrates to common +dc and dc terminals. To sample the source voltages and control the gatesource voltages Vgs , Au over Ni-plated brass control pins is bonded to the metal traces on the direct bond copper substrates. The pins are bonded with the lead-based solder that is used for die bonding. The housing is mounted on the baseplate that is machined from a glass-lled polyimide material, torlon 5030. The housing is used to support the busbars, Ni-plated Cu, and contain the encapsulation gel, Nusil Gel 8100, during the curing process. Again, these materials are chosen since they are stable and reliable when used at these temperatures [41], [42]. All switching components and interconnects are isolated from the heat sink baseplate. For simplifying system assembly and thermal management, the interconnection to the dc voltage input terminals and the phase-leg output terminals are assigned as a screw terminal type. The module also includes three thermistors to monitor the substrate temperature. Stresses in the die-attach interface during operation are simulated by thermal shock testing (TST) by cycling 54 samples between 40 C and 200 C, as shown in Fig. 3(a). This set of TST conditions corresponds to a rate of temperature change (dT/dt) of 1.3 C/s. To evaluate potential metallurgical issues, another 54 die-attach samples are subject to high temperature storage (HTS) test at 200 C. The TST on the samples is performed for a maximum of 1000 cycles and the HTS is performed for a maximum of 1000 h. HTS and TST are chosen since the HTS test reveals direct temperature effects such as diffusion or decomposition of polymeric materials, while the TST reveals damage due to effects such as expansion- and contraction-induced mechanical stresses. These test conditions are somewhat arbitrary since there is no published automotive specication for this temperature range when these tests begin. Therefore, the researchers adopt this standard based on reviewing a number of automotive and former mil-spec standards as representative of what would commonly be used in a variety of applications. Some application may require more cycles and some may require fewer; however, these test conditions are a reasonable compromise. From the tests, it is observed that high lead content solders show very reliable die-attach interfaces after the TST and HTS. This observation is based on the fact that the shear strength of the lead-based die-soldering material shows statistically insignicant drop after TST or HTS, as shown in Fig. 3(b) and (c). Fig. 4 shows the observed change in the pull strength of the wire bonds in both control and encapsulated samples. It is observed from the control samples that the wire pull strength drops signicantly with the increased number of temperature cycles. From the encapsulated samples, the drop in the pull strength of the wires is greater than that in the control samples. This is likely due to the fact that the gel itself has a very high coefcient of thermal expansion (CTE), and although it has a low modulus, it exerts some small amount of force on the wires. However, the pull strengths of the wire bonds in the encapsulated samples are still greater than the minimum preseal

XU et al.: DEVELOPMENT OF A SiC JFET-BASED SIX-PACK POWER MODULE FOR A FULLY INTEGRATED INVERTER

1467

wire pull strength at the end of the 1000 cycles, as specied in MIL-STD 883. This nding is relevant to module construction since it would potentially enable alternative methods for providing isolation in the module that do not require encapsulating gel. III. STATIC CHARACTERISTICS The static characteristics of the switching element in the module are obtained with a curve tracer at various temperatures from 25 C to 200 C, as shown in Fig. 5. In the test, the module is heated with a hot plate with a thermocouple as the temperature monitor. The forward characteristics of switching element are obtained at JFET gate-source voltage Vgs of 0 V, as shown in Fig. 5(a). Fig. 5(b) shows the forward characteristics at different Vgs at 200 C. Fig. 5(c) illustrates the transfer characteristic at different temperatures. Since the JFETs are normally-on devices, the pinch-off voltage is negative. From Fig. 5(c), the pinch-off voltage is lower with increasing temperatures, from 16 V at 25 C to 17 V at 200 C. Fig. 5(d) shows the reverse characteristics of the switching element measured with the JFETs blocked by Vgs of 22 V, in which both the antiparallel diodes and JFET body diodes are considered. The threshold voltage Vth decreases with rising temperatures, and the slope of the linear region becomes shallower with rising temperatures, which means the series resistance RD of the diode increases. The measurement of the on-state resistance of the JFET is based on the slope of the forward characteristic in the linear region. Fig. 6 shows that the four paralleled SiC JFETs on-state resistance RJ increases with higher temperature, from 25 m at 25 C to 55 m at 200 C, at 60 A drainsource current Ids , at Vgs = 0 V. The low on-state resistance and high temperature tolerance determine the low conduction loss of SiC-based power module even at 200 C. For JFET-based switching cell, when current ows through drainsource direction, only RJ conducts current, and the conduction loss is given in (1). When current ows through source drain direction, the current will ow in two conditions, and when current is smaller than a threshold value, only the JFET conducts. When the current exceeds this threshold value, both the JFETs and the diodes will conduct current [43]. The switching cell equivalent circuit in this mode is shown in Fig. 7, and conduction loss is given as Pcon = I 2 RJ Pcon = I 2 RJ , Pcon (1) I (2) Vth RJ Vth RJ I + I 2 RJ RD Vth = , I> . RJ + RD RJ

Fig. 3. Thermal prole and shear test results for solder die-attach samples. (a) Thermal shock cycle prole. (b) Shear strength during 1000 cycles. (c) Shear strength during 1000 h.

Fig. 4. Pull strength of wire bonds plotted versus number of shock cycles from 40 C to 200 C.

From Fig. 5(a) and (d), the reverse diodes start to conduct sourcedrain direction current at 36 and 12 A, at 25 C and 200 C, respectively. The diodes currents include the currents owing through both antiparallel SBDs and JFETs body diodes. Fig. 8(a) and (b) shows the sourcedrain direction current sharing between JFETs and diodes at 25 C and 200 C at different load current levels. Fig. 8(c) and (d) shows the current sharing at different temperatures at 20- and 60-A load currents,

1468

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 3, MARCH 2013

Fig. 6.

On-state resistance of four paralleled SiC JFETs in the module.

Fig. 7. Switching cell equivalent circuit when current ows through source drain direction.

respectively. These gures demonstrate that as the temperature increases, the reverse diodes starting conduction current decreases and the shared current increases. In this SiC JFET-based power module, the JFETs channel will conduct more current than the reverse diodes even at 200 C, 60 A. IV. SWITCHING PERFORMANCE EVALUATION In this section, the module phase-leg switching behaviors are evaluated by double pulse test (DPT). The Saber simulation circuit is based on the phase-leg circuit in Fig. 2(a) with parasitic inductance shown in Table I. In the experiments, the module is tested at a 650-V dc bus voltage, 60-A current, and 150 C junction temperature. The load is a 1-mH inductor with 7 pF equivalent parallel capacitance. A. DPT Circuit and Gate Drive Fig. 9 shows DPT circuit with gate drive schematic. Both high-side and low-side switching elements are four paralleled SiC JFETs with two antiparallel SiC SBDs. In the test, the four high-side JFETs are off, and the double pulse signal is applied to the low-side JFETs gate terminal. As shown in Fig. 10, the load inductor is charged to rated current value at the end of the rst pulse. When low-side JFETs are turned OFF, load current commutates to high-side SBDs. The load current commutates back to low-side JFETs when they are turned ON during the second pulse. The self-heating of the devices is not considered and the junction temperature is assumed the same as the case temperature because of the slow thermal time constant compared to the pulse duration. Considering JFET pinch-off voltage measured previously, and the devices 25-V gate breakdown voltage, a value of 0 V of Vgs is chosen for turn-on and 22 V of Vgs is used for

Fig. 5. Static characteristics of the switching element in the module. (a) Paralleled SiC JFETs forward characteristic. (b) Paralleled SiC JFETs forward characteristic at 200 C. (c) Paralleled SiC JFETs transfer characteristic. (d) Paralleled diodes forward. characteristic.

XU et al.: DEVELOPMENT OF A SiC JFET-BASED SIX-PACK POWER MODULE FOR A FULLY INTEGRATED INVERTER

1469

Fig. 9.

DPT circuit with gate drive schematic.

Fig. 10.

DPT waveforms. (Time: 20 s/div).

TABLE II MEASUREMENT APPARATUS USED IN MODULE DPT

Fig. 8. Sourcedrain direction current sharing between JFETs and diodes. (a) Current sharing at 25 C at different load current levels. (b) Current sharing at 200 C at different load current levels. (c) Current sharing at different temperatures at 20-A load current. (d) Current sharing at different temperatures at 60-A load current.

turn-off. The driver IC in DPT is IXDN409 from IXYS. In the test, RCD network [44] is used between the gate driver and JFETs to adapt to the different gate characteristics in case of JFETs paralleling. In Fig. 9, the turn-on resistor is Rg 1 //Rg 2 = 4 , and the turn-off resistance is Rg 1 = 10 . The measurement apparatuses, which have high bandwidth for switching measurement, are listed in Table II. The propagation delays of probes are compensated. In the test, the shoot-through protection of the phase leg is realized by an IGBT, which is connected in series with +dc bus as shown in Fig. 9. Once the current exceeds the limit, the IGBT will be turned OFF to separate the phase leg from dc power supply and protect the module. Fig. 11 shows a photograph of the high-temperature testing setup. The module is heated by connecting to the hot plate. The temperature is monitored by a thermocouple, and a fan is used to cool the printed circuit board and the shunt resistor.

1470

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 3, MARCH 2013

Fig. 11.

High temperature switching test setup.

Fig. 13. Switching loss as a function of load current at 650-V dc voltage with different temperatures. (a) Turn-on loss. (b) Turn-off loss.

Fig. 12. Switching waveforms at 650 V and 60 A. (a) Turn-on waveforms. (b) Turn-off waveforms.

B. Switching Characteristic Fig. 12(a) and (b) shows the turn-on and turn-off waveforms of four paralleled SiC JFETs in the module, respectively. The waveforms are obtained with a 650-V voltage and 60-A current.

The turn-on overshoot current is 18 A at 150 C due to the discharging current of junction capacitance of high-side JFETs body diodes and antiparallel SBDs. It is veried in [43] that the use of SiC SBD, which has no reverse recovery, helps to reduce the turn-on overshoot current. From the comparison of the switching waveforms at 25 C and 150 C in Fig. 12, it is observed that the SiC JFETs switch faster at 150 C than at 25 C. In this paper, the turn-on time ton is dened as the time from the current rising to 10% of its peak value until the voltage falls to 10% of the dc voltage value. Similarly, the turnoff time to is dened from the time the current falls to 90% until the voltage rises to 90% of its dc value. At 150 C, ton is 140 ns and to is 170 ns. However, ton is 160 ns and to is 220 ns at 25 C. Fast switching leads to low switching loss. The switching loss calculation covers the whole switching transient. From the tests, the turn-on loss Eon of four paralleled SiC JFETs in the modules switching element is 3.8 mJ at 25 C and 3.4 mJ at 150 C. The turn-off loss Eo is 3.6 mJ at 25 C and 2.9 mJ at 150 C. Fig. 13(a) and (b) shows the Eon and Eo as a function of load current at different temperatures, under 650-V dc voltage. Both turn-on and turn-off losses of SiC JFETs, with antiparallel SiC SBDs in the module, decrease with the temperature increasing. The switching loss of the Si IGBT, IGW60T120 from Inneon which has the same rating as this power module, is 9.5 mJ at 25 C and 15.8 mJ at 150 C, at

XU et al.: DEVELOPMENT OF A SiC JFET-BASED SIX-PACK POWER MODULE FOR A FULLY INTEGRATED INVERTER

1471

Fig. 14. JFET structure and package parasitic impact on phase-leg shootthrough. (a) SiC JFET structure. (b) Phase-leg circuit with JFET internal capacitance and parasitic inductances in gate loop and dc bus, during low-side JFETs turning ON.

600-V voltage and 60-A current [45]. The comparison shows the low switching loss of SiC JFET-based power module obviously. C. Discussion on Phase-Leg Shoot-Through Shoot-through is dened as both high-side and low-side switches in a phase leg being turned ON at the same time. It will cause additional power dissipation in the switching devices, increase losses [46], or even damage devices. Shoot-through is mainly caused by high dv/dt during a switching transient. The structure of a SiC JFET, as shown in Fig. 14(a) [47], leads to the existence of the intrinsic capacitance, as shown in the circuit in Fig. 14(b), which is a crucial factor in determining the switching speed. For a normally-on JFET, the capacitor Cgs is charged during turn-on transient, and the device will be turned ON after Vgs exceeds the pinch-off voltage. During turn-off transient, Cgs will discharge to reduce Vgs . Even though a JFET is not switching, its drain and source terminal voltages still vary when other switches are turning ON and OFF, and the internal capacitance of it will be charged or discharged due to dv/dt. Since the SiC power module has a fast switching speed, and the normally-on JFET gate breakdown voltage is only a few volts away from the pinch-off voltage, 25 and 17 V, respectively, the issues of phase-leg shoot-through need to be addressed.

The package parasitics play signicant roles on module electrical performances. It is demonstrated in [48] that JFET drain side, source side, and gate loop inductances have signicant role on its switching performance. Furthermore, the existence of the parasitic inductance may cause shoot-through during fast switching transient. The key parasitics include gate loop inductances and dc bus inductances. The voltage of phase-leg output terminal drops from 650 to 0 V during low-side JFETs turning ON in the test. At this time, the gate loop current ig appears in high-side JFETs gate loops because of the existence of JFET internal capacitance. When ig increases, there is a voltage VL across parasitic inductance Lg , as shown in Fig. 14(b). Since external gate voltage VG and Vgs are negative values to turn OFF the normally-on JFET, it is possible that Vgs is larger than pinch-off voltage if VL is large enough. Fig. 15(a) shows the simulation results of high-side JFET Vgs and channel current with different values of Lg . It is obvious that large Lg in highside JFET gate loop will cause Vgs of JFET to be larger than its pinch-off voltage. In addition, the JFET internal capacitance will have a charge current ibus associated with it on the dc bus, and ibus will cause a voltage drop Vbus across the dc bus parasitic inductance Lbus , as shown in Fig. 14(b). This effect may also result in shoot-through since it leads to high-side JFETs drain voltage being higher than dc voltage and therefore increases the dv/dt during switching. Fig. 15(b) shows the simulation results of high-side JFET Vgs and channel current with different values of Lbus . A large Lbus leads to Vgs being more than the pinch-off voltage and causes shoot-through as shown in the gure. In addition, temperature is another factor for phase-leg shootthrough. From Fig. 5(c), the JFET pinch-off voltage decreases with the temperature increasing. So, the shoot-through is more severe at higher temperature because of the reduction of the difference between JFET turn-off voltage and pinch-off voltage. Based on the aforementioned analysis, shoot-through can be inuenced by many factors including the internal capacitance, package parasitic inductances, and operation temperature. The key parasitics include parasitic inductances in JFET gate loop and module dc bus. Since the SiC JFET-based power modules are often operated at higher temperatures, it is more important to reduce the parasitic inductances in gate loops and dc buses. Due to the simulation results in Fig. 20, the gate loop and dc bus parasitic inductance values of the module, listed in Table I, are small enough to avoid phase-leg shoot-through at the proposed test condition. V. SiC INVERTER DEVELOPMENT Based on the six-pack power module developed and characterized previously, a three-phase inverter is developed for EV/HEV applications, shown in Fig. 16(a). This inverter has a designed power rating of 30 kW continuous and 50-kW peak. The custom gate driver, shown in Fig. 16(b), contains circuits for inherently safe operation of the depletion mode JFETs under start-up and fault modes. The dc input consists of metalized 94-F polypropylene lm capacitors with segmented foils to provide short-circuit protection. There is an integral input LC electromagnetic interference lter to reduce conducted

1472

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 3, MARCH 2013

Fig. 16. Three-phase SiC inverter prototype. (a) Integrated prototype inverter. (b) Gate driver board integrated on SiC power module. TABLE III SiC INVERTER SPECIFICATIONS

Fig. 15. Gate loop and dc bus parasitic inductances inuence on phase-leg shoot-through at 200 C. (a) High-side JFET V g s and channel current with different L g . (b) High-side JFET V g s and channel current with different L b u s .

line currents. The controller is a Texas Instruments Piccolo TMX320F28035 microcontroller-based control card. The input and output power and signal connections are by keyed twist-lock connectors for maximum safety and convenience. The inverter specications are summarized in Table III. This liquid cooled inverter is 22.9 cm 22.4 cm 7.1 cm in dimension with a volume of 3.6 L, and a weight of 3.53 kg. A. Gate Driver Circuits With Shoot-Through Protection The SiC JFETs used in the module have a normally-on characteristic, and when they are in the phase-leg with dc-link voltage

active, any failure of gate driver will cause the shoot-through. Thus, an inherently safe gate driver for normally-on JFETs is developed with 12-V dc-link voltage and 60-mA current, as shown in Fig. 17. The circuit uses a linear regulator to develop an internal operating voltage, which is positive compared to the low-side SiC JFETs source, from any voltage applied to the high voltage bus ranging from 6 to 650 Vdc . The negative gate voltage, which nominally is regulated at 22 V, is created using a high-speed switching buckboost converter. The

XU et al.: DEVELOPMENT OF A SiC JFET-BASED SIX-PACK POWER MODULE FOR A FULLY INTEGRATED INVERTER

1473

Fig. 17.

Schematic diagram of the inherently safe gate bias circuit.

buckboost converter operates with a switching speed in the low mega Hertz region from a discrete controller that has been designed to start up rapidly allowing the negative gate voltage to be generated in less than a couple hundred microseconds. The heart of the buckboost converter is a small inductor of 6 mm3 which is 2.5 H with a 1-A peak current at 2 MHz, built on a ferrite core. The control circuit regulates the voltage on JFET gate input using a simple start-stop algorithm to minimize complexity and component count. The Zener diodes prevent voltage overshoot due to the fast rise time of the negative bias voltage. An external bias voltage can also be provided for the inherently safe circuit to reduce power dissipation in the linear regulator and to maintain the circuit in a standby mode. For normal operation, a conventional gate drive IC, Inneon IED02I12-FA, is used, to provide gate voltage of 0/22 V. The inherently safe bias voltage is presented to the gate of the SiC JFET using a noncontact solid-state switch which is a biased np-n transistor. This switch is opened when the conventional gate drive circuit is operational, and turns off the safe bias controller, removing the load from the linear regulator to prevent unnecessary power loss. The test results of the safety lockout circuit in the converter are shown in Fig. 18(a) and (b). The rst waveform is the output voltage of the linear regulator. The second and the third waveforms are oscillator and buckboost output voltages, respectively. From the zoom in waveforms in Fig. 18(b), the oscillation frequency is 1.8 MHz. The last waveform is the gate input voltage of the SiC JFET. From Fig. 18(a), the startup delay to get to pinch-off voltage of 17 V is about 120 s. From Fig. 19, the JFET energy dissipation is about 1 J at 120 s. Since the destructive energy of the JFET is 60 J/cm2 [49], 120 s is fast enough to prevent damage even if a very high voltage is instantaneously applied across the SiC JFETs with no power for the normal gate drive. The energy dissipated in JFETs is related to the value of inductance of the dc busbar and the package parasitics. According to the inductance values of the module,

Fig. 18. Safety lockout circuit waveforms. (a) Response time of safety lockout circuit (Time: 20 s/div). (b) Safety lockout circuit performance (Time: 200 ns/div).

1474

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 3, MARCH 2013

Fig. 19.

Four paralleled SiC JFETs energy dissipation.

Fig. 20.

SiC inverter test and efciency measurement setup.

Fig. 21. Experimental waveforms of the SiC inverter at 650 Vd c , f = 60 Hz, M = 0.85 with the RL load, R = 10 and L = 1.2 mH. (Time: 5 ms/div, V a b and V b c : 700 V/div, ia and ib : 30 A/div). (a) fsw = 10 kHz. (b) fsw = 40 kHz.

the JFET energy dissipation is estimated as 250 mJ, until it is turned OFF, because the safety lockout circuits provide negative biasing to JFET gate input from 0 to 17 V gradually [50]. B. SiC Inverter Test and Efciency Measurement The liquid-cooled SiC inverter is tested with an RL load. As shown in Fig. 20, the inverter is connected to a dc power supply and feeds ac power to a three-phase RL load with Y-connection, where R = 10 and L = 1.2 mH. The switches in the inverter are controlled by space vector pulsewidth modulation signals generated by the TMX320F28035 microcontroller board. The chiller changes the coolant temperature from 25 C to 95 C. The coolant ow rate is set at 6.8 L/min with 50% ethylene glycol, 50% water at the output of the chiller. The input dc voltage, the input dc current, the three-phase line-to-line voltage, and the line current are monitored and measured by the oscilloscope, Tektronix DPO7104. The power conversion efciency and the quality of the inverted ac power are monitored and measured using Yokogawa WT3000 Precision Power Analyzer with an accuracy of 0.02%. For ac side, three-phase three-wire power measurement method is used, and dc-side power is obtained by multiplying dc voltage and current. Some of the experimental waveforms of line-to-line output voltage (Vab and Vb c ) and output current (ia and ib ) at coolant

temperature of 25 C are shown in Fig. 21. The input voltage in the gure is 650 Vdc . The frequency of the output current is 60 Hz, and its magnitude is set by a modulation index of 0.85. Fig. 21(a) shows the waveforms with 10-kHz switching frequency. When the switching frequency is increased to 40 kHz, as Fig. 21(b) shows, the line current is distorted at zero crossing because the xed dead time of 2 s between high-side and low-side switches is relatively large compared to the switching period 25 s. The measured temperature difference between the coolant and the thermistor on the substrate inside the module is shown in Fig. 22. The maximum coolant temperature is limited by the operation temperature of the dc link. The difference between the coolant temperature and the substrate temperature is about 4 C and 13 C at 5-kW output power, at fsw = 10 kHz and fsw = 40 kHz, respectively. As Fig. 23 shows, the inverter efciencies are measured at up to 11.4-kW output power with different switching frequencies from 10 to 40 kHz, at 60-Hz fundamental output frequency, 25 C coolant temperature, and 0.85 modulation index. The power loss at the gate driver board, which is 5 to 8.5 W depending on the switching frequency, is included in the efciency measurement. The efciency curves are measured by changing the dc input voltage with the xed RL load. The maximum

XU et al.: DEVELOPMENT OF A SiC JFET-BASED SIX-PACK POWER MODULE FOR A FULLY INTEGRATED INVERTER

1475

Fig. 25. Efciency variation with coolant temperature changes at 5-kW output power and different switching frequencies.

Fig. 22. Measured substrate temperatures at different coolant temperatures at 5-kW output power.

Fig. 24. The conversion efciency degradation at coolant temperature of 95 C is less than 0.2% compared to the measured data at 25 C. Considering the thermal resistance from JFET junction to inlet coolant of 2.62 C/W, the estimated JFET junction temperature is 113.6 C at 10-kW output power, 10-kHz switching frequency, and 95 C coolant temperature. The conversion efciencies are measured with the different switching frequencies at xed 5-kW output power over coolant temperatures, as shown in Fig. 25. No signicant efciency degradation is observed. When the coolant temperature increases at 40-kHz switching frequency, the conversion efciency is improved because the switching loss, which is about two times of the conduction loss [43], reduces at higher junction temperature. The degradation of the efciency is expected at higher temperature over 150 C and low switching frequency range, because the conduction loss will dominate the switching loss of SiC JFETs in this operation regime. VI. CONCLUSION A SiC JFET-based three-phase inverter power module with 200 C packaging is designed and demonstrated. Each switching element consists of four paralleled normally-on SiC JFETs with two antiparallel SiC SBDs. Basic switching cell theory is used to reduce package parasitics. The stability of the module assembly processes is conrmed. The module static characteristics are tested up to 200 C, and the switching performance is evaluated by the DPT up to 150 C, at 650-V voltage and 60-A current. In addition, the inuences of phase-leg shoot-through, including JFET internal capacitance, package parasitic inductance, and junction temperature, are analyzed. The key parasitics are parasitic inductances in JFET gate loop and module dc bus. The results show the low loss of SiC JFET-based three-phase power module even at high temperature, and the increase of conduction loss and decrease of switching loss with temperature increasing. Meanwhile, the signicance of shoot-through protection and package parasitics reduction for the SiC JFET module is pointed out. A liquid-cooled inverter based on this power module is developed and demonstrated for EV/HEV applications. The safety lockout circuits successfully protects the normally-on JFETs from shoot-through by providing a negative bias from dc-link

Fig. 23. Efciency of the SiC inverter at 25 C coolant temperature, different output power levels, and switching frequencies.

Fig. 24. Efciency of the SiC inverter at 10-kHz switching frequency, different output power levels, and coolant temperatures.

98.5% efciency including the 5-W gate driver power loss is achieved at a switching frequency of 10 kHz at 5-kW output power, 450-V dc voltage, with the power factor 0.73. The inverter conversion efciencies with different coolant temperatures at 10-kHz switching frequency are shown in

1476

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 3, MARCH 2013

voltage within the safe power dissipation range. The efciency of the inverter is 98.5% at 10-kHz switching frequency at 5-kW output power. The inverter was successfully demonstrated at up to 95 C coolant temperature. These show the benets by using the SiC JFET-based power module in EV/HEV applications. REFERENCES
[1] M. Helsper and B. Brendel, Challenges for IGBT modules in hybrid buses, in Proc. Eur. Conf. Power Electron. Appl., Barcelona, Spain, Sep. 2009, pp. 18. [2] R. John, O. Vermesan, and R. Bayerer, High temperature power electronics IGBT modules for electrical and hybrid vehicles, in Proc. Int. Microelectron. Packag. Soc. High Temp. Electron. Netw., Oxford, U.K., Sep. 2009, pp. 199204. [3] Z. Xu, M. Li, F. Wang, and Z. Liang, Investigation of Si IGBT operation at 200 C for traction application, in Proc. IEEE Energy Conv. Cong. Expo., Phoenix, AZ, Sep. 2011, pp. 23972404. [4] Z. Xu, D. Jiang, M. Li, P. Ning, F. Wang, and Z. Liang, Si IGBT phase-leg module packaging and cooling design for operation at 200 C in hybrid electrical vehicle applications, in Proc. IEEE Appl. Power Electron. Conf. Expo., Orlando, FL, Feb. 2012, pp. 483490. [5] J. Lai, W. Yu, H. Qian, P. Sun, P. Ralston, and K. Meehan, High temperature device characterization for hybrid electric vehicle traction inverters, in Proc. IEEE Appl. Power Electron. Conf. Expo., Washington, DC, Feb. 2009, pp. 665670. [6] P. Sun, J. Lai, C. Liu, and W. Yu, A 55 kW three-phase inverter based on hybrid-switch soft-switching modules for high-temperature hybrid electric vehicle drive application, IEEE Trans. Ind. Appl., vol. 48, no. 3, pp. 962 969, May/Jun. 2012. [7] B. Wrzecionko, J. Biela, and J. K. Kolar, SiC power semiconductors in HEVs: Inuence of junction temperature on power density, chip utilization and efciency, in Proc. IEEE Ind. Electron. Annu. Conf., Porto, Portugal, Nov. 2009, pp. 38343841. [8] R. Lai, F. Wang, R. Burgos, Y. Pei, D. Boroyevich, B. Wang, T. A. Lipo, V. D. Immanuel, and K. J. Karimi, A system topology evaluation methodology for high-density three-phase PWM ACAC converters, IEEE Trans. Power Electron., vol. 23, no. 6, pp. 26652680, Nov. 2008. [9] B. Shi, G. Venkataramanan, and N. Sharma, Design considerations for reactive elements and control parameters for three phase boost rectiers, in Proc. IEEE Int. Conf. Electr. Mach. Drives, May 2005, pp. 17571764. [10] Z. Liang, B. Lu, J. D. van Wyk, and F. C. Lee, Integrated CoolMOS FET/SiC-diode module for high performance power switching, IEEE Trans. Power Electron., vol. 20, no. 3, pp. 679686, May 2005. [11] B. Ozpineci, M. S. Chinthavali, L. M. Tolbert, A. S. Kashyap, and H. A. Mantooth, A 55-kW three-phase inverter with Si IGBTs and SiC Schottky diodes, IEEE Trans. Ind. Appl., vol. 45, no. 1, pp. 278285, Jan./Feb. 2009. [12] K. Ishikawa, K. Ogawa, H. Onose, N. Kameshiro, and M. Nagasu, Traction inverter that applies hybrid module using 3-kV SiC-SBDs, in Proc. 2010 Int. Power Electron. Conf., Sapporo, Japan, Jun. 2010, pp. 3266 3270. [13] T. W. Franke and F. W. Fuchs, Comparison of switching and conducting performance of SiC-JFET and SiC-BJT with a state of the art IGBT, in Proc. Eur. Conf. Power Electron. Appl., Barcelona, Spain, Sep. 2009, pp. 110. [14] M. Chinthavali, P. Ning, Y. Cui, and L. M. Tolbert, Investigation on the parallel operation of discrete SiC BJTs and JFETs, in Proc. IEEE Appl. Power Electron. Conf. Expo., Fort Worth, TX, Mar. 2011, pp. 10761083. [15] R. A. Wood and T. E. Salem, Evaluation of a 1200-V, 800-A all-SiC dual module, IEEE Trans. Power Electron., vol. 26, no. 9, pp. 25042511, Sep. 2011. [16] D. Grider, M. Das, S. Leslie, J. Ostop, R. Raju, M. Schutten, and A. Hefner, 10 kV/120 A SiC DMOSFET half H-Bridge power modules for 1 MVA solid state power substation, in Proc. IEEE Electr. Ship Technol. Symp., Alexandria, VA, Apr. 2011, pp. 131134. [17] L. D. Stevanovic, K. S. Matocha, P. A. Losee, J. S. Glaser, J. J. Nasadoski, and S. D. Arthur, Recent advances in silicon carbide MOSFET power devices, in Proc. IEEE Appl. Power Electron. Conf. Expo., Palm Springs, CA, Feb. 2010, pp. 401407. [18] J. Richmond, S. Leslie, B. Hull, M. Das, A. Agarwal, and J. Palmour, Roadmap for megawatt class power switch modules utilizing large area silicon carbide MOSFETs and JBS diodes, in Proc. Energy Convers. Congr. Expo., San Jose, CA, Sep. 2009, pp. 106111.

[19] T. E. Salem, D. P. Urciuoli, R. Green, and G. K. Ovrebo, Hightemperature high-power operation of a 100 A SiC DMOSFET module, in Proc. IEEE Appl. Power Electron. Conf. Expo., Washington, DC, Feb. 2009, pp. 653657. [20] K. Sheng, Y. Zhang, M. Su, J. H. Zhao, X. Li, P. Alexandrov, and L. Fursin, Demonstration of the rst SiC power integrated circuit, Solid State Electron., vol. 52, no. 10, pp. 16361646, Oct. 2008. [21] M. Gurnkel, H. D. Xiong, K. P. Cheung, J. S. Suehle, J. B. Bernstein, Y. Shapira, A. J. Lelis, D. Habersat, and N. Goldsman, Characterization of transient gate oxide trapping in SiC MOSFETs using fast I-V techniques, IEEE Trans. Electron Devices, vol. 55, no. 8, pp. 20042012, Aug. 2008. [22] C. Buttay, D. Planson, B. Allard, D. Bergogne, P. Bevilacqua, C. Joubert, M. Lazar, C. Martin, H. Morel, D. Tournier, and C. Raynaud, State of the art of high temperature power electronics, in Proc. Microtherm., Lodz, Poland, Sep. 2009, pp. 110. [23] B. Reese, B. McPherson, R. Shaw, J. Hornberger, R. Schupbach, A. Lostetter, B. Rowden, A. Mantooth, S. Ang, J. Balda, K. Okumura, and T. Otsuka, High temperature (250 C) silicon carbide power modules with integrated gate drive boards, in Proc. Int. Microelectron. Packag. Soc. Int. Conf. Exhib. High Temp. Electron., Albuquerque, NM, May 2010, pp. 297304. [24] K. Takao, T. Shinohe, S. Harada, K. Fukuda, and H. Ohashi, Evaluation of a SiC power module using low-on-resistance IEMOSFET and JBS for high power density power converters, in Proc. IEEE Appl. Power Electron. Conf. Expo., Palm Springs, CA, Feb. 2010, pp. 20302035. [25] T. Funaki, J. C. Balda, J. Junghans, A. S. Kashyap, H. A. Mantooth, F. Barlow, T. Kimoto, and T. Hikihara, Power conversion with SiC devices at extremely high ambient temperatures, IEEE Trans. Power Electron., vol. 22, no. 4, pp. 13211329, Jul. 2007. [26] P. Ning, T. G. Lei, F. Wang, G. Q. Lu, and K. D. T. Ngo, A novel hightemperature planar package for SiC multichip phase-leg power module, IEEE Trans. Power Electron., vol. 25, no. 8, pp. 20592067, Aug. 2010. [27] H. Zhang, M. Chinthavali, L. M. Tolbert, J. H. Han, and F. Barlow, 18 kW three phase inverter system using hermetically sealed SiC phase-leg power modules, in Proc. IEEE Appl. Power Electron. Conf. Expo., Palm Springs, CA, Feb. 2010, pp. 11081112. [28] D. Bergogne, H. Morel, D. Planson, D. Tournier, P. Bevilacqua, B. Allard, R. Meuret, S. Vieillard, S. Ra el, and F. MeibodyTabar, Towards an airborne high temperature SiC inverter, in Proc. IEEE Power Electron. Spec. Conf., Rhodes, Greece, Jun. 2008, pp. 31783183. [29] J. M. Hornberger, E. Cilio, B. McPherson, R. M. Schupbach, A. B. Lostetter, and H. A. Mantooth, A fully integrated 300 C, 4 kW, 3-phase, SiC motor drive module, in Proc. IEEE Power Electron. Spec. Conf., Orlando, FL, Jun. 2007, pp. 10481053. [30] K. Sheng, Maximum junction temperatures of SiC power devices, IEEE Trans. Electron. Devices, vol. 56, no. 2, pp. 337342, Feb. 2009. [31] C. Buttay, C. Raynaud, H. Morel, G. Civrac, M. L. Locatelli, and F. Morel, Thermal stability of silicon carbide power diodes, IEEE Trans. Electron Devices, vol. 59, no. 3, pp. 761769, Mar. 2012. [32] R. W. Johnson, C. Wang, Y. Liu, and J. D. Scoeld, Power device packaging technologies for extreme environments, IEEE Trans. Electron. Packag. Manuf., vol. 30, no. 3, pp. 182193, Jul. 2007. [33] S. Li, L. M. Tolbert, F. Wang, and F. Z. Peng, P-cell and N-cell based IGBT module: Layout design, parasitic extraction, and experimental verication, in Proc. IEEE Appl. Power Electron. Conf., Fort Worth, TX, Mar. 610, 2011, pp. 372378. [34] Q3D Extractor Online Help. (2011). [Online]. Available: http://www. ansoft.com/products/si/q3d_extractor [35] C. Martin, J. Guichon, J. Schanen, and R. Pasterczyk, Gate circuit layout optimization of power module regarding transient current imbalance, IEEE Trans. Power Electron., vol. 21, no. 5, pp. 11761184, Sep. 2006. [36] T. Ruemenapp and D. Peier, Investigation of the ageing performance of AlN-ceramic used in high-power-semiconductors, in Proc. 8th Int. Conf. Dielectr. Mater., Meas. Appl., Edinburgh, U.K., Sep. 2000, pp. 285290. [37] Y. Kurihara, S. Takahashi, S. Ogihara, and T. Kurosu, Bonding mechanism between aluminum nitride substrate and Ag-Cu-Ti solder, IEEE Trans. Compon., Hybrids, Manuf. Technol., vol. 15, no. 3, pp. 361368, Jun. 1992. [38] S. Kulkarni, S. Arifeen, B. Patterson, G. Potirniche, A. Elshabini, and F. Barlow, Evaluation of ceramic substrates for high power and high temperature applications, in Proc. Ceram. Interconnect Ceram. Microsys. Technol., San Diego, CA, Apr. 2011, pp. 199206. [39] S. Kulkarni, F. Barlow, A. Elshabini, and R. Edgeman, SiC&GaN die attach for extreme environment electronics, in Proc. Int. Microelectron. Packag. Conf., Providence, RI, Nov. 2008, pp. 11191125.

XU et al.: DEVELOPMENT OF A SiC JFET-BASED SIX-PACK POWER MODULE FOR A FULLY INTEGRATED INVERTER

1477

[40] B. Patterson, A. Elshabini, and F. Barlow, Evaluation of direct bond aluminum substrates for power electronic applications in extreme environments, presented at the Ceram. Interconnect Ceram. Microsys. Technol., Erfurt, Germany, Apr. 2012. [41] G. Rao, S. Kulkarni, F. Barlow, and A. Elshabini, Encapsulation of power modules for extreme environments, in Proc. 2009 Int. Microelectron. Packag. Conf., San Jose, CA, Nov. 2009, pp. 678685. [42] T. J. Han, J. Nagashima, S. J. Kim, S. Kulkarni, and F. Barlow, High density 50 kW SiC inverter systems using a JFETs based six-pack power module, in Proc. 8th Int. Conf. Power Electron.ECCE Asia, Jeju, Korea, May/Jun. 2011, pp. 764769. [43] D. Jiang, R. Burgos, F. Wang, and D. Boroyevic, Temperature dependent characteristics of SiC devices: Performance evaluation and loss calculation, IEEE Trans. Power Electron., vol. 27, no. 2, pp. 10131024, Feb. 2012. [44] S. Round, M. Heldwein, J. W. Kolar, I. Hofsajer, and P. Friedrichs, A SiC JFET driver for a 5 kW, 150 kHz three-phase PWM converter, in Proc. IEEE Ind. Appl. Conf., Hong Kong, Oct. 2005, pp. 410416. [45] Inneon. (2012). [Online]. Available: http://www.inneon.com [46] A. G. Black, Impact of source inductance on synchronous buck regulator FET shoot through performance, in Proc. IEEE Power Electron. Spec. Conf., Orlando, FL, Jun. 2007, pp. 981986. [47] T. Funaki, A. S. Kashyap, H. A. Mantooth, J. C. Balda, F. D. Barlow, T. Kimoto, and T. Hikihara, Characterization of SiC JFET for temperature dependent device modeling, in Proc. IEEE Power Electron. Spec. Conf., Jeju, Korea, Jun. 2006, pp. 16. [48] Z. Chen, Characterization and modeling of high-switching-speed behavior of SiC active devices, M.S. Thesis, Blacksburg, VA, 2009. [49] N. Boughrara, S. Moumen, S. Lefebvre, Z. Khatir, P. Friedrichs, and J. C. Faugi` eres, Robustness of SiC JFET in short-circuit modes, IEEE Electron Device Lett., vol. 30, no. 1, pp. 5153, Jan. 2009. [50] F. Dubois, D. Bergogne, D. Risaletto, R. Robutel, H. Morel, R. Meuret, and S. Dhokkar, High temperature inverter for airborne application, in Proc. Int. Microelectron. Packag. Soc. Int. Conf. Exhib. High Temp. Electron., Albuquerque, NM, May 2010, pp. 222227.

Dong Jiang (S05M12) received the B.S and M.S degrees in electrical engineering from Tsinghua University, Beijing, China, in 2005 and 2007, respectively. He began his Ph.D. study in the Center for Power Electronics (CPES) in Virginia Tech in 2007, and in 2010 he was transferred to the University of Tennessee, Knoxville to continue his research and received the Ph.D. degree there in 2011. He has been with United Technologies Research Center (UTRC) since Jan. 2012 as a Senior Research Scientist/Engineer. His research interests include high performance motor control, multi-phase PWM converter design and control, EMI, power electronics devices, and magnetic bearings.

Fan Xu (S09) received the B.S. and M.S. degrees in electrical engineering from Tsinghua University, Beijing, China, in 2007 and 2009, respectively. He is currently working toward the Ph.D. degree at the University of Tennessee, Knoxville. His research interests include SiC power device application, three-phase current source converters, three-phase converter design, and analysis for high efciency applications.

Leon M. Tolbert (S88M91SM98) received the Bachelors, M.S., and Ph.D. degrees in electrical engineering from the Georgia Institute of Technology, Atlanta, in 1989, 1991, and 1999, respectively. He worked at Oak Ridge National Laboratory, Oak Ridge, TN, from 1991 until 1999. He was appointed as an Assistant Professor with the Department of Electrical and Computer Engineering, The University of Tennessee, Knoxville, in 1999. He is currently the Min Kao Professor in the Department of Electrical Engineering and Computer Science, The University of Tennessee. He is the UTK Campus Director for the National Science Foundation/Department of Energy Research Center, CURENT (Center for Ultra-wide-area Resilient Electric Energy Transmission Networks). He is also a Senior Research Engineer with the Power Electronics and Electric Machinery Research Center, Oak Ridge National Laboratory. In 2010, he was a Visiting Professor at Zhejiang University, Hangzhou, China. Dr. Tolbert is a Registered Professional Engineer in the state of Tennessee. He received an NSF CAREER Award in 2001, the 2001 IEEE Industry Applications Society Outstanding Young Member, and three prize paper awards from the IEEE Industry Applications Society and the IEEE Power Electronics Society. From 2003 to 2006, he was the Chairman of the Education Activities Committee of the IEEE Power Electronics Society and an Associate Editor for the IEEE POWER ELECTRONICS LETTERS. He was an Associate Editor of the IEEE TRANSACTIONS ON POWER ELECTRONICS from 2007 to 2012. He was elected to serve as a Member-At-Large to the IEEE Power Electronics Society Advisory Committee for 20102012 and is presently the Chair of the Membership Committee for the society.

Timothy Junghee Han (M11) received the B.S. and M.S. degrees in electrical engineering from Busan National University, Busan, South Korea, and the Ph.D. degree in electrical engineering from Korea Advanced Institute of Science and Technology (KAIST), South Korea. He is a Senior Manager of Global Power Electronics, Inc. (GPE). He has 20 years experience in semiconductor devices, SiC power devices and packaging, optical components and packaging, and simulation of the power electronics systems. Currently, he leads the design and development of the advanced power electronics subsystems using SiC devices for the next generation hybrid electric vehicles (HEV) and alternative energy industry at GPE, and collaborates with university professors and leading R&D institutions. He was a visiting scholar at the Power Electronics Lab at the University of Tennessee at Knoxville and National Transportation Research Center of Oak Ridge National Laboratory. He has authored 22 technical journal papers, 12 patents, and made 11 presentations at prestigious international conferences.

Fei (Fred) Wang (S85M91SM99F10) received the B.S. degree from Xian Jiaotong University, Xian, China, and the M.S. and Ph.D. degrees from the University of Southern California, Los Angeles, in 1982, 1985, and 1990, respectively, all in electrical engineering. He was a Research Scientist in the Electric Power Lab, University of Southern California, from 1990 to 1992. In 1992, he joined the GE Power Systems Engineering Department, Schenectady, NY, as an Application Engineer. From 1994 to 2000, he was a Senior Product Development Engineer with GE Industrial Systems, Salem, VA. During 2000 to 2001, he was the Manager of Electronic and Photonic Systems Technology Lab, GE Global Research Center, Schenectady, NY and Shanghai, China. In 2001, he joined the Center for Power Electronics Systems (CPES) at Virginia Tech, Blacksburg, VA as a Research Associate Professor and became an Associate Professor in 2004. From 2003, he also served as the CPES Technical Director. Since 2009, he has been with The University of Tennessee and Oak Ridge National Lab, Knoxville, TN as a Professor and Condra Chair of Excellence in Power Electronics. He is a founding member and Technical Director of the multi-university NSF/DOE Engineering Research Center for Ultra-wide-area Resilient Electric Energy Transmission Networks (CURENT) led by The University of Tennessee. His research interests include power electronics, power systems, controls, electric machines, and motor drives.

1478

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 3, MARCH 2013

James Nagashima (M98) received the B.S. degree in electrical engineering from California University, Long Beach, in 1969 and the Masters degree in business administration, in 1983. He has over 30 years of experience in the eld of power electronics. He retired from General Motors in June 2009. During his career at General Motors he was a GM Technical Fellow and Manager of Advanced Engineering for General Motors Powertrain Advanced Technology Center in Torrance, CA. He is currently the Director of Technology Strategy for Global Power Electronics, Inc., and is responsible for developing SiC based power electronics and related technologies. He was responsible for developing advanced concepts in power electronics, motor drives, and controls for GMs electric, hybrid and fuel cell vehicle programs. His past research projects included wide bandgap power modules, advanced thermal methods for power electronics such as phase change cooling and double-sided cooling, die attachment processes, inverter and converter development from 30 kW to 250 kW. He holds 55 patents in the eld of power electronics, controls, and electric machines. He has published many journal and conference papers on advanced motor drives and electronics. He is currently a reviewer for the Department of Energy Vehicle Technologies Program annual merit review in the areas of power electronics and motors.

Srikanth Kulkarni graduated with an M.S. degree in electrical and computer engineering from the University of Idaho, with a major in the eld of Microelectronic Packaging. He worked in Idaho Microelectronics Laboratory at the University of Idaho from 2006 to 2011 and is currently working at Micron Technology Inc., Idaho.

Sung Joon Kim received the B.S., M.S., and Ph.D. degrees in electrical engineering from the California Institute of Technology, and the MBA degree from Purdue University, West Lafayette, IN. He is experienced in bringing out new ideas and technologies from R&D labs, productizing them and building successful businesses from them. He was a Founder and General Manager of Transponder Business Group, while at Lucent Technologies, and brought out a new optical subsystem products from R&D ideas in Bell Labs into commercial market. After leaving Lucent Technologies, he co-founded CENIX creating business from high tech ideas in telecom industry. He is also a Founder and Managing Partner of Global Opportunities Fund, a Venture Capital company, that incubates and funds early stage companies. He is Founder, President, and CEO of Global Power Electronics, Inc. He is especially interested in creating values and startup companies in power electronics industry based on novel and game changing technologies and ideas, such as SiC based power electronics products.

Fred Barlow (M96SM10) received the B.S. degree in physics and applied physics from Emory University, Georgia, and the M.S. and Ph.D. degrees in electrical engineering from Virginia Tech. He is currently serving as a Professor and the Department Chair for Electrical and Computer Engineering at the University of Idaho. He worked for several universities including Virginia Tech and the University of Arkansas, where he held the position of Associate Department Head. He has served as the major Professor for thirty graduate students, and served as PI or Co-PI on more than $5 million of funded research. He has authored over one hundred and twenty publications, and is coeditor of the Handbook of Thin Film Technology (McGraw Hill, 1998), as well as the Handbook of Ceramic Interconnect Technology (CRC Press, 2007). Dr. Barlow is a Fellow Member of the International Microelectronics and Packaging Society (IMAPS).